Datasheet

DS2762 High-Precision Li+ Battery Monitor With Alerts
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Table 2. Memory Map
ADDRESS (HEX) DESCRIPTION READ/WRITE
00 Protection Register R/W
01 Status Register R
02–06 Reserved
07 EEPROM Register R/W
08 Special Feature Register R/W
09–0B Reserved
0C Voltage Register MSB R
0D Voltage Register LSB R
0E Current Register MSB R
0F Current Register LSB R
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
12–17 Reserved
18 Temperature Register MSB R
19 Temperature Register LSB R
1A–1F Reserved
20–2F EEPROM, block 0 R/W*
30–3F EEPROM, block 1 R/W*
40–7F Reserved
80 SRAM (Optional Accumulated Current Interrupt
High Threshold MSB)
R/W
81 SRAM (Optional Accumulated Current Interrupt
High Threshold LSB)
R/W
82 SRAM (Optional Accumulated Current Interrupt
Low Threshold MSB)
R/W
83 SRAM (Optional Accumulated Current Interrupt
Low Threshold LSB)
R/W
84 SRAM (Optional Temperature Interrupt High
Threshold)
R/W
85 SRAM (Optional Temperature Interrupt Low
Threshold)
R/W
86-8F SRAM R/W
90–FF Reserved
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give conditional
control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when corresponding
protection conditions occur and remain set until cleared by the host system. The default values of the CE and DE
bits of the protection register are stored in lockable EEPROM in the corresponding bits in address 30h. A recall
data command for EEPROM block 1 recalls the default values into CE and DE. Figure 10 shows the format of the
protection register. The function of each bit is described in detail in the following paragraphs.
Figure 10. Protection Register Format
ADDRESS 00
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OV UV COC DOC
CC DC
CE DE