Datasheet

DS2762 High-Precision Li+ Battery Monitor With Alerts
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OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition.
This bit must be reset by the host system.
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an undervoltage
condition. This bit must be reset by the host system.
COC—Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a charge-
direction overcurrent condition. This bit must be reset by the host system.
DOC—Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a discharge-
direction overcurrent condition. This bit must be reset by the host system.
CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE—Charge Enable. Writing a 0 to this bit disables charging (
CC output high, external charge FET off) regardless
of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the presence of any
protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to active
mode.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (
DC output high, external discharge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to override by the presence
of any protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to
active mode.
STATUS REGISTER
The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of address
31h. A recall data command for EEPROM block 1 recalls the default values into the status register bits. The format
of the status register is shown in Figure 11. The function of each bit is described in detail in the following
paragraphs.
Figure 11. Status Register Format
ADDRESS 01
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
X X PMOD RNAOP SWEN IE X X
X—Reserved Bits.
PMOD—Sleep Mode Enable. A value of 1 in this bit enables the DS2762 to enter sleep mode when the DQ line
goes low for greater than 2s and to leave sleep mode when the DQ line goes high. A value of 0 disables DQ-
related transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5
of address 31h. The factory default is 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address command to
33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should be set in bit 4 of
address 31h. The factory default is 0.
SWEN—SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP command. If
set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of address 31h. This bit is
read-only. The factory default is 0.
IE—Interrupt Enable. A value of 1 in this bit location enables the PIO pin to be used as an interrupt to the host
system when either the user-programmed thresholds for Accumulated Current and Temperature are met or
exceeded. If set to 0, the PIO pin performs as noted in the PIO section. This bit is read-only. The desired default
value should be set in bit 2 of address 31h. The factory default is 0.