Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - telecommunication Parallel, Serial PBGA 256

1 of 133 REV: 092706

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

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FEATURES

 Operates as M13 or E13 Multiplexer or as

Stand-Alone T3 or E3 Framer

 Flexible Multiplexer can be Programmed for

Multiple Configurations Including:

M13 Multiplexing (28 T1 Lines into a T3

Data Stream)

E13 Multiplexing (16 E1 Lines into an E3

Data Stream)

E1 to T3 Multiplexing (21 E1 Lines into a T3

Data Stream)

 Two T1/E1 Drop and Insert Ports

 Supports T3 C-Bit Parity Mode

 B3ZS/HDB3 Encoder and Decoder

 Generates and Detects T3/E3 Alarms

 Generates and Detects T2/E2 Alarms

 Integrated HDLC Controller Handles LAPD

Messages Without Host Intervention

 Integrated FEAC Controller

 Integrated BERT Supports Performance

Monitoring

 T3/E3 and T1/E1 Diagnostic (Tx to Rx), Line

(Rx to Tx), and Payload Loopback

Supported

 Nonmultiplexed or Multiplexed 16-Bit

Control Port (with Optional 8-Bit Mode)

 3.3V Supply with 5V Tolerant I/O

 Available in 256-Pin 1.27mm Pitch PBGA

Package

 IEEE 1149.1 JTAG Support

DS3112

TEMPE T3/E3 Multiplexe

3.3V T3/E3 Framer and M13/E13/G.747 Mux

FUNCTIONAL DIAGRAM

APPLICATIONS

Wide Area Network Access Equipment

PBXs

Access Concentrators

Digital Cross-Connect Systems

Switches

Routers

Optical Multiplexers

ADMs

Test Equipment

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS3112

0°C to +70°C

256 PBGA

DS3112+

0°C to +70°C

256 PBGA

DS3112N

-40°C to +85°C

256 PBGA

DS3112N+

-40°C to +85°C

256 PBGA

+Denotes lead-free/RoHS-compliant package.

www.maxim-ic.com

T1/E1

T3/E3

T2/E2

DS3112

Summary of content (133 pages)

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DS3112 TEMPE T3/E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 Mux www.maxim-ic.
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DS3112 TABLE OF CONTENTS 1 DETAILED DESCRIPTION 1.1 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 2 4.3.1 4.3.2 4.4 CPU BUS SIGNAL DESCRIPTION .................................................................................................19 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION ...........................................................................21 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION ...................................................................
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DS3112 7.6 7.7 8 BERT 8.1 9 T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION .................................................75 T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION ......................................................76 78 BERT REGISTER DESCRIPTION ..................................................................................................78 HDLC CONTROLLER 9.1 9.2 9.2 9.3 87 RECEIVE OPERATION ..............................................................................
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DS3112 14.8 E13 BASICS .............................................................................................................................128 14.9 E2 FRAMING STRUCTURE AND E12 MULTIPLEXING ....................................................................129 14.10 E3 FRAMING STRUCTURE AND E23 MULTIPLEXING ................................................................129 14.11 G.747 BASICS .........................................................................................................
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DS3112 LIST OF FIGURES Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode) ................................................................... 11 Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)................................................................... 12 Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) ............................................................. 13 Figure 2-1. T3/E3 Receive Framer Timing .........................................
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DS3112 LIST OF TABLES Table 2-1. Pin Naming Convention............................................................................................................................ 14 Table 2-2. Pin Description ......................................................................................................................................... 14 Table 2-3. Mode Select Decode ................................................................................................................................
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DS3112 1 DETAILED DESCRIPTION The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer. When the device is used as a multiplexer, it can be operated in one of three modes: M13—Multiplex 28 T1 lines into a T3 data stream E13—Multiplex 16 E1 lines into an E3 data stream G.747—Multiplex 21 E1 lines into a T3 data stream See Figure 1-1, Figure 1-2, and Figure 1-3 for block diagrams of these three modes.
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DS3112 1.1 Applicable Standards 1) American National Standard for Telecommunications - ANSI T1.107 – 1995 “Digital Hierarchy Formats Specification” 2) American National Standard for Telecommunications - ANSI T1.231 - 199X – Draft “Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring” 3) American National Standard for Telecommunications - ANSI T1.
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DS3112 1.2 Main DS3112 TEMPE Features 1.2.
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DS3112 1.2.6 BERT Can generate and detect the pseudorandom patterns of 27 - 1, 211 - 1, 215 - 1 and QRSS as well as repetitive patterns from 1 to 32 bits in length BERT is a global chip resource that can be used either in the T3/E3 data path or in any one of the T1 or E1 data paths Large error counter (24 bits) allows testing to proceed for long periods without Host intervention Errors can be inserted into the generated BERT patterns for diagnostic purposes 1.2.
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Signal Inversion HRNEG HRPOS T2 Framer 2 7 Error Counters CPU Interface & Global Configuration (Routed to All Blocks) FRMECU CA0 to CD0 to CWR* CRD* CCS* CALE CIM CA7 CD15 (CR/W*) (CDS*) 11 of 133 Receive T1 Loop Timed Mode T1 Diagnostic Loopback T1 Line Loopback Transmit Signal Inversion Control To BERT To BERT To BERT To BERT 1 FIFO 1 to 7 Demux AIS Gen.
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Signal Inversion HRNEG HRPOS FRMECU CA0 to CD0 to CWR* CRD* CCS* CALE CIM CA7 CD15 (CR/W*) (CDS*) E2 Framer 2 3 4 Error Counters CPU Interface & Global Configuration (Routed to All Blocks) 12 of 133 Receive E1 Loop Timed Mode E1 Diagnostic Loopback E1 Line Loopback Transmit Signal Inversion Control To BERT To BERT To BERT 1 To BERT 1 to 4 Demux FIFO FEAC Controller AIS Gen.
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Signal Inversion HRNEG HRPOS G747 Framer 2 7 Error Counters CPU Interface & Global Configuration (Routed to All Blocks) FRMECU CA0 to CD0 to CWR* CRD* CCS* CALE CIM CA7 CD15 (CR/W*) (CDS*) 13 of 133 Receive E1 Loop Timed Mode E1 Diagnostic Loopback E1 Line Loopback Transmit Signal Inversion Control To BERT 1 To BERT 1 to 7 Demux To BERT FEAC Controller FIFO HDLC Controller with 256 Byte Buffer FAS / RAI / Sn / AIS Generation BERT Insert BERT Insert Signal Inversion Control BERT Inse
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DS3112 2 PIN DESCRIPTION This section describes the input and output signals on the DS3112. Signal names follow a convention that is shown in Table 2-1. Table 2-2 lists all the signals, their signal type, description, and pin location. Table 2-1.
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DS3112 PIN D5 TYPE I A9 B9 C9 C8 B8 A7 A8 A10 B10 C10 C11 A11 NAME CRD(CDS) CWR (CR/W) FRCLK FRD FRDEN FRLOF FRLOS FRMECU FRSOF FTCLK FTD FTDEN FTMEI FTSOF B6 G.
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DS3112 PIN W14 Y16 Y17 U16 V18 V19 V20 T20 R20 N18 M18 L18 K18 H20 K1 M1 N1 P2 P4 T3 U3 W3 U5 W5 W6 Y7 U9 W10 W11 V12 Y14 W15 W16 Y18 Y19 W20 T17 T19 R19 P20 M17 L19 K19 J18 K3 L3 NAME LRCLK15 LRCLK16 LRCLK17 LRCLK18 LRCLK19 LRCLK20 LRCLK21 LRCLK22 LRCLK23 LRCLK24 LRCLK25 LRCLK26 LRCLK27 LRCLK28 LRCLKA LRCLKB LRDAT1 LRDAT2 LRDAT3 LRDAT4 LRDAT5 LRDAT6 LRDAT7 LRDAT8 LRDAT9 LRDAT10 LRDAT11 LRDAT12 LRDAT13 LRDAT14 LRDAT15 LRDAT16 LRDAT17 LRDAT18 LRDAT19 LRDAT20 LRDAT21 LRDAT22 LRDAT23 LRDAT24 LRDAT25 LRDAT26
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DS3112 PIN G19 P1 R2 U1 T4 V3 V4 V5 U7 W7 Y8 Y9 Y11 W12 V13 V14 V15 W17 W18 Y20 U18 T18 P17 P19 N20 M20 K20 J19 H18 L2 M3 N3 P3 T2 V1 W1 W4 Y4 V6 V7 W8 W9 Y10 Y12 W13 Y15 NAME LTCCLK LTCLK1 LTCLK2 LTCLK3 LTCLK4 LTCLK5 LTCLK6 LTCLK7 LTCLK8 LTCLK9 LTCLK10 LTCLK11 LTCLK12 LTCLK13 LTCLK14 LTCLK15 LTCLK16 LTCLK17 LTCLK18 LTCLK19 LTCLK20 LTCLK21 LTCLK22 LTCLK23 LTCLK24 LTCLK25 LTCLK26 LTCLK27 LTCLK28 LTCLKA LTCLKB LTDAT1 LTDAT2 LTDAT3 LTDAT4 LTDAT5 LTDAT6 LTDAT7 LTDAT8 LTDAT9 LTDAT10 LTDAT11 LTDAT12 LTDAT13 LTD
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DS3112 PIN U14 V16 V17 W19 U19 U20 R18 P18 N19 M19 L20 J20 H19 L1 M2 NAME LTDAT16 LTDAT17 LTDAT18 LTDAT19 LTDAT20 LTDAT21 LTDAT22 LTDAT23 LTDAT24 LTDAT25 LTDAT26 LTDAT27 LTDAT28 LTDATA LTDATB TYPE I I I I I I I I I I I I I I I FUNCTION Low-Speed (T1 or E1) Transmit Data for Port 16 Low-Speed (T1 or E1) Transmit Data for Port 17 Low-Speed (T1 or E1) Transmit Data for Port 18 Low-Speed (T1 or E1) Transmit Data for Port 19 Low-Speed (T1 or E1) Transmit Data for Port 20 Low-Speed (T1 or E1) Transmit Data fo
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DS3112 2.2 CPU Bus Signal Description Signal Name: CMS Signal Description: CPU Bus Mode Select Signal Type: Input This signal should be tied low when the device is to be operated as a 16-bit bus. This signal should be tied high when the device is to be operated as an 8-bit bus.
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DS3112 Signal Name: CINT Signal Description: CPU Bus Interrupt Signal Type: Output (Open Drain) This signal is an open-drain output that will be forced low if one or more unmasked interrupt sources within the device is active. The signal will remain low until either the interrupt is serviced or masked. Signal Name: CCS Signal Description: CPU Bus Chip Select Signal Type: Input This active low signal must be asserted for the device to accept a read or write command from an external host.
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DS3112 2.3 T3/E3 Receive Framer Signal Description Signal Name: FRSOF Signal Description: T3/E3 Receive Framer Start Of Frame Sync Signal Signal Type: Output This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary (Figure 2-1). This signal can be configured via the FRSOFI control bit in Master Control Register 3 (Section 4.2) to be either active high (normal mode) or active low (inverted mode).
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DS3112 Signal Name: FRLOS Signal Description: T3/E3 Receive Framer Loss Of Signal Signal Type: Output This signal will be forced high when the receive T3/E3 framer is in a Loss Of Signal (LOS) state. It will remain high as long as the LOS state persists and will return low when the framer exits the LOS state. See Section 5.3 for details on the set and clear criteria for this signal. LOS status is also available via a software bit in the T3/E3 Status Register (Section 5.3).
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DS3112 2.4 T3/E3 Transmit Formatter Signal Description Signal Name: FTSOF Signal Description: T3/E3 Transmit Formatter Start Of Frame Sync Signal Signal Type: Output/Input This signal can be configured via the FTSOFC control bit in Master Control Register 1 to be either an output or an input. When this signal is an output, it pulses for one FTCLK period to indicate a T3 or E3 frame boundary (Figure 2-2). When this signal is an input, it is sampled to set the transmit T3 or E3 frame boundary (Figure 2-2).
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DS3112 Signal Name: FTMEI Signal Description: T3/E3 Transmit Formatter Manual Error Insert Strobe Signal Type: Input Via the EIC control bit in the T3/E3 Error Insert Control Register (Section 5.2), the DS3112 can be configured to use this asynchronous input to cause errors to be inserted into the transmitted data stream. A zero to one transition on this input causes the device to begin the process of causing errors to be inserted.
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DS3112 2.5 Low-Speed (T1 or E1) Receive Port Signal Description Signal Name: LRDAT1 to LRDAT28 Signal Description: Low-Speed (T1 or E1) Receive Serial Data Outputs Signal Type: Output These output signals present the demultiplexed serial data for the 28 T1 data streams or the 16/21 E1 data streams. Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of the associated LRCLK.
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DS3112 Signal Name: LRCCLK Signal Description: Low-Speed (T1 or E1) Receive Common Clock Input Signal Type: Input If enabled via the LRCCEN control bit in Master Control Register 1 (Section 4.2), all 28 LRCLK or 16/21 LRCLK can be slaved to this common clock input. In T3 mode, LRCCLK would be a 1.544MHz clock and in E3 mode, LRCCLK would be 2.048MHz.
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DS3112 Signal Name: LTDATA/LTDATB Signal Description: Low-Speed (T1 or E1) Transmit Insert Port Serial Data Inputs Signal Type: Input These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any of the 16/21 E1 data streams (Section 7.4). Data can be clocked into the device either on falling edges (normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK.
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DS3112 2.7 High-Speed (T3 or E3) Receive Port Signal Description Signal Name: HRPOS/HRNEG Signal Description: High-Speed (T3 or E3) Receive Serial Data Inputs Signal Type: Input These input signals sample the serial data from the incoming T3 data streams or E3 data streams. Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of the associated HRCLK. This option is controlled via the HRCLKI control bit in Master Control Register 2 (Section 4.
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DS3112 2.9 JTAG Signal Description Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this signal should be pulled high. Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial Data Input Signal Type: Input (with internal 10kΩ pullup) Test instructions and data are clocked into this signal on the rising edge of JTCLK.
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DS3112 Signal Name: T3E3MS Signal Description: T3/E3 Mode Select Input Signal Type: Input This signal determines whether the DS3112 will operate in either the T3 mode or the E3 mode. It acts as a global control bit for the entire DS3112. This signal should be set into the proper state before a hardware reset is issued via the RST signal. This input is coupled with the G.747E input to create a special test mode whereby all the outputs are tri-stated (Table 2-3). 0 = T3 Mode 1 = E3 Mode Signal Name: G.
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DS3112 3 MEMORY MAP Table 3-1.
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DS3112 ADDRESS 82 84 86 88 90 92 38, 48, 64, 66, 68, 94, 96, 98, 0E, 1A, 1C, 1E, 2C, 2E, 3A, 3C, 3E, 4A, 4C, 4E, 6A, 6C, 8A, 8C, 8E, 9A, 9C, 9E ACRONYM RHDLC THDLC HSR IHSR FCR FSR R/W R W R R/W R/W R — — REGISTER NAME Receive HDLC FIFO Register Transmit HDLC FIFO Register HDLC Status Register Interrupt Mask Register for HSR FEAC Control Register FEAC Status Register Not Assigned *Addresses A0 to FF are not assigned. 32 of 133 SECTION 9.2 9.2 9.3 9.3 10.1 10.
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DS3112 4 MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT 4.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to one, all of the internal registers will be placed into their default state, which is 0000h. A reset can also be invoked by the RST hardware signal. The upper byte of the MRID register is read-only and it can be read by the host to determine the chip revision.
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DS3112 4.2 Master Configuration Registers Description Register Name: Register Description: Register Address: MC1 Master Configuration Register 1 02h Bit # Name Default 7 FTSOFC 0 6 LOTCMC 0 5 UNI 0 4 MECU 0 3 AECU 0 2 CBEN 0 1 UNCHEN 0 0 ZCSD 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 LLTM 0 10 DENMS 0 9 LRCCEN 0 8 LTCCEN 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Zero Code Suppression Disable (ZCSD).
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DS3112 Bit 4: Manual Error Counter Update (MECU). A zero to one transition on this bit will cause the device to update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit must be cleared and set again for a subsequent update. This bit is logically ORed with the external FRMECU hardware input signal. After this bit has toggled, the host must wait at least 100ns before reading the error counters to allow the device time to complete the update.
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DS3112 Register Name: Register Description: Register Address: Bit # Name Default 7 — — Bit # Name Default 15 — — MC2 Master Configuration Register 2 04h 6 — — 14 — — 5 HTDATL 0 13 — — 4 HTDATH 0 12 — — 3 HRDATI 0 2 HRCLKI 0 1 HTDATI 0 0 HTCLKI 0 11 LRDATI 0 10 LRCLKI 0 9 LTDATI 0 8 LTCLKI 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: HTCLK Invert Enable (HTCLKI).
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DS3112 Register Name: Register Description: Register Address: MC3 Master Configuration Register 3 06h Bit # Name Default 7 FRSOFI 0 6 FRCLKI 0 5 FRDI 0 4 FRDENI 0 3 FTSOFI 0 2 FTCLKI 0 1 FTDI 0 0 FTDENI 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: FTDEN Invert Enable (FTDENI).
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DS3112 4.3 Master Status and Interrupt Register Description 4.3.1 Status Registers The status registers in the DS3112 allow the host to monitor the real-time condition of the device. Most of the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits within the device are latched to ensure that the host can detect changes in state and the true status of the device. There are three types of status bits in the DS3112.
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DS3112 Figure 4-3. Real-Time Status Bit Internal Signal Status Bit Interrupt Read 4.3.2 MSR The Master Status Register (MSR) is a special status register that can be used to help the host quickly locate changes in device status. There is a status bit in the MSR for each of the major blocks within the DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur.
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DS3112 determine the change of state. This bit will be cleared when the BERTEC0 is read and will not be set again until the BERT has experienced another change of state. The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the BERTEC0 register is read (Figure 4-4). Bit 3: Change in HDLC Status (HDLC).
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DS3112 device detects a clock at FTCLK. The HRCLK checks for the presence of the FTCLK. On reset, both the LOTC and LORC status bits will be set and then immediately cleared if the clock is present. Bit 11: Loss Of Receive Clock Detected (LORC). This read-only real-time status bit will be set to a one when the device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock is detected at the HRCLK input.
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DS3112 Figure 4-5.
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DS3112 Figure 4-6.
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DS3112 Figure 4-7.
PAGE 45
DS3112 Figure 4-9.
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DS3112 Register Name: Register Description: Register Address: IMSR Interrupt Mask for Master Status Register 0Ah Bit # Name Default 7 — — 6 T2E2SR2 0 5 T2E2SR1 0 4 FEAC 0 3 HDLC 0 2 BERT 0 1 COVF 0 0 OST 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 LORC 0 10 LOTC 0 9 T3E3SR 0 8 T1LB 0 Bit 0: One-Second Timer Boundary Occurrence (OST). 0 = interrupt masked 1 = interrupt unmasked Bit 1: Counter Overflow Event (COVF).
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DS3112 4.4 Test Register Description Register Name: Register Description: Register Address: TEST Test Register 0Ch Bit # Name Default 7 — — 6 — — 5 FT5 0 4 FT4 0 3 FT3 0 2 FT2 0 1 FT1 0 0 FT0 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 — — Bits 0 to 5: Factory Test Bits (FT0 to FT5). These bits are used by the factory to place the DS3112 into the test mode. For normal device operation, these bits should be set to zero whenever this register is written to.
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DS3112 5 T3/E3 FRAMER On the receive side, the T3/E3 framer locates the frame boundaries of the incoming T3 or E3 data stream and monitors the data stream for alarms and errors. Alarms are detected and reported in T3/E3 Status Register (T3E3SR) and the T3/E3 Information Register (T3E3INFO), which are described in Section 5.3. Errors are accumulated in a set of error counters (Section 5.4). The host can force the T3/E3 framer to resynchronize via the T3E3RSY control bit in the MRID register (Section 4.1).
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DS3112 5.4 T3/E3 Framer Control Register Description Register Name: Register Description: Register Address: Bit # Name Default 7 DLB 0 Bit # Name Default 15 — — T3E3CR T3/E3 Control Register 10h 6 LLB 0 5 T3IDLE 0 4 E3SnC1 0 14 PLB 0 13 TFEBE 0 12 AFEBED 0 3 E3SnC0 0 11 ECC 0 2 TPT 0 10 FECC1 0 1 TRAI 0 0 TAIS 0 9 FECC0 0 8 E3CVE 0 Bit 0: T3/E3 Transmit Alarm Indication Signal (TAIS).
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DS3112 Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See Figure 1-1 and Figure 1-2 for a visual description of this loopback. 0 = disable loopback 1 = enable loopback Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations (BPV) or Code Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of a HDB3 codeword.
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DS3112 Register Name: Register Description: Register Address: T3E3EIC T3/E3 Error Insert Control Register 18h Bit # Name Default 7 MEIMS 0 6 FBEIC1 0 5 FBEIC0 0 4 FBEI 0 3 T3CPBEI 0 2 T3PBEI 0 1 EXZI 0 0 BPVI 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 — — Bit 0: BiPolar Violation Insert (BPVI). A zero to one transition on this bit will cause a single BPV to be inserted into the transmit data stream.
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DS3112 Bits 5 and 6: Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1). FBEIC1 FBEIC0 TYPE OF FRAMING BIT ERROR INSERTED T3 Mode: A single F-bit error E3 Mode: A single FAS word of 1111000000 is generated instead of the normal FAS 0 0 word, which is 1111010000 (i.e., only 1 bit inverted) T3 Mode: A single M-bit error 0 1 E3 Mode: A single FAS word of 0000101111 is generated instead of the normal FAS word, which is 1111010000 (i.e.
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DS3112 5.5 T3/E3 Framer Status and Interrupt Register Description Register Name: Register Description: Register Address: T3E3SR T3/E3 Status Register 12h Bit # Name Default 7 — — 6 RSOF — 5 TSOF — 4 T3IDLE — 3 RAI — 2 AIS — 1 LOF — 0 LOS — Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 — — Note: See Figure 5-1 for details on the signal flow for the status bits in the T3E3SR register. Bits that are underlined are read-only. All others are read-write.
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DS3112 Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. Bit 6: Receive T3/E3 Start Of Frame (RSOF). This latched read-only event status bit will be set to a one on each T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and it will be cleared when read.
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DS3112 Register Name: Register Description: Register Address: IT3E3SR Interrupt Mask for T3/E3 Status Register 14h Bit # Name Default 7 — — 6 RSOF 0 5 TSOF 0 4 T3IDLE 0 3 RAI 0 2 AIS 0 1 LOF 0 0 LOS 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Loss Of Signal Occurrence (LOS). 0 = interrupt masked 1 = interrupt unmasked Bit 1: Loss Of Frame Occurrence (LOF).
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DS3112 Table 5-1. T3 Alarm Criteria ALARM/ CONDITION AIS DEFINITION Alarm Indication Signal Properly framed 1010... pattern, which is aligned with the 1 just after each overhead bit and all C bits are set to zero LOS Loss Of Signal (Note 2) LOF Loss Of Frame Too many F bits or M bits in error RAI (Note 1) Remote Alarm Indication (This is also referred to as SEF/AIS in Bellcore GR820) Inactive: X1 = X2 = 1 Active: X1 = X2 = 0 Properly framed 1100...
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DS3112 Table 5-2.
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DS3112 Bit 5: Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will be set to a one each time the DS3112 has detected either three or more F bits in error out of 16 consecutive F bits (T3 mode) or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will not be set again until the device detects another SEFE event. Bit 8: E3 National Bit (E3Sn). This read-only real-time status bit reports the incoming E3 National Bit (Sn).
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DS3112 5.6 T3/E3 Performance Error Counters There are six error counters in the DS3112. All of the errors counters are 16 bits in length. The host has three options as to how these errors counters are updated. The device can be configured to automatically update the counters once a second or manually via either an internal software bit (MECU) or an external signal (FRMECU). See Section 4.2 for details. All the error counters saturate when full and will not rollover.
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DS3112 Register Name: Register Description: Register Address: FECR Frame Error Count Register 24h Bit # Name Default 7 FE7 — 6 FE6 — 5 FE5 — 4 FE4 — 3 FE3 — 2 FE2 — 1 FE1 — 0 FE0 — Bit # Name Default 15 FE15 — 14 FE14 — 13 FE13 — 12 FE12 — 11 FE11 — 10 FE10 — 9 FE9 — 8 FE8 — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15: 16-Bit Framing Bit Error Counter (FE0 to FE15).
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DS3112 Register Name: Register Description: Register Address: CPCR T3 C-Bit Parity Bit Error Count Register 28h Bit # Name Default 7 CPE7 — 6 CPE6 — 5 CPE5 — 4 CPE4 — 3 CPE3 — 2 CPE2 — 1 CPE1 — 0 CPE0 — Bit # Name Default 15 CPE15 — 14 CPE14 — 13 CPE13 — 12 CPE12 — 11 CPE11 — 10 CPE10 — 9 CPE9 — 8 CPE8 — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15: 16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15).
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DS3112 6 M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME Note that if the DS3112 is used as a stand-alone T3/E3 framer and the multiplexer functionality is disabled, then the registers and functionality described in this section are not applicable and should be ignored by the host. On the receive side, the T2/E2/G.747 framer locates the frame boundaries of the incoming T2/E2/G.747 data stream and monitors the data stream for alarms and errors.
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DS3112 Register Name: Register Description: Register Address: T2E2CR2 T2/E2 Control Register 2 32h Bit # Name Default 7 — — 6 LOFG7 0 5 LOFG6 0 4 LOFG5 0 3 LOFG4 0 2 LOFG3 0 1 LOFG2 0 0 LOFG1 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 E2Sn4 — 10 E2Sn3 — 9 E2Sn2 — 8 E2Sn1 — Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 6: T2/E2/G.747 Transmit Loss Of Frame Generation (LOFGn where n = 1 to 7).
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DS3112 6.3 T2/E2/G.747 Framer Status and Interrupt Register Description Register Name: Register Description: Register Address: T2E2SR1 T2/E2 Status Register 1 34h Bit # Name Default 7 IELOF 0 6 LOF7 - 5 LOF6 - 4 LOF5 - 3 LOF4 - 2 LOF3 - 1 LOF2 - 0 LOF1 - Bit # Name Default 15 IEAIS 0 14 AIS7 - 13 AIS6 - 12 AIS5 - 11 AIS4 - 10 AIS3 - 9 AIS2 - 8 AIS1 - Note: See Figure 6-1 for details on the signal flow for the status bits in the T2E2SR1 register.
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DS3112 Figure 6-1.
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DS3112 Register Name: Register Description: Register Address: T2E2SR2 T2/E2 Status Register 2 36h Bit # Name Default 7 IERAI 0 6 RAI7 — 5 RAI6 — 4 RAI5 — 3 RAI4 — 2 RAI3 — 1 RAI2 — 0 RAI1 — Bit # Name Default 15 E2SOF4 — 14 E2SOF3 — 13 E2SOF2 — 12 E2SOF1 — 11 E2Sn4 — 10 E2Sn3 — 9 E2Sn2 — 8 E2Sn1 — Note: See Figure 6-2 for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all other bits are read-write.
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DS3112 Table 6-1.
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DS3112 6.4 T1/E1 AIS Generation Control Register Description Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ports or the 16/21 E1 ports. On reset, the device will force AIS in both the transmit and receive paths and it is up to the host to modify the T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the DS3112.
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DS3112 Register Name: Register Description: Register Address: T1E1TAIS1 T1/E1 Transmit Path AIS Generation Control Register 1 44h Bit # Name Default 7 AIS8 0 6 AIS7 0 5 AIS6 0 4 AIS5 0 3 AIS4 0 2 AIS3 0 1 AIS2 0 0 AIS1 0 Bit # Name Default 15 AIS16 0 14 AIS15 0 13 AIS14 0 12 AIS13 0 11 AIS12 0 10 AIS11 0 9 AIS10 0 8 AIS9 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15: Transmit AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2).
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DS3112 7 T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY On the T1 and E1 ports, the DS3112 has loopback capability in both directions. There is a per-port line loopback that loops the receive side back to the transmit side and a per-port diagnostic loopback that loops the transmit side back to the receive side. In addition, the device can detect the T1 line loopback command as well as generate it.
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DS3112 7.5 T1/E1 Loopback Control Register Description Register Name: Register Description: Register Address: T1E1LLB1 T1/E1 Line Loopback Control Register 1 50h Bit # Name Default 7 LLB8 0 6 LLB7 0 5 LLB6 0 4 LLB5 0 3 LLB4 0 2 LLB3 0 1 LLB2 0 0 LLB1 0 Bit # Name Default 15 LLB16 0 14 LLB15 0 13 LLB14 0 12 LLB13 0 11 LLB12 0 10 LLB11 0 9 LLB10 0 8 LLB9 0 Note: Bits that are underlined are read-only; all other bits are read-write.
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DS3112 Register Name: Register Description: Register Address: T1E1DLB1 T1/E1 Diagnostic Loopback Control Register 1 54h Bit # Name Default 7 DLB8 0 6 DLB7 0 5 DLB6 0 4 DLB5 0 3 DLB4 0 2 DLB3 0 1 DLB2 0 0 DLB1 0 Bit # Name Default 15 DLB16 0 14 DLB15 0 13 DLB14 0 12 DLB13 0 11 DLB12 0 10 DLB11 0 9 DLB10 0 8 DLB9 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15: T1/E1 Diagnostic Loopback Enable for Ports 1 to 16 (DLB1 to DLB16).
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DS3112 Register Name: Register Description: Register Address: T1LBCR1 T1 Line Loopback Command Register 1 58h Bit # Name Default 7 LB8 0 6 LB7 0 5 LB6 0 4 LB5 0 3 LB4 0 2 LB3 0 1 LB2 0 0 LB1 0 Bit # Name Default 15 LB16 0 14 LB15 0 13 LB14 0 12 LB13 0 11 LB12 0 10 LB11 0 9 LB10 0 8 LB9 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15: T1 Line Loopback Far End Activate Command for Ports 1 to 16 (LB1 to LB16).
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DS3112 Register Name: Register Description: Register Address: T1LBCR2 T1 Line Loopback Command Register 2 5Ah Bit # Name Default 7 LB24 0 6 LB23 0 5 LB22 0 4 LB21 0 3 LB20 0 2 LB19 0 1 LB18 0 0 LB17 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 LB28 0 10 LB27 0 9 LB26 0 8 LB25 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 17 to 28: T1 Line Loopback Far End Activate Command for Ports 17 to 28 (LB17 to LB28).
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DS3112 7.6 T1 Line Loopback Command Status Register Description Register Name: Register Description: Register Address: T1LBSR1 T1 Line Loopback Command Status Register 1 5Ch Bit # Name Default 7 LLB8 — 6 LLB7 — 5 LLB6 — 4 LLB5 — 3 LLB4 — 2 LLB3 — 1 LLB2 — 0 LLB1 — Bit # Name Default 15 LLB16 — 14 LLB15 — 13 LLB14 — 12 LLB13 — 11 LLB12 — 10 LLB11 — 9 LLB10 — 8 LLB9 — Note: See Figure 7-1 for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2 registers.
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DS3112 Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow LLB1 (T1LBSR1 Bit 0) Internal T1 Loopback Command Signal from T2/E2 Framer LLB2 (T1LBSR1 Bit 1) Internal T1 Loopback Command Signal from T2/E2 Framer T1LB Status Bit (MSR Bit 8) OR INT* Hardware Signal Mask LLB28 (T1LBSR2 Bit 11) Internal T1 Loopback Command Signal from T2/E2 Framer T1LB (IMSR Bit 8) 7.
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DS3112 Register Name: Register Description: Register Address: T1E1SIP T1/E1 Select Register for Transmit Insert Ports A and B 62h Bit # Name Default 7 — — 6 — — 5 — — 4 IPAS4 0 3 IPAS3 0 2 IPAS2 0 1 IPAS1 0 0 IPAS0 0 Bit # Name Default 15 — — 14 — — 13 — — 12 IPBS4 0 11 IPBS3 0 10 IPBS2 0 9 IPBS1 0 8 IPBS0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 4: T1/E1 Insert Port A Select Bits (IPAS0 to IPAS4).
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DS3112 8 BERT The BERT block can generate and detect the following patterns: 7 11 15 • Pseudorandom patterns 2 - 1, 2 - 1, 2 - 1, and QRSS • A repetitive pattern from 1 to 32 bits in length • Alternating (16-bit) words that flip every 1 to 256 words The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts on detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters. See Section 8.
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DS3112 Bits 8 to 12: Transmit BERT Port Select Bits 0 to 4 (TBPS0 to TBPS4). These bits determine if the transmit BERT will be used to replace the normal transmit data on any of the 28 T1 or 16/21 E1 transmit ports or at the T3/E3 transmit formatter. If these bits are set to 11101, data from the transmit BERT is only placed in the payload bit positions of the T3/E3 data stream.
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DS3112 Register Name: Register Description: Register Address: BERTC0 BERT Control Register 0 70h Bit # Name Default 7 PBS 0 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit # Name Default 15 IESYNC 0 14 IEBED 0 13 IEOF 0 12 n/a - 11 RPL3 0 10 RPL2 0 9 RPL1 0 8 RPL0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Force Resynchronization (RESYNC).
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DS3112 Bits 8 to 11: Repetitive Pattern Length Bits 5 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32.
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DS3112 Register Name: Register Description: Register Address: BERTC1 BERT Control Register 1 72h Bit # Name Default 7 EIB2 — 6 EIB1 0 5 EIB0 0 4 SBE 0 3 — 0 2 — 0 1 — 0 0 TC 0 Bit # Name Default 15 AWC7 0 14 AWC6 0 13 AWC5 0 12 AWC4 0 11 AWC3 0 10 AWC2 0 9 AWC1 0 8 AWC0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Transmit Pattern Load (TC).
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DS3112 Register Name: Register Description: Register Address: BERTRP0 BERT Repetitive Pattern 0 (lower word) 74h Bit # Name Default 7 RP7 0 6 RP6 0 5 RP5 0 4 RP4 0 3 RP3 0 2 RP2 0 1 RP1 0 0 RP0 0 Bit # Name Default 15 RP15 0 14 RP14 0 13 RP13 0 12 RP12 0 11 RP11 0 10 RP10 0 9 RP9 0 8 RP8 0 Register Name: Register Description: Register Address: BERTRP1 BERT Repetitive Pattern 1 (upper word) 76h Bit # Name Default 7 RP23 0 6 RP22 0 5 RP21 0 4 RP20 0 3 RP19 0 2 RP18 0 1 RP17 0 0
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DS3112 Register Name: Register Description: Register Address: BERTBC0 BERT 32-Bit Bit Counter (lower word) 78h Bit # Name Default 7 BBC7 0 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bit # Name Default 15 BBC15 0 14 BBC14 0 13 BBC13 0 12 BBC12 0 11 BBC11 0 10 BBC10 0 9 BBC9 0 8 BBC8 0 Register Name: Register Description: Register Address: BERTBC1 BERT 32-Bit Bit Counter (upper word) 7Ah Bit # Name Default 7 BBC23 0 6 BBC22 0 5 BBC21 0 4 BBC20 0 3 BBC19 0 2 BBC
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DS3112 Register Name: Register Description: Register Address: BERTEC0 BERT 24-Bit Error Counter (lower) and Status Information 7Ch Bit # Name Default 7 — — 6 RA1 — 5 RA0 — 4 RLOS — 3 BED — 2 BBCO — 1 BECO — 0 SYNC — Bit # Name Default 15 BEC7 0 14 BEC6 0 13 BEC5 0 12 BEC4 0 11 BEC3 0 10 BEC2 0 9 BEC1 0 8 BEC0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Real-Time Synchronization Status (SYNC).
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DS3112 Figure 8-1.
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DS3112 9 HDLC CONTROLLER The DS3112 contains an on-board HDLC controller with 256-byte buffers in both the transmit and receive paths. When the device is operated in the T3 mode, the HDLC controller is only active in the CBit Parity mode. When the device is operated in the E3 mode, the user has the option to connect the HDLC controller to the Sn bit position. On the receive side, the HDLC controller is always connected to the receive E3 framer.
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DS3112 then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR) status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the host. The transmit HDLC has been designed to minimize its real-time host support requirements.
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DS3112 Bit 5: Transmit HDLC Reset (THR). A zero to one transition will reset the Transmit HDLC controller. Must be cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit FIFO and cause one FEh abort sequence (7 ones is a row) to be sent followed by either 7Eh (flags) or FFh (idle) until a new packet is initiated by writing new data (at least 2 bytes) into the FIFO. Bit 6: Receive HDLC Reset (RHR).
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DS3112 Register Name: Register Description: Register Address: RHDLC Receive HDLC FIFO 82h Bit # Name Default 7 D7 — 6 D6 — 5 D5 — 4 D4 — 3 D3 — 2 D2 — 1 D1 — 0 D0 — Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 PS1 — 10 PS0 — 9 CBYTE — 8 OBYTE — Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always read the lower byte (bits 0 to 7) first followed by the upper byte (bits 8 to 15).
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DS3112 Register Name: Register Description: Register Address: THDLC Transmit HDLC FIFO 84h Bit # Name Default 7 D7 0 6 D6 0 5 D5 0 4 D4 0 3 D3 0 2 D2 0 1 D1 0 0 D0 0 Bit # Name Default 15 — — 14 — — 13 — — 12 — — 11 — — 10 — — 9 — — 8 TMEND 0 Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always write to the lower byte (bits 0 to 7) first followed by the upper byte (bits 8 to 15). Note 2: The THDLC is a write-only register.
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DS3112 Bit 4: Receive FIFO High Watermark (RHWM). This read-only real-time status bit will be set to a one when the receive FIFO contains more than the number of bytes configured by the Receive High Watermark Setting control bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO empties below the high watermark.
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DS3112 (i.e., the FIFO has been read from and then allowed to fill up again). The setting of this bit can cause a hardware interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read. Bit 14: Receive FIFO Empty (REMPTY).
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DS3112 Figure 9-1.
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DS3112 Register Name: Register Description: Register Address: IHSR Interrupt Mask for HDLC Status Register 88h Bit # Name Default 7 TUDR 0 6 RPE 0 5 RPS 0 4 RHWM 0 3 — — 2 TLWM 0 1 — — 0 TEND 0 Bit # Name Default 15 RABT 0 14 — — 13 ROVR 0 12 — — 11 — — 10 — — 9 — — 8 — — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Transmit Packet End (TEND). 0 = interrupt masked 1 = interrupt unmasked Bit 2: Transmit FIFO Low Watermark (TLWM).
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DS3112 10 FEAC CONTROLLER The DS3112 contains an onboard FEAC controller. When the device is operated in the T3 mode, the FEAC controller is only active in the C-Bit Parity Mode. When the device is operated in the E3 mode, the user has the option to connect the FEAC controller to the Sn bit position. On the receive side, the FEAC controller is always connected to the receive E3 framer.
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DS3112 Bits 6 and 7: Transmit FEAC Codeword Select Bits 0 and 1 (TFS0 and TFS1). These two bits control what two available codewords should be generated. Both TFS0 and TFS1 are edge triggered. To change the action, the host must go back to the null state (TFS0 = TFS1 = 0) before proceeding to the desired action. Wait a minimum of (10) codewords before changing to out-of-idle state.
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DS3112 10.2 FEAC Status Register Description Register Name: Register Description: Register Address: FSR FEAC Status Register 92h Bit # Name Default 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 RFI — 0 RFCD — Bit # Name Default 15 RFFO — 14 RFFE — 13 RFF5 — 12 RFF4 — 11 RFF3 — 10 RFF2 — 9 RFF1 — 8 RFF0 — Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0: Receive FEAC Codeword Detected (RFCD).
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DS3112 11 JTAG The DS3112 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, IDCODE (Figure 11-1). The DS3112 contains the following items that meet the requirements set by the IEEE 1149.
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DS3112 11.1 TAP Controller State Machine Description This section describes the operation of the test access port (TAP) controller state machine (Figure 11-2). The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Figure 11-2.
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DS3112 11.1.1 Test-Logic-Reset Upon power-up of the DS3112, the TAP controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic on the DS3112 will operate normally. 11.1.2 Run-Test-Idle Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test register will remain idle. 11.1.3 Select-DR-Scan All test registers retain their previous state.
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DS3112 11.1.11 Capture-IR The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the Shift-IR state. 11.1.
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DS3112 11.2 Instruction Register and Instructions The Instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift data one stage towards the serial output at JTDO.
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DS3112 11.2.6 CLAMP All digital outputs will output data from the boundary scan parallel output while connecting the Bypass Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. 11.3 Test Registers IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register. An optional test register, the Identification register, has been included in the DS3112 design.
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DS3112 BIT SYMBOL PIN 22 23 FTD FTCLK FTSOF_ENB_ N FTSOF_OUT FTSOF_IN FTMEI HRNEG HRCLK HRPOS HTNEG HTCLK HTPOS LTCCLK LRCCLK LTCLK28 LTDAT28 LRCLK28 LRDAT28 LTCLK27 LTDAT27 LRCLK27 LRDAT27 LTCLK26 LTDAT26 LRCLK26 LRDAT26 LTCLK25 LTDAT25 LRCLK25 LRDAT25 LTCLK24 LTDAT24 LRCLK24 LRDAT24 LTCLK23 LTDAT23 LRCLK23 LRDAT23 LTCLK22 LTDAT22 LRCLK22 LRDAT22 LTCLK21 LTDAT21 LRCLK21 LRDAT21 LTCLK20 LTDAT20 B10 A10 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
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DS3112 BIT SYMBOL PIN 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 LRCLK20 LRDAT20 LTCLK19 LTDAT19 LRCLK19 LRDAT19 LTCLK18 LTDAT18 LRCLK18 LRDAT18 LTCLK17 LTDAT17 LRCLK17 LRDAT17 LTCLK16 LTDAT16 LRCLK16 LRDAT16 LTCLK15 LTDAT15 LRCLK15 LRDAT15 LTCLK14 LTDAT14 LRCLK14 LRDAT14 LTCLK13 LTDAT13 LRCLK13 LRDAT13 LTCLK12 LTDAT12 LRCLK12 LRDAT12 LTCLK11 LTDAT11 LRCLK11 LRDAT11 LTCLK10 LTDAT10
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DS3112 BIT SYMBOL PIN 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 LRDAT8 LTCLK7 LTDAT7 LRCLK7 LRDAT7 LTCLK6 LTDAT6 LRCLK6 LRDAT6 LTCLK5 LTDAT5 LRCLK5 LRDAT5 LTCLK4 LTDAT4 LRCLK4 LRDAT4 LTCLK3 LTDAT3 LRCLK3 LRDAT3 LTCLK2 LTDAT2 LRCLK2 LRDAT2 LTCLK1 LTDAT1 LRCLK1 LRDAT1 LTCLKB LTDATB LRCLKB LRDATB LTCLKA LTDATA LRCLKA LRDATA CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA
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DS3112 BIT SYMBOL PIN 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 CD13_OUT CD13_IN CD12_OUT CD12_IN CD11_OUT CD11_IN CD10_OUT CD10_IN CD9_OUT CD9_IN CD8_OUT CD8_IN CD7_OUT CD7_IN CD6_OUT CD6_IN CD5_OUT CD5_IN CD4_OUT CD4_IN CD3_OUT CD3_IN CD2_OUT CD2_IN CD1_OUT CD1_IN CD0_OUT CD0_IN G3 G3 F1 F1 F2 F2 G4 G4 F3 F3 E1 E1 E2 E2 E3 E3 D1 D1 C1 C1 E4 E4 D3 D3 D2 D2 C2 C2 196 CD_ENB_N Control bit I/O OR CONTROL BIT DESCRIPTION O I O I O
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DS3112 12 DC ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to VSS (except VDD)……………………………...-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS……………………………….………..-0.3V to +3.63V Operating Temperature Range………………………………………………………………..0°C to +70°C Storage Temperature Range………………………………………………………………-55°C to +125°C Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification Note: The typical values listed below are not production tested.
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DS3112 13 AC ELECTRICAL CHARACTERISTICS Table 13-1. AC Characteristics—Low-Speed (T1 and E1) Ports (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-1.
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DS3112 Figure 13-1.
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DS3112 Table 13-2. AC Characteristics—High-Speed (T3 and E3) Ports (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-2.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES 22.4 ns 1, 3 HRCLK/HTCLK Clock Period t1 29.
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DS3112 Table 13-3. AC Characteristics–Framer (T3 and E3) Ports (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-3.) PARAMETER SYMBOL MIN TYP MAX UNITS 22.4 ns FRCLK/FTCLK Clock Period t1 29.
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DS3112 Table 13-4. AC Characteristics—CPU Bus (Multiplexed and Nonmultiplexed) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-4, Figure 13-5, Figure 13-6, Figure 13-7, Figure 13-8, Figure 13-9, Figure 13-10, and Figure 13-11.
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DS3112 Figure 13-4. Intel Read Cycle (Nonmultiplexed) t9 CA[7:0] Address Valid Data Valid CD[15:0] t5 CWR t1 CCS t2 t3 t4 t10 CRD Figure 13-5.
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DS3112 Figure 13-6. Motorola Read Cycle (Nonmultiplexed) t9 Address Valid CA[7:0] Data Valid CD[15:0] t5 CR/W t1 CCS t2 t3 t4 t10 CDS Figure 13-7.
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DS3112 Figure 13-8. Intel Read Cycle (Multiplexed) t13 t12 CALE t11 Address Valid CA[7:0] t14 CD[15:0] Data Valid t14 CWR t5 t1 CCS t2 t3 t4 t10 CRD NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. Figure 13-9.
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DS3112 Figure 13-10. Motorola Read Cycle (Multiplexed) t13 t12 CALE t11 Address Valid CA[7:0] t14 Data Valid CD[15:0] t14 CR/W t5 t1 CCS t2 t4 t3 t10 CDS NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST. Figure 13-11.
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DS3112 Table 13-5. AC Characteristics—JTAG Test Port Interface (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-12.) PARAMETER SYMBOL MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock Low Time t2 400 ns JTCLK Clock High Time t3 400 ns JTMS/JTDI Setup Time to the t4 50 ns Rising Edge of JTCLK JTMS/JTDI Hold Time from the t5 50 ns Rising Edge of JTCLK Delay Time from the Falling Edge t6 2 50 ns of JTCLK to Data Valid on JTDO Figure 13-12.
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DS3112 Table 13-6. AC Characteristics—Reset and Manual Error Counter/Insert Signals (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.) (See Figure 13-13 .) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES RST Low Time t1 1000 ns FRMECU/FTMEI High Time t2 50 ns FRMECU/FTMEI Low Time t3 1000 ns Figure 13-13.
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DS3112 14 APPLICATIONS AND STANDARDS OVERVIEW 14.1 Application Examples Figure 14-1 and Figure 14-2 detail two possible applications of the DS3112. Figure 14-1 shows an example of a channelized T3/E3 application. It shows the DS3112 being used to multiplex and demultiplex a T3/E3 data stream into either 28 T1 data streams or 16 E1 data streams. The demultiplexed T1/E1 data streams are fed into the DS21FF42/44 16-channel T1/E1 framer and the DS21FT42 12channel T1 framer devices.
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DS3112 Figure 14-2. Unchannelized Dual T3/E3 Application DS3112 TEMPE 44.2Mbps (T3) or 34Mbps (E3) datastream PCI Bus DS3134 CHATEAU 256 Channel HDLC Controller T3/E3 Framer & M13/ E13/ G747 Mux 44.2Mbps (T3) or 34Mbps (E3) datastream DS3112 TEMPE T3/E3 Framer & M13/ E13/ G747 Mux bipolar I/F DS3150 T3/E3 Line Interface T3/E3 Line - or NRZ I/F bipolar I/F OC-3/ OC-12/ OC-48 Mux DS3150 T3/E3 Line Interface Optical I/F T3/E3 Line - or NRZ I/F OC-3/ OC-12/ OC-48 Mux Optical I/F 14.
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DS3112 14.3 T2 Framing Structure To understand the M12 function users must understand T2 framing. The T2 frame structure is made up of four subframes called M subframes (Figure 14-3). The four M subframes are transmitted one after another (...M1/M2/M3/M4/M1/M2...) to make up the complete T2 M frame data structure. Each M subframe is made up of six blocks and each block is made up of 49 bits.
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DS3112 Figure 14-3.
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DS3112 14.5 T3 Framing Structure As with M12, to understand the M23 function requires an understanding of T3 framing. The T3 frame structure is very similar to the T2 frame structure; however, it is made up of seven M subframes (see Figure 14-5). The seven M subframes are transmitted one after another (...M1/M2/M3/.../ M6/M7M1/M2...) to make up the complete T3 M frame structure. Each M subframe is made up of eight blocks and each block is made up of 85 bits.
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DS3112 14.7 C-Bit Parity Mode Unlike the M23 application that uses the C bits for stuffing, the C-Bit Parity mode assumes that a stuff bit should be placed at every opportunity and, hence, the C bits can be used for other purposes. Table 14-4 lists how the C bits are redefined in the C-Bit Parity mode. Table 14-4.
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DS3112 Figure 14-5.
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DS3112 Figure 14-6. T3 Stuff Block Structure M1 Subframe F4 Stuff Bit 1 Info Bit 2 Info Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Info Bit 7 Info Bit 8 ...... Info Bit 84 M2 Subframe F4 Info Bit 1 Stuff Bit 2 Info Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Info Bit 7 Info Bit 8 ...... Info Bit 84 M3 Subframe F4 Info Bit 1 Info Bit 2 Stuff Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Info Bit 7 Info Bit 8 ......
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DS3112 14.9 E2 Framing Structure and E12 Multiplexing The E2 frame structure is made up of four 212-bit sets (Figure 14-7). The four sets are transmitted one after another (...Set1/Set2/Set3/Set4/Set1...) to make up the complete E2 frame structure. The Frame Alignment Signal (FAS) is placed in the first 10 bits of Set 1 and is followed by the Remote Alarm Indication (RAI) bit and a National Bit (Sn). The remainder of Set 1 is filled with bits from the four tributaries.
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DS3112 Figure 14-7. E2 Frame Structure Set 1 Bit 1 FAS (1111010000) RAI Sn b11 b21 b31 b41 b12 Bit 212 ...bits from the tributaries... Set 2 Bit 1 c11 Bit 212 c21 c31 c41 ...bits from the tributaries... Set 3 Bit 1 c12 Bit 212 c22 c32 c42 c23 c33 c43 ...bits from the tributaries... Set 4 Bit 1 c13 NOTE 1: NOTE 2: NOTE 3: NOTE 4: Bit 212 s1 s2 s3 BIT 1 OF SET 1 IS TRANSMITTED FIRST. BJI TRIBUTARY BITS CJI JUSTIFICATION CONTROL BITS SJ STUFFING BITS s4 ...bits from the tributaries.
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DS3112 14.11 G.747 Basics G.747 multiplexing is a mixture of T3 and E1. It is a two-step process of merging 21 E1 lines into a single T3 line. First, three of the E1 lines are merged into a single T2 rate and then seven T2 rates are merged to form the T3 just like the normal T2 to T3 multiplexing scheme. Once the three E1 lines have been multiplexed together, the resultant 6.312Mbps data stream is treated just like a T2 data stream that contains four T1 lines. We will only discuss the G.
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DS3112 14.12 G.747 Framing Structure and E12 Multiplexing The G.747 frame structure is made up of five 168-bit sets (Figure 14-9). The five sets are transmitted one after another (...Set1/Set2/Set3/Set4/Set5/Set1...) to make up the complete G.747 frame structure. The Frame Alignment Signal (FAS) is placed in the first 9 bits of Set 1. Set 2 contains the Remote Alarm Indication (RAI) bit and a Parity Bit (PAR) as well as a reserved bit, which is fixed to a one.
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DS3112 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.1 256-Ball PBGA (56-G6002-001) 133 of 133 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.