Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - telecommunication LIU PLCC 28

1 of 28 REV: 071305

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

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GENERAL DESCRIPTION

The DS3150 performs all the functions necessary for

interfacing at the physical layer to DS3, E3, and

STS-1 lines. The receiver performs clock and data

recovery, B3ZS/HDB3 decoding, and loss-of-signal

monitoring. The transmitter encodes outgoing data

and drives standards-compliant waveforms onto 75Ω

coaxial cable. The jitter attenuator can be mapped

into the receive path or the transmit path.

APPLICATIONS

SONET/SDH and PDH Multiplexers

Digital Cross-Connects

Access Concentrators

ATM and Frame Relay Equipment

Routers

PBXs

DSLAMs

CSUs/DSUs

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS3150QN

-40°C to +85°C

28 PLCC

DS3150Q

0°C to +70°C

28 PLCC

DS3150TN

-40°C to +85°C

48 TQFP

DS3150T

0°C to +70°C

48 TQFP

FUNCTIONAL DIAGRAM

FEATURES

§ Integrated Transmitter, Receiver, and Jitter

Attenuator for DS3, E3, and STS-1

§ Performs Receive Clock/Data Recovery and

Transmit Waveshaping

§ Jitter Attenuator Can Be Placed in the Receive

Path or the Transmit Path

§ AGC/Equalizer Block Handles from 0dB to

15dB of Cable Loss

§ Interfaces to 75W Coaxial Cable at Lengths Up to

380m (DS3), 440m (E3), or 360m (STS-1)

§ Interfaces Directly to a DSX Monitor Signal

(20dB Flat Loss) Using Built-In Preamp

§ Built-In B3ZS and HDB3 Encoder/Decoder

§ Bipolar and NRZ Interfaces

§ Local and Remote Loopbacks

§ On-Board 2

- 1 and 2

- 1 Pseudorandom Bit

Sequence (PRBS) Generator and Detector

§ Line Build-Out (LBO) Control

§ Transmit Line-Driver Monitor Checks for a

Faulty Transmitter or a Shorted Output

§ Complete DS3 AIS Generator (ANSI T1.107)

§ Unframed All-Ones Generator (E3 AIS)

§ Clock Inversion for Glueless Interfacing

§ Tri-State Line Driver for Low-Power Mode and

Protection Switching Applications

§ Loss-of-Signal (LOS) Detector (ANSI T1.231

and ITU G.775)

§ Automatic Data Squelching During LOS

§ Requires Minimal External Components

§ Drop-In Replacement for TDK 78P2241/B and

78P7200L (Refer to Application Note 362)

§ Pin Compatible with TDK 78P7200

§ 3.3V Operation (5V Tolerant I/O), 110mA (max)

§ Industrial Temperature Range: -40°C to +85°C

§ Small Packaging: 28-Pin PLCC and

48-Pin TQFP

Pin Configurations appear at end of data sheet.

DS3150

3.3V, DS3/E3/STS-1 Line Interface Unit

www.maxim-ic.com

DEMO KIT AVAILABLE

Rx+

Rx-

Tx+

Tx-

RCLK

LINE IN

DS3, E3,

STS-1

LINE OU

DS3, E3,

STS-1

DS3150

LIU

RPOS

RNEG

TCLK

TPOS

TNEG

RECEIVE

CLOCK

AND DATA

TRANSMIT

CLOCK

AND DATA

Summary of content (28 pages)

PAGE 1
DEMO KIT AVAILABLE DS3150 3.3V, DS3/E3/STS-1 Line Interface Unit www.maxim-ic.com FEATURES GENERAL DESCRIPTION § The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω coaxial cable.
PAGE 2
DS3150 TABLE OF CONTENTS 1. 1.1 1.2 1.3 1.4 DETAILED DESCRIPTION.................................................................................................4 RECEIVER .................................................................................................................................... 7 TRANSMITTER .............................................................................................................................10 DIAGNOSTICS ...................................................
PAGE 3
DS3150 LIST OF FIGURES Figure 1-1. Block Diagram ...........................................................................................................4 Figure 1-2. External Connections.................................................................................................6 Figure 1-3. Receiver Jitter Tolerance...........................................................................................9 Figure 1-4. E3 Waveform Template ...........................................................
PAGE 4
DS3150 1. DETAILED DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator (Figure 1-1). The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss-of-signal. The receiver optionally performs B3ZS/HDB3 decoding and outputs the recovered data in either NRZ or bipolar format.
PAGE 5
DS3150 Table 1-A. Applicable Telecommunications Standards SPECIFICATION T1.102-1993 T1.107-1995 T1.231-1997 T1.404-1994 G.703 G.751 G.775 G.823 G.824 O.
PAGE 6
DS3150 Figure 1-2. External Connections TRANSMIT TX+ VDD 0.05µF 330W (1%) 0.01µF 0.1µF 1µF VDD 0.01µF 0.1µF 1µF 0.01µF 0.1µF 1µF VDD TX- 1:2ct VDD 3.3V POWER PLANE DS3150 RECEIVE VSS RX+ 0.05µF 1:2ct GROUND VSS 330W (1%) PLANE VSS RX- Table 1-B. Transformer Recommendations MANUFACTURER PART NO.
PAGE 7
DS3150 1.1 Receiver Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75W) through a 1:2 step-up transformer. Figure 1-2 shows the arrangement of the transformer and other recommended interface components. The device expects the incoming signal to be in B3ZS- or HDB3-coded AMI format. Optional Preamp.
PAGE 8
DS3150 For E3 LOS Assertion: 1) The ALOS circuitry detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal and mutes the data coming out of the clock and data recovery block. (24dB below nominal is in the “tolerance range” of G.775, where LOS may or may not be declared.) 2) The DLOS detector counts 175 ±75 consecutive zeros coming out of the clock and data recovery block and asserts LOS.
PAGE 9
DS3150 § A third consecutive zero (0, 0, 0) In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RNRZ causes one of the following code violations: § § § A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V) A BPV with the same polarity as the last BPV A fourth consecutive zero (0, 0, 0, 0) When RLCV is asserted to flag a BPV, the RNRZ pin outputs a 1.
PAGE 10
DS3150 1.2 Transmitter Transmit Clock. The clock applied at the TCLK input is used to clock in data on the TPOS/TNRZ and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock and must be transmission quality (i.e., ±20ppm frequency accuracy and low jitter).
PAGE 11
DS3150 Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the DM output pin. When the transmitter is tri-stated (TTS = 0), the transmit driver monitor is also disabled. The transmitter is declared to be faulty when the transmitter outputs see a load of less than about 25W. The DM pin is only available in the TQFP package. Transmitter Jitter Generation (Intrinsic).
PAGE 12
DS3150 Table 1-E. STS-1 Waveform Template TIME (UNIT INTERVALS) -0.85 £ T £ -0.68 -0.68 £ T £ 0.26 0.26 £ T £ 1.4 -0.85 £ T £ -0.36 -0.36 £ T £ 0.36 0.36 £ T £ 1.4 NORMALIZED AMPLITUDE EQUATIONS UPPER CURVE 0.03 0.5 {1 + sin[(p/2)(1 + T/0.34)]} + 0.03 0.1 + 0.61e-2.4(T - 0.26) LOWER CURVE -0.03 0.5 {1 + sin[(p/2)(1 + T/0.18)]} - 0.03 -0.03 Table 1-F.
PAGE 13
DS3150 Figure 1-4. E3 Waveform Template 1.2 1.1 17ns 1.0 0.9 8.65ns 0.8 0.7 G.703 E3 Template Output 0.6 Level (V) 0.5 12.1ns 0.4 0.3 0.2 0.1 24.5ns 0 29.1ns -0.1 -0.2 Time (ns) Table 1-G.
PAGE 14
DS3150 Figure 1-5.
PAGE 15
DS3150 1.3 Diagnostics PRBS Generator and Detector. The DS3150 contains on-board pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer testing. The device generates and detects unframed 215 - 1 (DS3 or STS-1) or 223 - 1 PRBS patterns compliant with the ITU O.151 specification. The PRBS generator is enabled through the TDS0 and TDS1 inputs (Table 2-A and Table 2-B). The PRBS detector is always enabled and reports its status on the PRBS output pin.
PAGE 16
DS3150 1.4 Jitter Attenuator The DS3150 contains an on-board jitter attenuator (JA) that can be placed in the receive path or in the transmit path or disabled. This selection is made using the RMON and TTS input pins. See Table 2-C for selection details. Figure 1-8 shows the minimum jitter attenuation for the device when the JA is enabled. Figure 1-8 also shows the jitter transfer of the receiver when the JA is disabled.
PAGE 17
DS3150 2. PIN DESCRIPTIONS Pins are listed in alphabetical order. Section 4 shows the pin configurations for both packages. Table 2-A. Pin Descriptions NAME TYPE FUNCTION DM O Active-Low Driver Monitor (Open Drain). When the transmit driver monitor detects a faulty transmitter, DM is driven low. Requires an external pullup to VDD. Not bonded out in the PLCC package. I3 (Note 2) Enhanced Feature Enable.
PAGE 18
DS3150 NAME PRBS RCLK RMON TYPE FUNCTION O3 (Note 3) PRBS Detector. The PRBS pin reports the status of the PRBS detector. The PRBS detector constantly searches for either a 215 - 1 (DS3 or STS-1) or 223 - 1 (E3) pseudorandom bit sequence. When the PRBS detector is out of synchronization, the PRBS pin is driven high. When the detector synchronizes to an incoming PRBS pattern, the PRBS pin is driven low and then pulses high, synchronous with RCLK, for each bit error detected.
PAGE 19
DS3150 NAME TYPE TDS1/ OFSEL I3 (Note 2) TESS TNEG TPOS/ TNRZ FUNCTION Transmit Data Select Bit 1/Oscillator Frequency Select. If EFE = 1, TDS1, TDS0 and TESS select the source of the transmit data (Table 2-B). If EFE = 0, TDS1 is ignored. If MCLK is wired low, TDS1 is internally pulled low, and a resistor connected between this pin (OFSEL) and ground determines the frequency of an internal oscillator. The following resistor values should be used for specific applications: E3: 6.81kW, ±2% DS3: 5.
PAGE 20
DS3150 Table 2-B. Transmit Data Selection TDS1 TDS0 0 0 1 1 1 1 0 1 0 0 1 1 TESS TRANSMIT MODE SELECTED X Transmit normal data clocked in on TPOS/TNRZ and TNEG X Transmit unframed all ones 0 or Float Transmit unframed 101010… pattern 1 Transmit DS3 AIS (Figure 1-5) 0 Transmit 223 - 1 PRBS pattern (per ITU O.151) 1 or Float Transmit 215 - 1 PRBS pattern (per ITU O.151) Note: When EFE is low, the device ignores TDS0 and TDS1 and always transmits normal data clocked in on TPOS/TNRZ and TNEG.
PAGE 21
DS3150 3. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD) Supply Voltage Range (VDD) with Respect to VSS Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.3V to 5.5V -0.3V to 3.63V -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020 Standard Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 22
DS3150 FRAMER INTERFACE TIMING (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3150Q/T, TA = -40°C to +85°C for DS3150QN/TN.) (Figure 3-1) PARAMETER RCLK/TCLK Clock Period SYMBOL t1 CONDITIONS (Note 4) (Note 5) (Note 6) (Note 4) (Note 5) (Note 6) MIN 9.0 11.6 7.7 TYP 22.4 29.1 19.3 11.2 14.5 9.6 MAX UNITS ns 13.4 17.4 11.
PAGE 23
DS3150 RECEIVER INPUT CHARACTERISTICS—DS3 AND STS-1 MODES (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3150Q/T, TA = -40°C to +85°C for DS3150QN/TN.
PAGE 24
DS3150 TRANSMITTER OUTPUT CHARACTERISTICS—DS3 AND STS-1 MODES (VDD = 3.3V ±5%, TA = 0 to +70°C for DS3150Q/T, TA = -40°C to +85°C for DS3150QN/TN.) PARAMETER DS3 Output Pulse Amplitude, LBO = 0 (Note 13) DS3 Output Pulse Amplitude, LBO = 1 (Note 13) STS-1 Output Pulse Amplitude, LBO = 0 (Note 13) STS-1 Output Pulse Amplitude, LBO = 1 (Note 13) Ratio of Positive and Negative Pulse Peak Amplitudes DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth DS3 Unframed All-Ones Power Level at 44.
PAGE 25
DS3150 4.
PAGE 26
DS3150 5. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) 28-Pin PLCC Dimensions: millimeters Thermal Information: qJA = +68°C/W DIM A A1 A2 B B1 c D D1 D2 E E1 E2 L1 N e1 CH1 MIN MAX 0.165 0.180 0.090 0.120 0.020 — 0.026 0.033 0.013 0.021 0.009 0.012 0.485 0.495 0.450 0.456 0.390 0.430 0.485 0.495 0.450 0.456 0.390 0.430 0.060 — 28 — 0.050 BSC 0.042 0.
PAGE 27
DS3150 48-Pin TQFP Dimensions: millimeters Thermal Information: qJA = +46°C/W DIM A A1 A2 D D1 E E1 L E B C 27 of 28 MIN MAX — 1.20 0.05 0.15 0.95 1.05 8.80 9.20 7.00 BSC 8.80 9.20 7.00 BSC 0.45 0.75 0.50 BSC 0.17 0.27 0.09 0.
PAGE 28
DS3150 6. REVISION HISTORY REVISION 020602 062702 072602 010703 032904 082404 DESCRIPTION Official new product release. Section 3: Electrical Characteristics: DC Characteristics table—added IDD parameter for each device mode operation (E3, T3, STS-1 supply current over temperature). Table 2-A. Signal Descriptions: “< float = Test Mode (not recommended)” was added to the LBO description for = 1. Table 2-A. Signal Descriptions: Note 1—“All I3 inputs have an internal 10kW pullup to 1.5V.