DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over up to four interleaved PDH/TDM data streams using robust, balanced, and programmable inverse multiplexing. The Interleave Bus (IBO) serial link supports seamless bidirectional interconnection with Dallas Semiconductor’s T1/E1 framers and transceivers. 10/100 IEEE 802.
DS33Z41 Quad IMUX Ethernet Mapper TABLE OF CONTENTS 1 DESCRIPTION ....................................................................................................................7 2 FEATURE HIGHLIGHTS ....................................................................................................8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 GENERAL ......................................................................................................................................
DS33Z41 Quad IMUX Ethernet Mapper 8.14 ETHERNET MAC..........................................................................................................................46 8.14.1 MII Mode .............................................................................................................................................47 8.14.2 RMII Mode ..........................................................................................................................................47 8.14.
DS33Z41 Quad IMUX Ethernet Mapper 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 BYPASS............................................................................................................................................163 EXTEST ............................................................................................................................................163 CLAMP........................................................................................................................................
DS33Z41 Quad IMUX Ethernet Mapper LIST OF FIGURES Figure 3-1. Quad T1/E1 SCT to DS33Z41 .............................................................................................................. 11 Figure 6-1. Detailed Block Diagram......................................................................................................................... 13 Figure 7-1. DS33Z41 256-Ball CSBGA Pinout........................................................................................................
DS33Z41 Quad IMUX Ethernet Mapper LIST OF TABLES Table 2-1. T1 Related Telecommunications Specifications .................................................................................... 10 Table 7-1. Detailed Pin Descriptions ....................................................................................................................... 14 Table 8-1. Clock Selection for the Ethernet (LAN) Interface ................................................................................... 24 Table 8-2.
DS33Z41 Quad IMUX Ethernet Mapper 1 DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports, and Bit Error Rate Tester (BERT).
DS33Z41 Quad IMUX Ethernet Mapper 2 2.1 FEATURE HIGHLIGHTS General • • • • • 2.2 Link Aggregation (Inverse Multiplexing) • • • • 2.
DS33Z41 Quad IMUX Ethernet Mapper 2.6 SDRAM Interface • • • • • • 2.7 MAC Interface • • • • • • • • • • • 2.
DS33Z41 Quad IMUX Ethernet Mapper 2.10 Specifications compliance The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33Z41. Table 2-1. T1 Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications RFC1662—PPP in HDLC-like Framing RFC2615—PPP over SONET/SDH X.
DS33Z41 Quad IMUX Ethernet Mapper 3 APPLICATIONS • • • Bonded Transparent LAN Service LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design. Figure 3-1. Quad T1/E1 SCT to DS33Z41 T1/E1 Framer/LIU DS21455 DS21458 DS26528 HDLC/X.
DS33Z41 Quad IMUX Ethernet Mapper 4 ACRONYMS AND GLOSSARY • • • • • • • • • BERT—Bit Error Rate Tester DCE—Data Communication Interface DTE—Data Terminating Interface FCS—Frame Check Sequence HDLC—High Level Data Link Control MAC—Media Access Control MII—Media Independent Interface RMII—Reduced Media Independent Interface WAN—Wide Area Network Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
DS33Z41 Quad IMUX Ethernet Mapper 5 MAJOR OPERATING MODES Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor control is available in Section 8.1. 6 BLOCK DIAGRAMS Figure 6-1. Detailed Block Diagram 50 or 25 Mhz Oscillator Buffer Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.
DS33Z41 Quad IMUX Ethernet Mapper 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. Table 7-1. Detailed Pin Descriptions Note: I = Input; O = Output; Ipu = Input with pullup; Oz = Output with tri-state; IO = Bidirectional pin; IOz = Bidirectional pin with tri-state.
DS33Z41 Quad IMUX Ethernet Mapper NAME PIN TYPE FUNCTION Transmit Clock (MII). Timing reference for TX_EN and TXD[3:0]. The TX_CLK frequency is 25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. TX_CLK TX_EN A8 E10 IO O TXD[0] TXD[1] TXD[2] TXD[3] B9 C9 D9 E9 O RX_CLK A10 IO RXD[0] RXD[1] RXD[2] RXD[3] B11 C11 D11 A11 I RX_DV D10 I RX_CRS/ CRS_DV C8 I RX_ERR B12 In DTE mode, this is a clock input provided by the PHY.
DS33Z41 Quad IMUX Ethernet Mapper NAME PIN TYPE FUNCTION Collision Detect (MII). Asserted by the MAC PHY to indicate that a collision is occurring. In DCE Mode this signal should be connected to ground. This signal is only valid in half duplex mode, and is ignored in full duplex mode Management Data Clock (MII). Clocks management data between the PHY and DS33Z41. The clock is derived from SYSCLKI, with a maximum frequency is 1.67MHz. The user must leave this pin unconnected in the DCE Mode.
DS33Z41 Quad IMUX Ethernet Mapper NAME RD/DS WR/RW PIN TYPE FUNCTION Read Data Strobe (Intel Mode). The DS33Z41 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. E1 I Data Strobe (Motorola Mode). Used to latch data through the microprocessor interface. DS must be low during read and write operations. Write (Intel Mode).
DS33Z41 Quad IMUX Ethernet Mapper NAME PIN TYPE FUNCTION SDRAM CONTROLLER SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6] SDATA[7] SDATA[8] SDATA[9] SDATA[10] SDATA[11] SDATA[12] SDATA[13] SDATA[14] SDATA[15] SDATA[16] SDATA[17] SDATA[18] SDATA[19] SDATA[20] SDATA[21] SDATA[22] SDATA[23] SDATA[24] SDATA[25] SDATA[26] SDATA[27] SDATA[28] SDATA[29] SDATA[30] SDATA[31] SDA[0] SDA[1] SDA[2] SDA[3] SDA[4] SDA[5] SDA[6] SDA[7] SDA[8] SDA[9] SDA[10] SDA[11] M1 L2 N1 M2 N2 N4 N3 L4 J3 M3 H3 J1 J
DS33Z41 Quad IMUX Ethernet Mapper NAME PIN TYPE SCAS H4 O SWE M4 O SDMASK[0] SDMASK[1] SDMASK[2] SDMASK[3] N6 G4 M10 M9 O SDCLKO N5 O (4mA) SYSCLKI G13 I SDCS L6 O QOVF C7 O FUNCTION SDRAM Column Address Strobe. Active-low output, used to latch the column address on the rising edge of SDCLKO. It is used with commands for Bank Activate, Precharge, and Mode Register Write. SDRAM Write Enable. This active-low output enables write operation and auto precharge. SDRAM Mask 0 to 3.
DS33Z41 Quad IMUX Ethernet Mapper NAME PIN TYPE FUNCTION POWER SUPPLIES VDD3.3 VDD1.8 VSS N.C. G5–G10, H2, H5, H6, H7–H10 D3, D2, E3, F4, J4, K4, L3, F10, E11, E12, D12, M13, L12 A9, A12, B10, C10, D1, D5, E7, E8, F6, F8, F12, F13, J5, J6, J11, J7, J8, J9, J10, K3, K5, K7, K8, K9, K10, K12 F5, F9, B8 I VDD3.3: Connect to 3.3V Power Supply I VDD1.8: Connect to 1.8V Power Supply I VSS: Connect to the Common Supply Ground — No Connection. Do not connect these pins.
DS33Z41 Quad IMUX Ethernet Mapper Figure 7-1. DS33Z41 256-Ball CSBGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 A A0 A2 A5 A8 D0 D1 D2 TX_CLK VSS RX_CLK RXD[3] VSS DCEDTES B A1 A3 A6 A9 D3 D4 D5 NC TXD[0] VSS RXD[0] RX_ERR COL_DET C CS A4 A7 RMIIMIIS D6 D7 QOVF RX_CRS TXD[1] VSS RXD[1] MDC MDIO D VSS VDD1.8 VDD1.8 JTCLK VSS MODEC[0] MODEC[1] RST TXD[2] RX_DV RXD[2] VDD1.8 REF_CLK E RD / DS WR / RW VDD1.
DS33Z41 Quad IMUX Ethernet Mapper 8 FUNCTIONAL DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86(LAPS) Mapper, SDRAM interface, Serial IBO interface, control ports, and Bit Error Rate Tester (BERT).
DS33Z41 Quad IMUX Ethernet Mapper 8.1 Processor Interface Microprocessor control of the DS33Z41 is accomplished through the 20 interface pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins. When MODEC[1:0] = 00, bus timing is in Intel mode, as shown in Figure 11-11 and Figure 11-12. When MODEC[1:0] = 01, bus timing is in Motorola mode, as shown in Figure 11-13 and Figure 11-14.
DS33Z41 Quad IMUX Ethernet Mapper 8.2 Clock Structure The DS33Z41 clocks sources and functions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be gapped. • System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A clock supply with ±100ppm frequency accuracy is suggested.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-1. Clocking for the DS33Z41 50 or 25 Mhz Oscillator Buffer Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz Microport REF_CLK TSER TCLKI1 Line 1 RCLKI1 RSER IMUX HDLC + Serial Interface TX_CLK1 MAC RMII MII CIR Arbiter RXD RX_CLK1 TXD X.
DS33Z41 Quad IMUX Ethernet Mapper 8.2.1 Serial Interface Clock Modes The Serial Interface timing is determined by the line clocks. 8.192MHz is the required clock rate for interfacing the IBO bus to Dallas Semiconductor Framers and Single-Chip Transceivers. Both the transmit and receive clocks (TCLKI and RCLKI) are inputs. 8.2.2 Ethernet Interface Clock Modes The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation.
DS33Z41 Quad IMUX Ethernet Mapper 8.3 Resets and Low-Power Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the GL.CR1. RST bit) to their default values and resets all the other flops to their reset values. The device should be reset after all power supplies, SYSCLKI, RX_CLK, and TX_CLK are stable.
DS33Z41 Quad IMUX Ethernet Mapper 8.4 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3. Clear all reset bits. Allow 5 milliseconds for the reset recovery. STEP 2: Check the Device ID in the GL.IDRL and GL.IDRH registers. STEP 3: Configure the system clocks. Allow the clock system to properly adjust.
DS33Z41 Quad IMUX Ethernet Mapper 8.7 Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched Status registers GL.LIS, GL.SIS, GL.IBIS, GL.TRQIS, GL.IMXSLS, GL.IMXDFDELS, and GL.IMXOOFLS to initially determine the source of the interrupt. The host can then read the LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, LI.RX86S, SU.
DS33Z41 Quad IMUX Ethernet Mapper Transmit Queue FIFO Overflowed Transmit Queue Overflow Transmit Queue for Connection Exceeded Low Threshold Transmit Queue for Connection Exceeded High Threshold Receive Queue FIFO Overflowed Receive Queue Overflow Receive Queue for Connection Exceeded Low Threshold Receive Queue for Connection Exceeded High Threshold Performance Monitor Update Bit Error
DS33Z41 Quad IMUX Ethernet Mapper 8.8 Serial Interface The Serial Interface consists of physical serial port, IMUX/IBO Formatter, and HDLC/X.86 engine. The Serial Interface supports time-division multiplexed serial data, in a format compatible with Dallas Semiconductor’s 8.192Mbps Channel Interleaved Bus Operation (IBO). The Serial Interface receives and transmits the encapsulated Ethernet packets.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 TSER LIU Framer TSYNC T1E1 T1E1 T1E1 LIU LIU TCLKI Framer I B O Framer H D L C Line 1 IMUX RSER Arbiter Ethernet Port RSYNC RCLKI T1E1 LIU Framer SDRAM Interface Figure 8-4. Diagram of Data Transmission with IMUX Operation Sequence 02 . . . 128 Byte Sequence 02 128 Byte Sequence 01 Sequence 01 L1 32 L1 31 . . . L1 04 L1 03 s02 xxxx L1 32 L1 31 . . .
DS33Z41 Quad IMUX Ethernet Mapper 8.9.1 Microprocessor Requirements Link aggregation requires an external host microprocessor to issue instructions and to monitor the IMUX function of the DS33Z41. The host microprocessor is responsible for the following tasks to open a transmit channel: • Configuring GL.IMXCN to control the links participating in the aggregation. • Issuing a link start command through GL.IMXC. • Monitoring the ITSYNC1-4 status from GL.IMXSS or GL.IMXSLS. • Monitoring GL.IMXDFDELS.
DS33Z41 Quad IMUX Ethernet Mapper 8.9.2 IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Serial Interface is shown in Figure 8-5. The MSB for all commands is a “1”. The next 6 bits contain the actual opcode for the command. The LSB is the even parity calculation for the byte. These commands will be sent and received on Channel 2 of each of the T1/E1 interleaved IBO data. The commands that are possible are outlined in Table 8-3.
DS33Z41 Quad IMUX Ethernet Mapper The command and status registers for the IMUX function are detailed below: Table 8-4. Command and Status for the IMUX for Processor Communication REGISTER IMUX Configuration Register IMUX Command Register NAME COMMENTS GL.IMXCN Used to configure the number of links participating and select T1 or E1. GL.IMXC Used to issue commands for link management IMUX Sync Status Register GL.
DS33Z41 Quad IMUX Ethernet Mapper 8.9.3 Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monitoring is started. The device will declare an out of frame (OOF) if 2 consecutive sequence errors are received. The device automatically adjusts for single-frame slips by increasing or decreasing the expected frame sequence number. If a frame sequence number is neither repeated nor skipped by one (indicating a single-frame slip), it is considered a sequence error.
DS33Z41 Quad IMUX Ethernet Mapper 8.10 Connections and Queues The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device to provide software compatibility with multi-port devices. The connection will have an associated transmit and receive queue.
DS33Z41 Quad IMUX Ethernet Mapper It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure for setting up a connection follows: • Set up the queue sizes for both transmit and receive queue (AR.TQSC1 and AR.RQSC1). • Set up the high/low thresholds and interrupt enables if desired (GL.TRQIE, LI.
DS33Z41 Quad IMUX Ethernet Mapper 8.12 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z41 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mechanisms that are used for flow control: • In half duplex mode, a jam sequence is sent that causes collisions at the far end. The collisions cause the transmitting node to reduce the rate of transmission.
DS33Z41 Quad IMUX Ethernet Mapper 8.12.1 Full-Duplex Flow Control Automatic flow control is enabled by default. The host processor can disable this functionality with SU.GCR.ATFLOW. The flow control mechanism is governed by the high watermarks (SU.RQHT). The SU.RQLT low threshold can be used as indication that the network congestion is clearing up. The value of SU.RQLT does not affect the flow control.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-6. Flow Control Using Pause Control Frame 8 Receive Queue Low Water Rx Data Receive Queue Growth Receive Queue High Water Mark Initiate Flow control 8.12.2 Half-Duplex Flow control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant end.
DS33Z41 Quad IMUX Ethernet Mapper 8.13 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains 7 signals with a reference clock of 50MHz. In MII operation, the interface contains 17 signals and a clock reference of 25MHz. The DS33Z41 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS.
DS33Z41 Quad IMUX Ethernet Mapper • MII error asserted during the reception of the frame. • Dribbling bits occurred in the frame. • CRC error occurred. • Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes received. • Control frame was received. The mode must be full duplex. • Unsupported control frame was received. Note that frames received that are runt frames or frames with collision will automatically be rejected. Table 8-7.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-8.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-9.
DS33Z41 Quad IMUX Ethernet Mapper 8.14 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWL and SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z41 when the operation is complete. Reading from the MAC registers requires the SU.
DS33Z41 Quad IMUX Ethernet Mapper 8.14.1 MII Mode The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section 8.2.2. Diagrams of system connections for MII operation are shown in Figure 8-8 and Figure 8-9. 8.14.2 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high.
DS33Z41 Quad IMUX Ethernet Mapper 8.14.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management Interface is shown Figure 8-11.
DS33Z41 Quad IMUX Ethernet Mapper 8.15.2 Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync f6 err ors 6o 32 ors err bi t sw ith th wi its out 4b 1 bit error Verify Match Pattern Matches 8.15.4 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and counts the incoming bits. An OOS condition is declared when the synchronization state machine is not in the “Sync” state.
DS33Z41 Quad IMUX Ethernet Mapper 8.15.5.2 Performance Monitoring Update All counters stop counting at their maximum count. A counter register is updated by asserting (low to high transition) the performance monitoring update signal (PMU). During the counter register update process, the performance monitoring status signal (PMS) is deasserted.
DS33Z41 Quad IMUX Ethernet Mapper 8.16 Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The data output from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream (bit synchronous mode). HDLC processing can be disabled (clear channel enable).
DS33Z41 Quad IMUX Ethernet Mapper 8.17 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial data stream. Packet processing can be disabled (clear channel enable).
DS33Z41 Quad IMUX Ethernet Mapper FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet. If FCS processing or packet processing is disabled, FCS byte extraction is not performed. Bit reordering changes the bit order of each byte.
DS33Z41 Quad IMUX Ethernet Mapper 8.18 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides a HDLC-type framing structure for encapsulation of Ethernet frames, but does not inflict dynamic bandwidth expansion as HDLC does. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33Z41 expects a byte synchronization signal to provide the byte boundary for the X.86 receiver. This is provided by the RSYNC pin.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-15. X.86 Encapsulation of the MAC field Number of Bytes Flag(0x7E) 1 Address(0x04) 1 Control(0x03) 1 1st Octect of SAPI(0xfe) 1 2nd Octect of SAPI(0x01) 1 Destination Adrs(DA) 6 Source Adrs(SA) 6 Length/Type 2 MAC Client Data 46-1500 PAD FCS for MAC 4 FCS for LAPS 4 Flag(0x7E) MSB LSB The DS33Z41 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X.86 mode in the register LI.TX86E.
DS33Z41 Quad IMUX Ethernet Mapper The X86 received frame is aborted if: • • • • • If 7d, 7E is detected. This is an abort packet sequence in X.86. Invalid FCS is detected. The received frame has less than 6 octets. Control, SAPI and address field are mismatched to the programmed value. Octet 7d and octet other than 5d, 5e, 7e, or dd is detected. For the transmitter if X.
DS33Z41 Quad IMUX Ethernet Mapper 8.19 Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR can be used to restrict the transport of received MAC data to the serial port at a programmable rate. This is shown in Figure 8-16. The CIR will restrict the data flow from the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN.
DS33Z41 Quad IMUX Ethernet Mapper Figure 8-16. CIR in the WAN Transmit Path 50 or 25 Mhz Oscillator Buffer Dev Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz Microport REF_CLKI TSER TCLKI1 Line 1 RCLKI1 RSER IMUX HDLC + Serial Interface TX_CLK1 MAC RMII MII CIR Arbiter RXD RX_CLK1 TXD X.
DS33Z41 Quad IMUX Ethernet Mapper 9 DEVICE REGISTERS Ten address lines are used to address the register space. Table 9-1 shows the register map for the DS33Z41. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global Registers are preserved for software compatibility with multiport devices. The Serial Interface (Line) Registers are used to configure the serial port and the associated transport protocol.
DS33Z41 Quad IMUX Ethernet Mapper 9.1 Register Bit Maps Table 9-2, Table 9-3, Table 9-4, Table 9-5, Table 9-6, and Table 9-7 contain the registers of the DS33Z41. Bits that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized with a value of 00h for proper operation, unless otherwise noted. 9.1.1 Global Register Bit Map Table 9-2. Global Register Bit Map ADDR 000h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GL.
DS33Z41 Quad IMUX Ethernet Mapper 9.1.2 Arbiter Register Bit Map Table 9-3. Arbiter Register Bit Map ADDR 040h 041h 9.1.3 NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AR.RQSC1 RQSC1[7] RQSC1[6] RQSC1[5] RQSC1[4] RQSC1[3] RQSC1[2] RQSC1[1] RQSC1[0] AR.
DS33Z41 Quad IMUX Ethernet Mapper 9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map ADDR NAME 0C0h Reserved BIT 7 - BIT 6 - BIT 5 - BIT 4 - BIT 3 - BIT 2 - BIT 1 - BIT 0 - 0C1h LI.RSTPD 0C2h LI.LPBK - - - - - - RESET - - - - - - - - QLP 0C3h Reserved 0C4h LI.
DS33Z41 Quad IMUX Ethernet Mapper ADDR NAME 103h LI.RMPSCH 104h LI.RPPSR BIT 7 RMX15 BIT 6 RMX14 BIT 5 RMX13 BIT 4 RMX12 BIT 3 RMX11 BIT 2 RMX10 BIT 1 RMX9 BIT 0 RMX8 - - - - - REPC RAPC RSPC 105h LI.RPPSRL 106h LI.RPPSRIE REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE 107h Reserved 108h LI.RPCB0 RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPC0 109h LI.RPCB1 10Ah LI.
DS33Z41 Quad IMUX Ethernet Mapper 9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map ADDR 140h 141h 142h 143h 144h 145h 146h 147h 148h 149h 14Ah 14Bh 14Ch 14Dh 14Eh 14Fh 150h 151h 152h 153h 154h 155h 156h 157h 158h 159h 15Ah 15Bh 15Ch 15Dh 15Eh NAME SU.MACRADL BIT 7 MACRA7 BIT 6 MACRA6 BIT 5 MACRA5 BIT 4 MACRA4 BIT 3 MACRA3 BIT 2 MACRA2 BIT 1 MACRA1 BIT 0 MACRA0 SU.MACRADH MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRA09 MACRA08 SU.
DS33Z41 Quad IMUX Ethernet Mapper 9.1.6 MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map ADDR 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 100h 101h 102h 103h 10Ch 10Dh 10Eh 10Fh NAME BIT 7 SU.MACCR 31:24 23:16 DRO 15:8 7:0 BOLMT1 SU.MACAH 31:24 23:16 15:8 PADR47 7:0 PADR39 SU.
DS33Z41 Quad IMUX Ethernet Mapper ADDR 110h 111h 112h 113h 200h 201h 202h 203h 204h 205h 206h 207h 300h 301h 302h 303h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 334h 335h 336h 337h 338h 339h 33Ah 33Bh NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESERVED – initialize to FF RESERVED – initialize to FF RESERVED – initialize to FF RESERVED – initialize to FF SU.
DS33Z41 Quad IMUX Ethernet Mapper 9.2 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are preserved to provide code compatibility with the multiport devices in this product family. The global registers bit descriptions are presented below.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — GL.CR1 Global Control Register 1 02h 6 — 5 — 4 — 3 — 2 REF_CLKO 0 1 INTM 0 0 RST 0 Bit 2: REF_CLKO OFF (REF_CLKO). This bit determines the REF_CLKO output mode. 1 = REF_CLKO is disabled and outputs an active-low signal. 0 = REF_CLKO is active and in accordance with RMII/MII Selection Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INT pin.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GL.RTCAL Global Receive and Transmit Serial Port Clock Activity Latched Status 04h 6 — 0 5 — 0 4 RLCALS1 0 3 — 0 2 — 0 1 — 0 0 TLCALS1 0 Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1). This bit is set to 1 if the receive clock for Serial Interface 1 has activity. This bit is cleared upon read.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GL.LIE Global Serial Interface Interrupt Enable 06h 6 — 0 5 — 0 4 LIN1TIE 0 3 — 0 2 — 0 1 — 0 0 LIN1RIE 0 Bit 4: Serial Interface 1 Tx Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS. Bit 0: Serial Interface 1 Rx Interrupt Enable (LINE1RIE). Setting this bit to 1 enables an interrupt on LIN1RIS.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GL.TRQIE Global Transmit Receive Queue Interrupt Enable 0Ah 6 — 0 5 — 0 4 TQ1IE 0 3 — 0 2 — 0 1 — 0 0 RQ1IE 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE). Setting this bit to 1 enables an interrupt on RQ1IS.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default GL.CON1 Connection Register for Ethernet Interface 1 0Eh 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 LINE1[0] 1 Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit selects the Ethernet port that is to be connected to the Serial Interface. Note that bidirectional connection is assumed between the Serial and Ethernet Interfaces.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GL.IMXCN Inverse MUX Configuration Register 16h 6 T1E1 0 5 RXE 0 4 SENDE 0 3 L4 0 2 L3 0 1 L2 0 0 L1 0 Bit 6: T1E1 Mode (T1E1). This bit determines if IMUX if for T1 or E1 Mode. 0 = T1 Mode 1 = E1 Mode Bit 5: Receive Enable (RXE). If this bit is set to 1, data will be received from the Serial Interface and passed to the packet processor.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 ITSYNC4 0 GL.IMXSS Inverse MUX Sync Status 18h 6 ITSYNC3 0 5 ITSYNC2 0 4 ITSYNC1 0 3 IRSYNC4 0 2 IRSYNC3 0 1 IRSYNC2 0 0 IRSYNC1 0 Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the 4th portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 ITSYNCLS4 0 GL.IMXSLS Inverse MUX Sync Latched Status 1Ah 6 ITSYNCLS3 0 5 ITSYNCLS2 0 4 ITSYNCLS1 0 3 IRSYNCLS4 0 2 IRSYNCLS3 0 1 IRSYNCLS2 0 0 IRSYNCLS1 0 Bit 7: IMUX Transmit Sync Latched Status 4 (ITSYNCLS4). This is a latched status bit for ITSYNC4. Bit 6: IMUX Transmit Sync Latched Status 3 (ITSYNCLS3). This is a latched status bit for ITSYNC3.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TOOFIE4 0 GL.IMXOOFIE Inverse MUX OOF Interrupt Enable 1Eh 6 TOOFIE3 0 5 TOOFIE2 0 4 TOOFIE1 0 3 ROOFIE4 0 2 ROOFIE3 0 1 ROOFIE2 0 0 ROOFIE1 0 Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4. Bit 6: IMUX Transmit OOF Interrupt Enable 3 (TOOFIE3). Setting this bit to 1 enables an interrupt on TOOFLS3.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TOOFLS4 0 GL.IMXOOFLS Inverse MUX Out Of Frame Latched Status 1Fh 6 OOFLS3 0 5 TOOFLS2 0 4 TOOFLS1 0 3 ROOFL4 0 2 ROOFL3 0 1 ROOFLS2 0 0 ROOFLS1 0 Bit 7: IMUX Transmit OOF Latched Status 4 (TOOFLS4). This is a latched bit for Transmit OOF, this bit is set if the distant end is out of frame. Bit 6: IMUX Transmit OOF Latched Status 3 (TOOFLS3).
DS33Z41 Quad IMUX Ethernet Mapper Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the SDRAM and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z41. Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GL.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description Register Address: Bit # Name Default 7 SREFT7 0 GL.SDRFTC Global SDRAM Refresh Time Control 3Dh 6 SREFT6 1 5 SREFT5 0 4 SREFT4 0 3 SREFT3 0 2 SREFT2 1 1 SREFT1 1 0 SREFT0 0 Bits 7 to 0: SDRAM Refresh Time Control (SREFT7 to SREFT0). These 8 bits are used to control the SDRAM refresh frequency. The refresh rate will be equal to this register value x 8 x 100MHz. Note: This register has a non-zero default value.
DS33Z41 Quad IMUX Ethernet Mapper 9.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data to/from the SDRAM. The base address of the Arbiter register space is 0040h. 9.3.1 Arbiter Register Bit Descriptions Register Name: Register Description: Register Address: Bit # Name Default 7 RQSC7 0 AR.
DS33Z41 Quad IMUX Ethernet Mapper 9.4 BERT Registers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BCR BERT Control Register 80h 6 PMU 0 5 RNPL 0 4 RPIC 0 3 MPR 0 2 APRD 0 1 TNPL 0 0 TPIC 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU). This bit causes a performance monitoring update to be initiated.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: BPCLR BERT Pattern Configuration Low Register 82h Bit # 7 6 5 4 3 2 1 0 Name — QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0 Default 0 0 0 0 0 0 0 0 The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with a formula of xn + xy + 1. The initial value for x (the seed) is placed in the BSPB (bert seed/pattern) register. The BERT generates a series of bits by iteration of the formula.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 BSP7 0 BSPB0R BERT Pattern Byte 0 Register 84h 6 BSP6 0 5 BSP5 0 4 BSP4 0 3 BSP3 0 2 BSP2 0 1 BSP1 0 0 BSP0 0 Bits 7 to 0: BERT Pattern (BSP7 to BPS0). Lower eight bits of 32 bits. Register description follows next register.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TEICR Transmit Error Insertion Control Register 88h 6 — 0 5 TIER2 0 4 TIER1 0 3 TIER0 0 2 BEI 0 1 TSEI 0 0 — 0 Bits 5 to 3: Transmit Error Insertion Rate (TEIR2 to TEIR0). These three bits indicate the rate at which errors are inserted in the output data stream. One out of every 10n bits is inverted. TEIR[2:0] is the value n.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — — BSRL BERT Status Register Latched 8Eh 6 — — 5 — — 4 — — 3 PMSL — 2 BEL — 1 BECL — 0 OOSL — Bit 3: Performance Monitor Update Status Latched (PMSL). This bit is set when the PMS bit transitions from 0 to 1. Bit 2: Bit Error Detected Latched (BEL). This bit is set when a bit error is detected. Bit 1: Bit Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 BEC7 0 RBECB0R Receive Bit Error Count Byte 0 Register 94h 6 BEC6 0 5 BEC5 0 4 BEC4 0 3 BEC3 0 2 BEC2 0 1 BEC1 0 0 BEC0 0 Bits 7 to 0: Bit Error Count (BEC7 to BEC0). Lower eight bits of 24 bits. Register description below.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 BC15 0 RBCB1 Receive Bit Count Byte 1 Register #1 99h 6 BC14 0 5 BC13 0 4 BC12 0 3 BC11 0 2 BC10 0 1 BC9 0 0 BC8 0 Bits 7 to 0: Bit Count (BC15 to BC8). Eight bits of a 32-bit value. Register description below.
DS33Z41 Quad IMUX Ethernet Mapper 9.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“ designation should be written to zero, unless specifically noted in the register definition.
DS33Z41 Quad IMUX Ethernet Mapper 9.5.3 Transmit HDLC Processor Registers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.TPPCL Transmit Packet Processor Control Low Register 0C4h 6 — 0 5 TFAD 0 4 TF16 0 3 TIFV 0 2 TSD 0 1 TBRE 0 0 TIAEI 0 Note: The user should take care not to modify this register value during packet error insertion. Bit 5: Transmit FCS Append Disable (TFAD). This bit controls whether or not an FCS is appended to the end of each packet.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TIFG7 0 LI.TIFGC Transmit Inter-Frame Gapping Control Register 0C5h 6 TIFG6 0 5 TIFG5 0 4 TIFG4 0 3 TIFG3 0 2 TIFG2 0 1 TIFG1 0 0 TIFG0 1 Bits 7 to 0: Transmit Inter-Frame Gapping (TIFG7 to TIFG0). These eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 MEIMS 0 LI.TEPHC Transmit Errored Packet High Control Register 0C7h 6 TPER6 0 5 TPER5 0 4 TPER4 0 3 TPER3 0 2 TPER2 0 1 TPER1 0 0 TPER0 0 Bit 7: Manual Error Insert Mode Select (MEIMS). When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a 1.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.TPPSR Transmit Packet Processor Status Register 0C8h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 TEPF 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TPC7 0 LI.TPCR0 Transmit Packet Count Byte 0 0CCh 6 TPC6 0 5 TPC5 0 4 TPC4 0 3 TPC3 0 2 TPC2 0 1 TPC1 0 0 TPC0 0 Bits 7 to 0: Transmit Packet Count (TPC7 to TPC0). Eight bits of 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 TPC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TBC7 0 LI.TBCR0 Transmit Byte Count Byte 0 0D0h 6 TBC6 0 5 TBC5 0 4 TBC4 0 3 TBC3 0 2 TBC2 0 1 TBC1 0 0 TBC0 0 Bits 7 to 0: Transmit Byte Count (TBC7 to TBC0). Eight bits of 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 TBC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.THPMUU Serial Interface Transmit HDLC PMU Update Register 0D6h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 TPMUU 0 Bit 0: Transmit PMU Update (TPMUU). This signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated.
DS33Z41 Quad IMUX Ethernet Mapper 9.5.4 X.86 Registers X.86 Transmit and common Registers are used to control the operation of the X.86 encoder and decoder. Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.TX86EDE X.86 Encoding Decoding Enable 0D8h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 X86ED 0 Bit 0: X.86 Encoding Decoding (X86ED). If this bit is set to 1, X.86 encoding and decoding is enabled for the Transmit and Receive paths.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default LI.TRX86SAPIL Transmit Receive X.86 SAPIL 0DCh 7 6 5 4 3 2 1 0 TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 TRSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPIL0 0 0 0 0 0 0 0 1 Bits 7 to 0: X86 Transmit Receive Control (TRSAPIL7 to TRSAPIL0). This is the address field for the X.86 transmitter and expected value for the receiver. The register is reset to 0x01.
DS33Z41 Quad IMUX Ethernet Mapper 9.5.5 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen registers. Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RMX15 0 LI.RMPSCH Receive Maximum Packet Size Control High Register 103h 6 RMX14 0 5 RMX13 0 4 RMX12 0 3 RMX11 0 2 RMX10 1 1 RMX9 1 0 RMX8 1 Bits 7 to 0: Receive Maximum Packet Size (RMX15 to RMX8). These 16 bits indicate the maximum allowable packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 REPL — LI.RPPSRL Receive Packet Processor Status Register Latched 105h 6 RAPL — 5 RIPDL — 4 RSPDL — 3 RLPDL — 2 REPCL — 1 RAPCL — 0 RSPCL — Bit 7: Receive FCS Errored Packet Latched (REPL). This bit is set when a packet with an errored FCS is detected. Bit 6: Receive Aborted Packet Latched (RAPL). This bit is set when a packet with an abort indication is detected.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 REPIE 0 LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable 106h 6 RAPIE 0 5 RIPDIE 0 4 RSPDIE 0 3 RLPDIE 0 2 REPCIE 0 1 RAPCIE 0 0 RSPCIE 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE). This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RPC7 0 LI.RPCB0 Receive Packet Count Byte 0 Register 108h 6 RPC6 0 5 RPC5 0 4 RPC4 0 3 RPC3 0 2 RPC2 0 1 RPC1 0 0 RPC0 0 Bits 7 to 0: Receive Packet Count (RPC7 to RPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RPC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RFPC7 0 LI.RFPCB0 Receive FCS Errored Packet Count Byte 0 Register 10Ch 6 RFPC6 0 5 RFPC5 0 4 RFPC4 0 3 RFPC3 0 2 RFPC2 0 1 RFPC1 0 0 RFPC0 0 Bits 7 to 0: Receive FCS Errored Packet Count (RFPC7 to RFPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RFPC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RAPC7 0 LI.RAPCB0 Receive Aborted Packet Count Byte 0 Register 110h 6 RAPC6 0 5 RAPC5 0 4 RAPC4 0 3 RAPC3 0 2 RAPC2 0 1 RAPC1 0 0 RAPC0 0 Bits 7 to 0: Receive Aborted Packet Count (RAPC7 to RAPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RAPC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RSPC7 0 LI.RSPCB0 Receive Size Violation Packet Count Byte 0 Register 114h 6 RSPC6 0 5 RSPC5 0 4 RSPC4 0 3 RSPC3 0 2 RSPC2 0 1 RSPC1 0 0 RSPC0 0 Bits 7 to 0: Receive Size Violation Packet Count (RSPC7 to RSPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RSPC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RBC7 0 LI.RBC0 Receive Byte Count 0 Register 118h 6 RBC6 0 5 RBC5 0 4 RBC4 0 3 RBC3 0 2 RBC2 0 1 RBC1 0 0 RBC0 0 Bits 7 to 0: Receive Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RBC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 REBC7 0 LI.RAC0 Receive Aborted Byte Count 0 Register 11Ch 6 REBC6 0 5 REBC5 0 4 REBC4 0 3 REBC3 0 2 REBC2 0 1 REBC1 0 0 REBC0 0 Bits 7 to 0: Receive Aborted Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 REBC15 0 LI.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.RHPMUU Serial Interface Receive HDLC PMU Update Register 120h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 RPMUU 0 Bit 0: Receive PMU Update (RPMUU). This signal causes the receive cell/packet processor block performance monitoring registers to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and resets the associated counters.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LI.RX86LSIE Receive X.86 Interrupt Enable 123h 6 — 0 5 — 0 4 — 0 3 SAPINE01IM 0 2 SAPINEFEIM 0 1 CNE3LIM 0 0 ANE4IM 0 Bit 3: SAPI Octet Not Equal to LI.TRX86SAPIH Interrupt Enable (SAPINE01IM). If this bit is set to 1, LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet Not Equal to LI.TRX86SAPIL Interrupt Enable (SAPINEFEIM). If this bit is set to 1, LI.RX86S.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 TQHT7 0 LI.TQHT Serial Interface Transmit Queue High Threshold (Watermark) 125h 6 TQHT6 0 5 TQHT5 0 4 TQHT4 0 3 TQHT3 0 2 TQHT2 0 1 TQHT1 0 0 TQHT0 0 Bits 7 to 0: Transmit Queue High Threshold (TQHT7 to TQTH0). The transmit queue high threshold for the connection, in increments of 32 packets of 2048 bytes each.
DS33Z41 Quad IMUX Ethernet Mapper 9.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are shown in Table 9-7. Accessing the MAC Registers is described in the Section 8.14. 9.6.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 MACRD15 0 SU.MACRD1 MAC Read Data Byte 1 143h 6 MACRD14 0 5 MACRD13 0 4 MACRD12 0 3 MACRD11 0 2 MACRD10 0 1 MACRD9 0 0 MACRD8 0 Bits 7 to 0: MAC Read Data Byte 1 (MACRD15 to MACRD8). One of four bytes of data read from the MAC. Valid after a read command has been issued and the SU.MACRWC.MCS bit is zero.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 MACWD15 0 SU.MACWD1 MAC Write Data Byte 1 147h 6 MACWD14 0 5 MACWD13 0 4 MACWD12 0 3 MACWD11 0 2 MACWD10 0 1 MACWD09 0 0 MACWD08 0 Bits 7 to 0: MAC Write Data Byte 1 (MACWD15 to MACWD08). One of four bytes of data to be written to the MAC. Data has been written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 MACAW 15 0 SU.MACAWH MAC Address Write High 14Bh 6 MACAW 14 0 5 MACAW 13 0 4 MACAW12 0 3 MACAW11 0 2 MACAW10 0 1 MACAW9 0 0 MACAW8 0 Bits 7 to 0: MAC Write Address (MACAW15 to MACAW8). High byte of the MAC address. Used only for write operations. Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SU.LPBK Ethernet Interface Loopback Control Register 14Fh 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 QLP 0 Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is removed.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SU.TFRC Transmit Frame Resend Control 151h 6 — 0 5 — 0 4 — 0 3 NCFQ 0 2 TPDFCB 0 1 TPRHBC 0 0 TPRCB 0 Bit 3: No Carrier Queue Flush Bar (NCFQ). If this bit is set to 1, the queue for data passing from Serial Interface to Ethernet Interface will not be flushed when loss of carrier is detected. Bit 2: Transmit Packet Deferred Fail Control Enable (TPDFCB).
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 UR 0 SU.TFSL Transmit Frame Status Low 152h 6 EC 0 5 LC 0 4 ED 0 3 LOC 0 2 NOC 0 1 — 0 0 FABORT 0 Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer. Bit 6: Excessive Collisions (EC). When this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 FL7 0 SU.RFSB0 Receive Frame Status Byte 0 154h 6 FL6 0 5 FL5 0 4 FL4 0 3 FL3 0 2 FL2 0 1 FL1 0 0 FL0 0 Bits 7 to 0: Frame Length (FL7 to FL0). These 8 bits are the low byte of the length (in bytes) of the received frame, with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet without PCS or Pad bytes.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 MF 0 SU.RFSB3 Receive Frame Status Byte 3 157h 6 — 0 5 — 0 4 BF 0 3 MCF 0 2 UF 0 1 CF 0 0 LE 0 Bit 7: Missed Frame (MF). This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter. Bit 4: Broadcast Frame (BF). This bit is set to 1 if the current frame is a broadcast frame. Bit 3: Multicast Frame (MCF).
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 RMPS7 1 SU.RMFSRL Receiver Maximum Frame Low Register 158h 6 RMPS6 1 5 RMPS5 1 4 RMPS4 0 3 RMPS3 0 2 RMPS2 0 1 RMPS1 0 0 RMPS0 0 Bits 7 to 0: Receiver Maximum Frame (RMPS7 to RMPS0). Eight bits of 16-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RMPS15 0 SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SU.QRIE Receive Queue Cross Threshold Enable 15Ch 6 — 0 5 — 0 4 — 0 3 RFOVFIE 0 2 RQVFIE 0 1 RQLTIE 0 0 RQHTIE 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE). If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE). If this bit is set, the interrupt is enabled for RQOVFLS.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SU.RFRC Receive Frame Rejection Control 15Eh 6 UCFR 0 5 CFRR 0 4 LERR 0 3 CRCERR 0 2 DBR 0 1 MIIER 0 0 BFR 0 Bit 6: Uncontrolled Control Frame Reject (UCFR). When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal to zero, non-pause control frames are rejected. Bit 5: Control Frame Reject (CFRR). When set to 1, control frames are allowed.
DS33Z41 Quad IMUX Ethernet Mapper 9.6.2 MAC Registers The control registers related to the control of the individual MACs are shown in the following tables. The DS33Z41 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Note that the addresses listed are the indirect addresses that must be provided to SU.MACRADH/SU.MACRADL or SU.MACAWH/SU.MACAWL. Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Bit 12: Late Collision Control (LCC). When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY). When set to 1, the MAC makes only a single attempt to transmit each frame. If a collision occurs, the MAC ignores the current frame and proceeds to the next frame.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Reserved MAC Reserved Control Register 010Ch (indirect) 010Ch: Bit # Name Default 31 Reserved 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 27 Reserved 0 26 Reserved 0 25 Reserved 0 24 Reserved 0 010Dh: Bit # Name Default 23 Reserved 0 22 Reserved 0 21 Reserved 0 20 Reserved 0 19 Reserved 0 18 Reserved 0 17 Reserved 0 16 Reserved 0 010Eh: Bit # Name Default 15 Reserved 0 14 Reserved 0 13 Reserved 0
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: Reserved MAC Reserved Control Register 0110h (indirect) 0110h: Bit # Name Default 31 Reserved 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 27 Reserved 0 26 Reserved 0 25 Reserved 0 24 Reserved 0 0111h: Bit # Name Default 23 Reserved 0 22 Reserved 0 21 Reserved 0 20 Reserved 0 19 Reserved 0 18 Reserved 0 17 Reserved 0 16 Reserved 0 0112h: Bit # Name Default 15 Reserved 0 14 Reserved 0 13 Reserved 0
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0200h: Bit # Name Default 0201h: Bit # Name Default 0202h: Bit # Name Default 0203h: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0204h: Bit # Name Default 0205h: Bit # Name Default 0206h: Bit # Name Default 0207h: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0300h: Bit # Name Default 0301h: Bit # Name Default 0302h: Bit # Name Default 0303h: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0308h: Bit # Name Default 0309h: Bit # Name Default 030Ah: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 030Ch: Bit # Name Default 030Dh: Bit # Name Default 030Eh: Bit # Name Default 030Fh: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0334h: Bit # Name Default 0335h: Bit # Name Default 0336h: Bit # Name Default 0337h: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper Register Name: Register Description: Register Address: 0338h: Bit # Name Default 0339h: Bit # Name Default 033Ah: Bit # Name Default 033Bh: Bit # Name Default SU.
DS33Z41 Quad IMUX Ethernet Mapper 10 FUNCTIONAL TIMING 10.1 MII and RMII Interfaces Each MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode TX_CLK is input from the external PHY.
DS33Z41 Quad IMUX Ethernet Mapper Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first Nibble of the preamble in 100Mbps operation or first nibble of SFD for 10Mbps operation. The data on RXD[3:0] is not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode). RX_ERR should be tied low when in DCE Mode. Figure 10-3.
DS33Z41 Quad IMUX Ethernet Mapper 11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)………………………………………….–0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to VSS.……………………………………………………–0.3V to +3.6V Supply Voltage (VDD1.8) Range with Respect to VSS….…………………………………………………–0.3V to +2.0V Ambient Operating Temperature Range………………………………………………...…………………–40ºC to +85ºC Junction Operating Temperature Range…………………………………………………..……………..
DS33Z41 Quad IMUX Ethernet Mapper Note 1: Typical power is 145mW. Note 2: All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to VDD. Note 3: RST pin held low, or RST bit set. Note 4: RST pin held low, or RST bit set. All clocks stopped. 11.1 Thermal Characteristics Table 11-3. Thermal Characteristics PARAMETER Ambient Temperature Junction Temperature Theta-JA (θJA) in Still Air for 169-Pin 14mm CSBGA MIN -40°C TYP +52.
DS33Z41 Quad IMUX Ethernet Mapper 11.2 MII Interface Table 11-5. Transmit MII Interface PARAMETER TX_CLK Period TX_CLK Low Time TX_CLK High Time TX_CLK to TXD, TX_EN Delay SYMBOL MIN 10Mbps TYP 400 MAX MIN 100Mbps TYP 40 UNITS t1 t2 t3 140 140 260 260 14 14 26 26 ns ns ns t4 0 20 0 20 ns Figure 11-1.
DS33Z41 Quad IMUX Ethernet Mapper Table 11-6. Receive MII Interface 10Mbps TYP 400 100Mbps TYP 40 PARAMETER SYMBOL RX_CLK Period RX_CLK Low Time RX_CLK High Time RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time t5 t6 t7 140 140 t8 5 5 ns t9 5 5 ns MIN MAX MIN 260 260 14 14 MAX 26 26 Figure 11-2.
DS33Z41 Quad IMUX Ethernet Mapper 11.3 RMII Interface Table 11-7. Transmit RMII Interface PARAMETER SYMBOL MIN REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time REF_CLK to TXD, TX_EN Delay 10Mbps TYP 50MHz ±50ppm 20 MAX MIN 100Mbps TYP 50MHz ±50ppm 20 UNITS t1 t2 t3 7 7 13 13 7 7 13 13 ns ns ns t4 5 10 5 10 ns Figure 11-3.
DS33Z41 Quad IMUX Ethernet Mapper Table 11-8. Receive RMII Interface PARAMETER SYMBOL MIN REF_CLK Frequence REF_CLK Period REF_CLK Low Time REF_CLK High Time RXD, CRS_DV to REF_CLK Setup Time REF_CLK to RXD, CRS_DV Hold Time 10Mbps TYP 50MHz ±50ppm 20 MAX 100Mbps TYP 50MHz ±50ppm 20 MIN MAX UNITS MHz t1 t2 t3 7 7 t8 5 5 ns t9 5 5 ns 13 13 7 7 13 13 Figure 11-4.
DS33Z41 Quad IMUX Ethernet Mapper 11.4 MDIO Interface Table 11-9. MDIO Interface PARAMETER SYMBOL MIN t1 t2 t3 t4 t5 t6 540 270 270 20 10 20 MDC Frequency MDC Period MDC Low Time MDC High Time MDC to MDIO Output Delay MDIO Setup Time MDIO Hold Time TYP 1.67 600 300 300 Figure 11-5.
DS33Z41 Quad IMUX Ethernet Mapper 11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER TCLKI Frequency TCLKI Period TCLKI Low Time TCLKI High Time TCLKI to TSER Output Delay TSYNC Setup Time TSYNC Hold Time SYMBOL MIN t1 t2 t3 t4 t5 t6 19.2 8 8 3 3.5 7 TYP 10 Figure 11-6.
DS33Z41 Quad IMUX Ethernet Mapper 11.6 Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER SYMBOL MIN t1 t2 t3 t4 t4 t5 t5 19.2 8 8 7 7 2 2 RCLKI Frequency RCLKI Period RCLKI Low Time RCLKI High Time RSER Setup Time RSYNC Setup Time RSER Hold Time RSYNC Hold Time TYP Figure 11-7.
DS33Z41 Quad IMUX Ethernet Mapper 11.7 SDRAM Timing Table 11-12.
DS33Z41 Quad IMUX Ethernet Mapper Figure 11-8.
DS33Z41 Quad IMUX Ethernet Mapper Figure 11-9. Receive IBO Channel Interleave Mode Timing LINK #1, CHANNEL #1 RSYNC RSER L3 C32 L4 C32 L1 C1 L2 C1 L3 C1 L4 C1 L1 C2 L2 C2 L3 C2 L4 C2 BIT LEVEL DETAIL RCLKI RSYNC LINK 4, CHANNEL 32 RSER LINK 2, CHANNEL 1 LINK 1, CHANNEL 1 LSB MSB LSB MSB Note 1: 8.192MHz bus configuration. Note 2: Data on unused channels must be filled with all ones.
DS33Z41 Quad IMUX Ethernet Mapper Figure 11-10. Transmit IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Unused channels filled with FFh.
DS33Z41 Quad IMUX Ethernet Mapper 11.8 Microprocessor Bus AC Characteristics Table 11-13. AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40°C to +85°C.
DS33Z41 Quad IMUX Ethernet Mapper Figure 11-11. Intel Bus Read Timing (MODEC = 00) t9 ADDR[12:0] Address Valid Data Valid DATA[7:0] t5 WR t1 CS t2 t3 t4 RD t10 Figure 11-12.
DS33Z41 Quad IMUX Ethernet Mapper Figure 11-13. Motorola Bus Read Timing (MODEC = 01) t9 ADDR[12:0] Address Valid Data Valid DATA[7:0] t5 RW t1 CS t2 t3 t4 DS t10 Figure 11-14.
DS33Z41 Quad IMUX Ethernet Mapper 11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.
DS33Z41 Quad IMUX Ethernet Mapper 12 JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
DS33Z41 Quad IMUX Ethernet Mapper 12.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 12-2 for a diagram of the state machine operation.
DS33Z41 Quad IMUX Ethernet Mapper Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state.
DS33Z41 Quad IMUX Ethernet Mapper Figure 12-2. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test/ Idle 1 Select DR-Scan 1 Select IR-Scan 0 1 0 1 Capture DR Capture IR 0 Shift DR 0 Shift IR 0 1 Exit IR Pause IR 0 1 0 Exit2 DR 1 0 0 Pause DR 0 1 1 Exit DR 1 0 1 0 Exit2 IR 1 1 Update DR Update IR 1 1 0 0 12.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
DS33Z41 Quad IMUX Ethernet Mapper Table 12-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001 12.2.1 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions.
DS33Z41 Quad IMUX Ethernet Mapper 12.3 JTAG ID Codes Table 12-2. ID Code Structure DEVICE DS33Z41 REVISION ID[31:28] 0000 DEVICE CODE ID[27:12] 0000 0000 0110 0010 MANUFACTURER’S CODE ID[11:1] 000 1010 0001 REQUIRED ID[0] 1 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the device design.
DS33Z41 Quad IMUX Ethernet Mapper 12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern. • Shifting the TDI pin to the TDO pin through the bypass shift register. • An asynchronous reset occurs while shifting. Figure 12-3.
DS33Z41 Quad IMUX Ethernet Mapper 13 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.
DS33Z41 Quad IMUX Ethernet Mapper 14 DOCUMENT REVISION HISTORY REVISION DESCRIPTION 021405 New Product Release 122006 Added TCLKI to TSER Output Delay Minimum of 3ns. Added TCLKI to TSYNC Setup Time Minimum of 3.5ns. Added definition for BPCLR.PLF[4:0]. Corrected pin description of MDC. Corrected default value listed in the SU.RMFSRL register definition. Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC register definitions. Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.