Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS34S102GN+

_________________________________________________________ Maxim Integrated Products 1

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DS34S101, DS34S102, DS34S104, DS34S108

Single/Dual/Quad/Octal TDM-over-Packet Chip

General Description

These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC

compliant devices allow up to eight E1, T1 or serial

streams or one high-speed E3, T3, STS-1 or serial

stream to be transported transparently over IP, MPLS

or Ethernet networks. Jitter and wander of recovered

clocks conform to G.823/G.824, G.8261, and TDM

specifications. TDM data is transported in up to 64

individually configurable bundles. All standards-

based TDM-over-packet mapping methods are

supported except AAL2. Frame-based serial HDLC

data flows are also supported. The high level of

integration available with the DS34S10x devices

minimizes cost, board space, and time to market.

Applications

TDM Circuit Extension Over PSN

o Leased-Line Services Over PSN

o TDM Over GPON/EPON

o TDM Over Cable

o TDM Over Wireless

Cellular Backhaul Over PSN

Multiservice Over Unified PSN

HDLC-Based Traffic Transport Over PSN

Functional Diagram

Features

♦ Transport of E1, T1, E3, T3 or STS-1 TDM or

Other CBR Signals Over Packet Networks

♦ Full Support for These Mapping Methods:

SAToP, CESoPSN, TDMoIP (AAL1), HDLC,

Unstructured, Structured, Structured with CAS

♦ Adaptive Clock Recovery, Common Clock,

External Clock and Loopback Timing Modes

♦ On-Chip TDM Clock Recovery Machines, One

Per Port, Independently Configurable

♦ Clock Recovery Algorithm Handles Network

PDV, Packet Loss, Constant Delay Changes,

Frequency Changes and Other Impairments

♦ 64 Independent Bundles/Connections

♦ Multiprotocol Encapsulation Supports IPv4,

IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet

♦ VLAN Support According to 802.1p and 802.1Q

♦ 10/100 Ethernet MAC Supports MII/RMII/SSMII

♦ Selectable 32-Bit, 16-Bit or SPI Processor Bus

♦ Operates from Only Two Clock Signals, One for

Clock Recovery and One for Packet Processing

♦ Glueless SDRAM Buffer Management

♦ Low-Power 1.8V Core, 3.3V I/O

See detailed feature list in Section 7.

Ordering Information

PART PORTS TEMP RANGE PIN-PACKAGE

DS34S101GN

-40°C to +85°C

256 TECSBGA

DS34S101GN+

-40°C to +85°C

256 TECSBGA

DS34S102GN

-40°C to +85°C

256 TECSBGA

DS34S102GN+

-40°C to +85°C

256 TECSBGA

DS34S104GN

-40°C to +85°C

256 TECSBGA

DS34S104GN+

-40°C to +85°C

256 TECSBGA

DS34S108GN

-40°C to +85°C

484 HSBGA

DS34S108GN+

-40°C to +85°C

484 HSBGA

+Denotes a lead(Pb)-free/RoHS-compliant package (explanation).

CPU

Bus

Clock Inputs

xMII

Interface

Buffer

Manager

Circuit

Emulation

Engine

Clock

Adapters

10/100

Ethernet

MAC

TDM

Interfaces

SDRAM

Interface

DS34S108

Rev: 032609

Summary of content (198 pages)

PAGE 1
Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles.
PAGE 2
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table of Contents 1. INTRODUCTION ................................................................................................................................. 7 2. ACRONYMS AND GLOSSARY .......................................................................................................... 8 3. APPLICABLE STANDARDS ...............................................................................................
PAGE 3
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.3 GLOBAL REGISTERS ..................................................................................................................... 91 11.4 TDM-OVER-PACKET REGISTERS ................................................................................................... 93 11.4.1 Configuration and Status Registers ....................................................................................................
PAGE 4
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 List of Figures Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 12 Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 13 Figure 6-1. Top-Level Block Diagram ...........................................................................
PAGE 5
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-53. TDM-to-TDM Flow......................................................................................................................... 74 Figure 10-54. TDM-to-CPU Flow ......................................................................................................................... 75 Figure 10-55. CPU-to-TDM Flow .................................................................................
PAGE 6
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 List of Tables Table 3-1. Applicable Standards ......................................................................................................................... 10 Table 9-1. Short Pin Descriptions ........................................................................................................................ 18 Table 9-2. TDM-over-Packet Engine TDM Interface Pins.....................................
PAGE 7
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 11-16. Interrupt Controller Registers ........................................................................................................ 140 Table 11-17. Packet Classifier OAM Identification Registers.............................................................................. 147 Table 11-18. Ethernet MAC Registers .........................................................................................
PAGE 8
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 2.
PAGE 9
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SS7 SSMII STM-1 TDM TDMoIP TDMoP TSA Tx or TX UDP VoIP VPLS WAN Signaling System 7 Source Synchronous Serial Media Independent Interface Synchronous Transport Module Level 1 Time Division Multiplexing TDM over Internet Protocol TDM over Packet Timeslot Assigner Transmit User Datagram Protocol Voice over IP Virtual Private LAN Services Wide Area Network Glossary bundle – a virtual path configured at two endpoint TDM
PAGE 10
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 3. Applicable Standards Table 3-1. Applicable Standards SPECIFICATION IEEE IEEE 802.3 IEEE 1149.1 IETF RFC 4553 RFC 4618 RFC 5086 RFC 5087 ITU-T G.823 G.824 G.8261/Y.1361 I.363.1 I.363.2 I.366.2 O.151 O.161 Y.1413 Y.1414 Y.1452 Y.1453 MEF MEF 8 MFA MFA 4.0 MFA 5.0.0 MFA 8.0.
PAGE 11
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 4. Detailed Description The DS34S108 is an 8-port TDM-over-Packet (TDMoP) IC. The DS34S104, DS34S102 and DS34S101 have the same functionality as the DS34S108, except they have only 4, 2 or 1 ports, respectively. These sophisticated devices can map and demap multiple E1/T1 data streams or a single E3/T3/STS-1 data stream to and from IP, MPLS or Ethernet networks.
PAGE 12
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 5. Application Examples In Figure 5-1, a DS34S10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc. Figure 5-1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 5-2. TDMoP in Cellular Backhaul Other Possible Applications Point-to-Multipoint TDM Connectivity over IP/Ethernet The DS34S10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used as a virtual cross-connect.
PAGE 14
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 6. Block Diagram SD_D[31:0] SD_DQM[3:0] SD_A[11:0] SD_BA[1:0] SD_CLK SD_CS_N SD_WE_N SD_RAS_N SD_CAS_N Data Byte Enable Mask Address Bank Select Control CLK_HIGH CLK_CMN Figure 6-1. Top-Level Block Diagram CLAD1 38.88MHz 2.048/1.
PAGE 15
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 7. FEATURES Global Features • • • • • • • • • • • • TDMoP Interfaces o DS34S101: 1 E1/T1/serial TDM interface o DS34S102: 2 E1/T1/serial TDM interfaces o DS34S104: 4 E1/T1/serial TDM interfaces o DS34S108: 8 E1/T1/serial TDM interfaces o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDM interface o All four devices: each interface optionally configurable for serial operation for V.
PAGE 16
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 TDMoP TDM Interfaces • • • • • Supports single high-speed E3, T3 or STS-1 interface on port 1 or one (DS34S101), two (DS34S102), four (DS34S104) or eight (DS34S108) E1, T1 or serial interfaces For single high-speed E3, T3 or STS-1 interface, AAL1 or SAToP payload type is used For E1 or T1 interfaces, the following modes are available: o Unframed – E1/T1 pass-through mode (AAL1, SAToP or HDLC payload type) o Struct
PAGE 17
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 o o Robust to sudden significant constant delay changes Automatic transition to holdover when link break is detected TDMoP Delay Variation Compensation • • • • Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network Large maximum jitter buffer depths: o E1: up to 256 ms o T1 unframed: up to 340 ms o T1 framed: up to 256 ms o T1 framed with CAS: up to 192 ms o E3: up to
PAGE 18
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 9. PIN DESCRIPTIONS 9.1 Short Pin Descriptions Table 9-1.
PAGE 19
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) H_WR_BE2_N / SPI_SEL_N H_WR_BE3_N / SPI_CI H_READY_N H_INT TYPE(2) JTAG Interface JTRST_N JTCLK JTMS JTDI JTDO Reset and Factory Test Pins RST_SYS_N HIZ_N SCEN STMD MBIST_EN MBIST_DONE MBIST_FAIL TEST_CLK TST_CLD Power and Ground DVDDC DVDDIO DVSS ACVDD1, ACVDD2 ACVSS1, ACVSS2 I I Oz O PIN DESCRIPTION Host Write Enable Byte 2 or SPI Chip Select (Active Low) Host Write Enable Byte 3 (Active Low) or
PAGE 20
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 9.2 Detailed Pin Descriptions Table 9-2. TDM-over-Packet Engine TDM Interface Pins In this table, the transmit direction is the packet-to-TDM direction while the receive direction is the TDM-to-packet direction. See Figure 6-1. (1) PIN NAME TDMn_ACLK TDMn_TCLK (2) TYPE O 8mA Ipu PIN DESCRIPTION TDMoP Recovered Clock Output The clock recovered by the TDMoP clock recovery machine is output on this pin.
PAGE 21
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) TDMn_TSIG_CTS TYPE(2) O 8mA PIN DESCRIPTION Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10). Port[n]_cfg_reg.Int_type=specifies serial (00), E1 (01) or T1 (10) interface type. This pin is only active in external mode (GCR1.MODE=1). See the timing diagrams in Figure 14-8 through Figure 14-13.
PAGE 22
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) TYPE(2) PIN DESCRIPTION TDMoP Request To Send Input When the interface type is configured for serial, the request-to-send function of this pin is active. In this mode, the real-time status of this pin can be read from Port[n]_stat_reg1.RTS_P. Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0). Port[n]_cfg_reg.Int_type specifies serial (00), E1 (01) or T1 (10) interface type.
PAGE 23
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 9-4. Ethernet PHY Interface Pins (MII/RMII/SSMII) The PHY interface type is configured by General_cfg_reg0.MII_mode_select[1:0]. 00=MII, 01=Reduced MII (RMII), 11=Source Synchronous Serial MII (SSMII). The MII interface is described in IEEE 802.3-2005 Section 22. The RMII interface is described in this document: http://www.national.com/appinfo/networks/files/rmii_1_2.pdf.
PAGE 24
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) MII_RXD[3:0] TYPE(2) I PIN DESCRIPTION MII Receive Data Inputs In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0], on the rising edge of CLK_MII_RX. See the timing diagram in Figure 14-16. In RMII mode, receive data comes from the PHY two bits at a time on MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX. MII_RXD[1:0] are not used.
PAGE 25
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) CLK_HIGH TYPE(2) I PIN DESCRIPTION 19.44 MHz (2430*8 kHz). For systems using GPS, 8.184 MHz (1023*8 kHz). For systems connected by a single hop of 100 Mbit/s Ethernet where it is possible to lock the physical layer clock, 25 MHz (3125*8 kHz). For systems connected by a single hop of Gigabit Ethernet where it is possible to lock to the physical layer clock, 10MHz (1250*8 kHz).
PAGE 26
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 PIN NAME(1) H_WR_BE0_N / SPI_CLK H_WR_BE1_N / SPI_MOSI H_WR_BE2_N / SPI_SEL_N H_WR_BE3_N / SPI_CI H_READY_N TYPE(2) I I I I O 8mA PIN DESCRIPTION 1 = input data is latched on the trailing edge of the SCLK pulse; output data is updated on the leading edge H_WR_BE0_N: Host Write Enable Byte 0 (Active Low) In parallel interface mode during a write access this pin specifies whether or not byte 0 (H_D[7:0]) shou
PAGE 27
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 9-7. JTAG Interface Pins See the JTAG interface timing diagram in Figure 14-21. PIN NAME(1) JTRST_N TYPE(2) Ipu JTCLK I JTMS Ipu JTDI Ipu JTDO Oz 8mA PIN DESCRIPTION JTAG Test Reset (Active Low) This signal is used to asynchronously reset the test access port controller. After power up, JTRST_N must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode.
PAGE 28
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10. Functional Description 10.1 Power-Supply Considerations Due to the dual-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a 3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes because it could cause latchup. Two methods are available to prevent this.
PAGE 29
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 10-1. CPU Data Bus Widths Access to DAT_32_16_N Data Bus Chip Internal Value Width Resources 1 0 32 bits 16 bits 32 bit only 16 bit only Access to SDRAM Data Bus Bits MSB H_WR_BE Pins Used 8, 16, 32 bit 8, 16 bit H_D[31:0] H_D[15:0] H_D[31] H_D[15] 3:0 1:0 Burst accesses are not supported. The device uses the big-endian byte order, as explained in section 11.1.
PAGE 30
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The write access to the SDRAM is different than the write access to the chip. The SDRAM can be written with byte resolution using the four byte write enables. In contrast, internal chip resources are always written at full CPU data bus width (32 bits in Figure 10-2). The write byte enable signals should always be asserted when writing to internal device registers.
PAGE 31
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-5. Write Access to the SDRAM, 16-Bit Bus 16 bit data bus DAT_32_16_N[0] H_CS_N[0] H_AD[24:1] H_R_W_N[0] H_READY_N[0] [0] H_D[15:8] SDRAM WRITE ACCESS valid H_D[7:0] data ignored H_WR_BE1_N[0] H_WR_BE0_N[0] In 16-bit bus mode, read accesses to SDRAM are always 16 bits, as in Figure 10-6. Figure 10-6.
PAGE 32
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 • SPI_MISO is master data input, slave data output. • SPI_SEL_N is the slave chip select. The master initiates a data transfer by asserting SPI_SEL_N (low) and generating a sequence of SPI_CLK cycles accompanied by serial data on SPI_MOSI. During read cycles the slave outputs data on SPI_MISO. Each additional slave requires an additional slave chip-select wire.
PAGE 33
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.3.3 SPI Signals In SPI mode, the following CPU bus pins change their functionality and operate as SPI signals. • • Inputs o SPI_CLK is shared with H_WR_BE0_N o SPI_MOSI is shared with H_WR_BE1_N o SPI_SEL_N is shared with H_WR_BE2_N. Outputs o SPI_MISO is shared with H_D[0].
PAGE 34
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 signals in CPU bus mode (including being active low). At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. • The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care). • The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending with A1 (LSB).
PAGE 35
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 signals in CPU bus mode (including being active low). For a read access, all four of these bits should be 1. At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. • The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care). • The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending with A1 (LSB).
PAGE 36
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 • The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care). • The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status command. The value 00b represents a status command. At the same time, the slave transmits the opcode bits of the previous command on SPI_MISO. • The master then transmits 4 don’t care bits on SPI_MOSI.
PAGE 37
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The TDM-over-packet block also requires a 50 MHz or 75 MHz clock (±50 ppm or better) to clock its internal circuitry and the SDRAM interface (SD_CLK). When the CLK_SYS_S pin is low, a 50 MHz or 75 MHz clock applied to the CLK_SYS pin is passed directly to the TDMoP block.
PAGE 38
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-10.
PAGE 39
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.1.1 VLAN Tag As specified in IEEE Standard 802.1q, the twelve-bit VLAN identifier's tagged packets, enables the construction of a maximum of 4,096 distinct VLANs. For cases where this VLAN limit is inadequate VLAN stacking provides a twolevel VLAN tag structure, which extends the VLAN ID space to over 16 million VLANs.
PAGE 40
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 10-7. IPv4 Header Fields (UDP) Field Description IPVER IHL IP TOS Total Length Identification Flags Fragment Offset Time To Live Protocol IP Header Checksum Source IP Address Destination IP Address IP version number.
PAGE 41
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 10-9. IPv6 Header Fields (UDP) Field IPVER Traffic Class Flow Label Description IP version number, for IPv6 IPVER = 6 An 8-bit field similar to the type of service (ToS) field in IPv4. The 20-bit Flow Label field can be used to tag packets of a specific flow to differentiate the packets at the network layer. Similar to the Total Length field in IPv4.
PAGE 42
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.1.6 L2TPv3/IPv4 Header Figure 10-17. L2TPv3/IPv4 Header Format 0 0 1 1 2 3 IP HEADER IPVER 4 5 6 7 8 9 0 2 1 2 3 4 5 SOURCE IP 3 1 2 3 TOTAL 4 5 7 8 9 0 1 LENGTH FRAGMENT IP HEADER 6 OFFSET CHECKSUM ADDRESS IP ADDRESS L2TPv3 HEADER COOKIE 1 (OPTIONAL) COOKIE 2 (OPTIONAL) Description See Table 10-7. Must be set to 0x73 to signify L2TPv3 See Table 10-7. Table 10-13.
PAGE 43
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.1.7 L2TPv3/IPv6 Header Figure 10-18. L2TPv3/IPv6 Header Format 0 1 0 1 2 3 4 5 IPVER 6 7 8 9 2 0 1 2 3 4 5 6 7 8 TRAFFIC CLASS 3 0 9 1 2 3 4 5 6 7 8 0 9 1 FLOW LABEL PAYLOAD LENGTH NEXT HEADER IP HEADER SOURCE IP DESTINATION HOP LIMIT ADDRESS IP ADDRESS L2TPv3 HEADER SESSION ID = BUNDLE IDENTIFIER COOKIE 1 (OPTIONAL) COOKIE 2 (OPTIONAL) Table 10-14.
PAGE 44
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Field Description there is a failure of that direction of the bi-directional connection. This indication can be used to signal congestion or other network related faults. Receiving remote failure indication may trigger fall-back mechanisms for congestion avoidance. The R bit must be set after a preconfigured number of consecutive packets are not received, and must be cleared once packets are once again received.
PAGE 45
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SSRC Field Description Identifies the synchronization source. This identifier should be chosen randomly, with the intent that no two synchronization sources within the same RTP session have the same SSRC identifier. 10.6.1.10 TDM-over-Packet Payload This field can contain the following payload types: • AAL1 • HDLC • RAW (SAToP or CESoPSN formats) • OAM (VCCV or UDP/IP-specific).
PAGE 46
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-22.
PAGE 47
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.2 Typical Application In the application below (Figure 10-23), the device is embedded in a TDMoIP gateway to achieve TDM connectivity over a PSN. The TDM-over-Packet packet formats for both IP and MPLS are shown in Figure 10-24 and Figure 10-25, respectively. Figure 10-23. TDM Connectivity over a PSN Figure 10-24. TDMoP Packet Format in a Typical Application DA SA VLAN Tag Ethertype IP Header Optional IP Src.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-25. TDMoMPLS Packet Format in a Typical Application 1 2 3 4 DA SA VLAN Tag Ethertype Outer MPLS Inner MPLS Control Payload Type CRC-32 Label(s) Label Word Optional MPLS AAL1/ Bundle ID=A Optional HDLC/SAToP/ CESoPSN/OAM DA SA VLAN Tag Ethertype Outer MPLS Inner MPLS Control Payload Type CRC-32 Label(s) Label Word Optional MPLS AAL1/ Bundle ID=B Optional HDLC/SAToP/ CESoPSN/OAM 10.6.
PAGE 49
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 of the CLK_HIGH signal depend on the wander requirements of the recovered TDM clock. For applications where the recovered TDM clock must comply with G.823/G.824 requirements for traffic interfaces, typically a TCXO can be use as the source for the CLK_HIGH signal. For applications where the recovered clock must comply with G.823/G.
PAGE 50
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.5 CAS Handler 10.6.5.1 CAS Handler, TDM-to-Ethernet Direction In the TDM-to-Ethernet direction, the CAS handler receives the CAS bits (for structured-with-CAS AAL1/CESoPSN bundles) on the TDMn_RSIG_RTS signal.
PAGE 51
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces 0 31 ABCD (TS7) ABCD (TS6) ABCD (TS5) ABCD (TS4) ABCD (TS3) ABCD (TS2) ABCD (TS1) ABCD (TS0) ABCD (TS15) .. .. .. .. .. .. ABCD (TS8) ABCD (TS23) .. .. .. .. .. .. ABCD (TS16) ABCD (TS31) .. .. .. .. .. .. ABCD (TS24) Figure 10-28.
PAGE 52
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0) TDMn_TCLK Once in 3milliseconds TDMn_RX_SYNC TDMn_RSIG A B C D A Timeslot 22 B C D A Timeslot 23 B C D Timeslot 0 Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram TDMn_TCLK Once in 1.
PAGE 53
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-32.
PAGE 54
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-33. E1 MF Interface TSIG Timing Diagram TDMn_TCLK once in 2 milliseconds TDMn_TX_MF_CD TDMn_TSIG A B C D A Timeslot 30 B C Timeslot 31 D Timeslot 0 Figure 10-34. T1 ESF Interface TSIG Timing Diagram TDMn_TCLK Once in 3 milliseconds TDMn_TX_MF_CD TDMn_TSIG A B C D A Timeslot 22 B C D Timeslot 23 A B D C Timeslot 0 Figure 10-35.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-36. AAL1 Mapping, General The structure of the AAL1 header is shown in Table 10-21 below. Table 10-21. AAL1 Header Fields Length Field Description (bits) C SN CRC P 1 3 3 1 E Pointer 1 7 Indicates if there is a pointer in the second octet of the AAL1 SAR PDU. When set, a pointer exists.
PAGE 56
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SAR PDU payload contains 47 octets (376 bits) of TDM data without regard to frame alignment or timeslot byte alignment. All AAL1 SAR PDUs are non-P format for unstructured bundles. Structured bundles, for E1/T1 interfaces, support rates of N × 64 kbps, where N is the number of timeslots configured to be assigned to a bundle.
PAGE 57
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.7 HDLC Payload Type Machine Handling HDLC in TDM-over-Packet ensures efficient transport of CCS (common channel signaling, such as SS7), embedded in the TDM stream or other HDLC-based traffic, such as Frame Relay, according to IETF RFC 4618 (excluding clause 5.3 – PPP) and RFC 5087 (TDMoIP).
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.8 RAW Payload Type Machine The RAW payload type machine support the following bundle types: • Unstructured According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553 (SAToP). • Structured without CAS According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN). • Structured with CAS According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN). 10.6.8.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-40. CESoPSN Structured-Without-CAS Mapping TDM payload L2/L3 Header Control Word FRG bits = 00 (no fragmentation) 4 4 25 4 25 4 25 Frame 1 Frame N Frame 2 25 4 Frame 1 CRC Ethernet packet 25 4 Frame 2 25 Frame N The packetization delay of a CESoPSN structured-without-CAS bundle is: T = N x 125 µs (i.e.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-42.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-44.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.9 SDRAM and SDRAM Controller The device requires an external SDRAM for its operation. The following describes how the TDMoP block and the CPU use the SDRAM: The TDMoP block accesses these sections of the SDRAM: • Transmit buffers section This area stores outgoing packets created by the payload-type machines. It is a 1-Mbyte area with base address specified by the Tx_buf_base_add field in General_cfg_reg1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-45. SDRAM Access through the SDRAM Controller SDRAM CLOCK SDRAM CONTROLLER ARBITER ACCESS FROM HW BLOCKS RESET_N CPU PORT CONFIGURATION BITS OTHER PORTS CONFIGURATION REGISTER TDMoPacket CPU 10.6.10 Jitter Buffer Control (JBC) 10.6.10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-47.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 For T1 structured-with-CAS, multiply the above formula by 0.75. The jitter buffer depth is defined by the Rx_max_buff_size parameter found in the Bundle Configuration Tables. When the jitter buffer level reaches the value of Rx_max_buff_size, an overrun situation is declared.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 • For AAL1/HDLC/RAW structured bundles: the Jitter_buffer_index value is the number of the lowest timeslot in the bundle. For example, if the bundle consists of timeslots 2, 4, 17 on port 3, Jitter_buffer_index=0x2. • For unstructured bundles the Jitter_buffer_index value is 0x0. 10.6.10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-49.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.2 Buffer Descriptor First Dword Used for all paths. Located at offset 0x0 from the start of the buffer. Table 10-24.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.3 Buffer Descriptor Second Dword Located at offset 0x4 from the start of the buffer. 10.6.11.3.1 TDM  ETH and CPU  ETH Packets Table 10-25. Buffer Descriptor Second Dword Fields (TDM  ETH and CPU  ETH) Bits Data Element Description 31:15 14 Reserved Stamp 13:7 Ts_offset 6:0 Hdr2_length Must be set to zero. Indicates whether the packet should be time-stamped.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.4 Buffer Descriptor Third Dword Used for ETH  CPU packets. Located at offset 0x8 from start of the buffer. Table 10-27. Buffer Descriptor Third Dword Fields (ETH  CPU) Bits Data Element Description 31:0 Timestamp 32 bits timestamp latched by the packet classifier upon packet reception. Timestamp resolution is 100 µs or 1 µs as specified by the OAM_timestamp_resolution field in General_cfg_reg0. 10.6.11.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The CPU must define the number of buffers for each bundle by initializing the linked list for the bundle. Software prepares these buffers by writing the Ethernet, IP/MPLS/L2TPv3/MEF headers in advance, so that the payloadtype machines need only to write the packet payload. Since the headers contain bundle-specific data (e.g.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.8 TDM to Ethernet Flow Each payload-type machine receives the data of specific bundle timeslots and maps it into packets. To store a new packet in preparation, the machine extracts a pointer from the free buffer pool (section 10.6.11.7) and fills the associated buffer with TDM timeslot data, one by one.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.9 Ethernet to TDM Flow A packet arriving from the Ethernet port passes through the Ethernet MAC block. The MAC block does not store the packet, but it does calculate the CRC to verify packet data integrity. If the packet is bad, the MAC signals this to the packet classifier on the last word of the packet, and the packet classifier discards it.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.10 TDM to TDM (Cross-Connect) Flow Each payload-type machine receives the data of bundle-specific TDM timeslots and maps the data into Ethernet packets. To store a packet, the payload-type machine needs an SDRAM buffer which it gets by extracting a buffer pointer from the free buffer pool. It then fills the buffer as it processes the TDM timeslots.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.11 TDM to CPU Flow The payload-type machines identify the destination of their packets according to the per-bundle configuration. Upon getting the first byte of a packet in a bundle destined to the CPU, the machine needs a buffer to store the packet. It therefore checks whether a buffer is available in the TDM-to-CPU pool. If the pool is empty, the machine discards the current data.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.12 CPU to TDM Flow The Rx arbiter polls the CPU-to-TDM queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and there are no buffers pending in the Rx FIFO or the cross-connect queue, the Rx arbiter extracts the pointer and copies the relevant data from the SDRAM buffer to the appropriate payload-type machine.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.13 CPU to Ethernet Flow The Tx Ethernet interface polls the CPU-to-Ethernet queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and no buffers from the payload-type machines are waiting in the Ethernet Tx queue, the Tx Ethernet interface extracts the pointer and copies the relevant data from the SDRAM buffer to the Ethernet MAC block.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.11.14 Ethernet to CPU Flow Ethernet packets enter the chip via the Ethernet MAC block and the packet classifier into the Rx arbiter. When the Rx arbiter identifies that a packet is destined to the CPU, it extracts a pointer from the Ethernet-to-CPU pool (if the pool is empty, the Rx arbiter discards the packet) and stores the packet data into the SDRAM in the buffer indicated by the pointer.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 In half-duplex mode the start of transmission is deferred if MII_CRS (carrier sense) is active. If MII_COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. MII_CRS and MII_COL have no effect in full-duplex mode. Figure 10-58.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.12.2 Pause Packet Support Ethernet transmission pause in response to a received pause packet is enabled when Pause_enable=1 in the MAC_network_configuration register. When a valid pause packet is received, the MAC_pause_time register is updated with the packet’s pause time regardless of its current contents and regardless of the state of Pause_enable bit.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.13 Packet Classifier The Packet Classifier is part of the receive path, immediately following the Ethernet MAC block. It analyzes the header of each incoming packet, by comparing the header fields to the chip’s configured parameters, and then decides whether to discard the packet or add a buffer descriptor and forward the packet to the CPU or one of the payload-type machines. Section 11.4.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 assigned to the chip’s internal bundles, is discarded if Discard_Switch_6 is set. Otherwise it is transferred to the CPU. Discard_Switch_7: A packet recognized as OAM packet (see section 10.6.13.3) is discarded if Discard_Switch_7 is set. Otherwise it is transferred to the CPU. Discard_Switch_8: A packet with Ethertype equal to CPU_dest_ether_type configuration is discarded when Discard_Switch_8 is set.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.13.1 TDMoIP Port Number The TDMoIP_port_num1 and TDMoIP_port_num2 configuration fields are used by the block to identify UDP/IP TDMoIP packets. Although the chip has two of these fields, in most cases both fields should have the default value (0x085E) as assigned by IANA for TDM-over-Packet.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.6.13.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 10-62. Structure of Packets with Trailer HEADER PAYLOAD TRAILER CRC32 (1-12 BYTES) Packets with total size of 64 bytes or more (including CRC32) 60 bytes HEADER PAYLOAD PADDING TRAILER CRC32 (1-12 BYTES) Packets with total size of less than 64 bytes (including CRC32) The CRC is calculated over all packet bytes including over the trailer bytes.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The destination MAC/IP (and/or VLAN) of the duplicated packets can be different as the chip supports more than one MAC/IP address in the packet classifier. 10.6.17 OAM Signaling TDMoP bundles require a signaling mechanism to provide feedback regarding problems in the communications environment. In addition, such signaling can be used to collect statistics related to the performance of the underlying PSN.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 10.7 Global Resources See the top-level block diagram in Figure 6-1. Global resources in the device include CLAD1, CLAD2 and the CPU Interface block. These resources are configured in the global registers described in section 11.3. These registers also handle device identification, top-level mode configuration, I/O pin configuration, global resets, and top-level interrupts. 10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Interrupt Type 5. Tx_CAS_change 1. 2. 3. 4. 5. CW_bits_change 1. 2. 3. 4. JB_underrun_Pn 1. 2. 3. 4. ETH_MAC 5. 1. 2. 3. Interrupt Procedure them. Read the corresponding Rx CAS information from the Rx Line CAS registers (section 11.4.10). Read the Tx_CAS_change bits in the Intpend register to determine which port(s) are indicating Tx CAS change.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11. Device Registers 11.1 Addressing Device registers and memory can be accessed either 2 or 4 bytes at a time, as specified by configuration pin DAT_32_16_N. In the 16-bit addressing mode, addresses are multiples of 2, while in 32-bit addressing, addresses are multiples of 4. The prefix “0x” indicates hexadecimal (base 16) numbering, as does the suffix “h” (Example: 2FFh).
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 11-4. Partial Data Elements (16 to 32 bits long) 15 8 7 0 2 15 8 7 0 0 31 24 23 16 8 7 0 ADD ADD 24 23 31 16 15 0 SPI interface mode (H_CPU_SPI_N=0) always uses 32-bit addressing. See section 10.3. 11.2 Top-Level Memory Map Table 11-1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.3 Global Registers Functions contained in the global registers include device ID, CLAD configuration and top-level interrupt masking. The global register base address is 0x108,000. Table 11-2.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 IDR (Identification Device Register) 0x0C Bits Data Element Name R/W [31:16] [15:4] ID[31:16] ID[15:4] RO RO [3:0] ID[3:0] RO Default Description 0 These bits are always zero. See Device ID JTAG ID. These bits have the same information as the lower 12 bits of the Device ID portion of the JTAG ID register. See Table 12-2. See Device Revision JTAG ID.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4 TDM-over-Packet Registers The base address for the TDMoP registers is 0x0. Table 11-3.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.1 Configuration and Status Registers The base address for the TDMoP configuration and status registers is 0x0,000. Table 11-4.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Addr Offset 110 114 118 11C 120 124 128 12C 130 134 138 13C 140 144 Register Name Port2_status_reg1 Port2_status_reg2 Port3_status_reg1 Port3_status_reg2 Port4_status_reg1 Port4_status_reg2 Port5_status_reg1 Port6_status_reg2 Port6_status_reg1 Port6_status_reg2 Port7_status_reg1 Port7_status_reg2 Port8_status_reg1 Port8_status_reg2 Description Page Port 2 status bit register 1 Port 2 status bit register 2 Port 3
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 General_cfg_reg0 0x00 Bits Data Element Name R/W Reset Value [6:5] Fq R/W 0x0 [4:3] Col_width R/W 0x0 [2:1] CAS_latency R/W 0x2 [0] Rst_SDRAM_n R/W 0x0 R/W Reset Value General_cfg_reg1 0x04 Bits Data Element Name [31] RTP_timestamp_generation_ mode R/W 0x0 [30:24] Sw_packet_offset R/W 0x04 [23:19] Tx_payload_offset R/W 0x00 [18] Reserved R/W 0x0 [17:10] JBC_sig_base_add R/W
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 General_cfg_reg2 0x08 Bits Data Element Name R/W Reset Value [31:29] Rx_HDLC_min_flags R/W 0x0 [28:24] Reserved R/W 0x0 [23:20] Rx_SAToP/CESoPSN_discard_ mask R/W 0x0 [19:0] Reserved R/W 0x0 Description Minimum number flags between 2 adjacent HDLC frames transmitted on the TDM pins. The number of flags is equal to Rx_hdlc_min_flags + 1. Range: 1 – 8.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Port[n]_cfg_reg 0x08+n*4 Bits Data Element Name R/W Reset Value [22:21] Tx_defect_modifier R/W 0x0 [20] Port_Rx_enable (Rx means from Ethernet MII) R/W 0x0 [19] CTS R/W 0x1 [18] CD_en R/W 0x0 [17] CD R/W 0x1 [16] Loss R/W 0x0 [15:11] Adapt_JBC_indx R/W 0x00 [10:9] SF_to_ESF_low_CAS_bits R/W 0x0 [8] TSA_act_blk R/W 0x0 [7] Port_Tx_enable (Tx mean toward Ethernet MII) R/W 0x0
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Port[n]_cfg_reg 0x08+n*4 Bits [4] Data Element Name Two_clocks R/W R/W Reset Value 0x1 [3:2] Int_framed_type R/W 0x0 [1:0] Int_type R/W 0x1 Rev: 032609 Description In two-clock mode (Two-clocks=1) this field specifies the TDMn_TCLK edge on which TDMn_TX_SYNC, TDMn_TX_MF_CD are sampled and the edge on which TDMn_TX and TDMn_TSIG_CTS are updated.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Rst_reg 0x2C Bits Data Element Name R/W [31:28] Reserved [27:24] Rst_tx_port_num R/W 0x0 [23:18] Rst_tx_internal_bundle_num R/W 0x00 [17] Rst_tx_open/close R/W 0x0 [16] Rst_tx R/W 0x0 [15:7] [6:1] Reserved Rst_rx_internal_bundle_num R/W R/W 0x0 0x00 [0] Rst_rx R/ set 0x0 Rev: 032609 - Reset Value 0x0 Description Must be set to zero Port number associated with Rst_tx field (below).
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The TDM_cond_data_reg register below holds four octets to be transmitted as conditioning data in the TDM direction during jitter buffer underrun. This data applies to all bundle types.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Packet_classifier_cfg_reg2 0x40 Bits Data Element Name R/W Packet_classifier_cfg_reg3 0x44 Bits [31:29] [28] Data Element Name Reserved Discard_packet_length_ mismatch R/W R/W Reset Value Reset Value Packet_classifier_cfg_reg6. Relevant only for packets received from Ethernet port.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Packet_classifier_cfg_reg3 0x44 Bits Data Element Name R/W Reset Value [16] Discard_switch_0 R/W 0x0 [15:0] MAC_add1 R/W 0x0000 R/W Reset Value Packet_classifier_cfg_reg4 0x48 Bits Data Element Name [31:16] TDMoIP_port_num2 R/W 0x085E [15:0] TDMoIP_port_num1 R/W 0x085E R/W Reset Value Packet_classifier_cfg_reg5 0x4C Bits [31:0] Data Element Name MAC_add2 R/W 0x0 R/W Reset Value Packe
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Packet_classifier_cfg_reg7 0x54 Bits [15:0] Data Element Name vlan_2nd_tag_identifier R/W R/W 0x8100 R/W Reset Value Packet_classifier_cfg_reg8 0x58 Bits [31:0] Data Element Name Ipv4_add3 R/W 0x0 R/W Reset Value Packet_classifier_cfg_reg9 0x5C Bits Data Element Name Reset Value [31:16] Mef_ether_type R/W 0x88d8 [15:0] Mef_oam_ether_type R/W 0x0800 R/W Reset Value Packet_classifier_cfg_reg1
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Packet_classifier_cfg_reg13 0x6C Bits [31:0] Data Element Name Ipv6_add1[31:0] R/W [31:0] Data Element Name Ipv6_add2[127:96] R/W 0x0 R/W Reset Value Description R/W 0x0 This field holds bits 127:96 of the second of two IPv6 addresses for the device. The other address is held in registers starting with Packet_classifier_cfg_reg10. Relevant only for packets received from the Ethernet port.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Packet_classifier_cfg_reg18 0x80 Bits [15:0] Data Element Name VCCV_oam_value R/W R/W 0x0000 R/W Reset Value R/W 0x00 - 0x0000 R/W 0x000 CPU_rx_arb_max_fifo_level_reg 0xD4 Bits Data Element Name [31:25] Tx_arb_max_fifo_level [24:10] Reserved [9:0] Rx_arb_max_fifo_level Rev: 032609 Reset Value Description in the VCCV_oam_value field below. See section 10.6.13.3.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.1.2 TDMoP Status Registers The General_stat_reg register has latched status registers that indicate hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The Port[n]_stat_reg1 register has real-time (not latched) status fields. The index n indicates port number: 1-8 for DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 AAL1_Bundle[n]_cfg[63:32] 0x100+n*4 Bits Data Element Name R/W Reset Value [31:22] Rx_max_buff_size R/W None [21:20] Payload_type_machine R/W None [19] Tx_RTP (Tx is toward Ethernet MAC) R/W None [18] Control_Word_exists R/W None [17:16] Tx_dest R/W None [15:9] Rx_max_lost_packets R/W None [8:4] Number_of_ts R/W None [3] Rx_ discard_sanity_fail R/W None [2:1] Header_type R/W Non
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 AAL1_Bundle[n]_cfg[95:64] 0x200+n*4 Bits Data Element Name R/W Reset Value [10:6] Reserved R/W None [5:4] Tx_cond_octet_type R/W None [3:2] Rx_AAL1_bundle_type R/W None [1:0] Protection_mode R/W None AAL1_Bundle[n]_cfg[127:96] 0x300+n*4 Bits Data Element Name R/W Reset Value [31] Reserved R/W [30:16] Rx_PDVT R/W None [15] Rx_CAS_src R/W None [14] Rx_cell_chk_ignore R/W None [13]
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 AAL1_Bundle[n]_cfg[127:96] 0x300+n*4 Bits Data Element Name R/W Reset Value [7:4] Port_num R/W None [3:2] Tx_VLAN_stack R/W None [1] Rx_bundle_identifier_valid R/W None [0] Reserved R/W None AAL1_Bundle[n]_cfg[159:128] 0x400+n*4 Bits Data Element Name R/W Reset Value [31:23] Reserved R/W None [22] Rx_RTP R/W None [21:20] Rx_L2TPV3_cookies R/W None [19:15] [14:10] Reserved Packet_s
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 HDLC_Bundle[n]_cfg[63:32] 0x100+n*4 Bits Data Element Name R/W Reset Value [21:20] Payload_type_machine R/W None [19] Tx_RTP R/W None [18] Control_Word_exists R/W None [17:16] Tx_dest R/W None [15:11] Reserved R/W None [10:9] Packet_SN_mode R/W None [8:3] Reserved R/W None [2:1] Header_type R/W None [0] Tx_R_bit R/W None HDLC_Bundle[n]_cfg[95:64] 0x200+n*4 [31:16] [15:13] Rese
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 HDLC_Bundle[n]_cfg[127:96] 0x300+n*4 Bits Data Element Name R/W Reset Value [7:4] Port_num R/W None [3:2] Tx_VLAN_stack R/W None [1] Rx_Bundle_Identifier_valid R/W None [0] Reserved R/W None HDLC_Bundle[n]_cfg[159:128] 0x400+n*4 Bits Data Element Name R/W Reset Value 0x000 [31:22] Reserved [21:20] Rx_L2TPV3_cookies R/W None [19:16] Reserved R/W None [15:0] Tx_IP_checksum R/W None
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SAToP/CESoPSN_Bundle[n]_cfg[63:32] 0x100+n*4 Reset Bits Data Element Name R/W Value [21:20] Payload_type_machine R/W None [19] Tx_RTP R/W None [18] Control_Word_exists R/W None [17:16] Tx_dest R/W None [15:9] Rx_max_lost_packets R/W None [8:4] Number_of_ts R/W None [3] Rx_ discard_sanity_fail R/W None [2:1] Header_type R/W None [0] Tx_R_bit R/W None SAToP/CESoPSN_Bundle[n]_cfg[95:
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SAToP/CESoPSN_Bundle[n]_cfg[95:64] 0x200+n*4 Reset Bits Data Element Name R/W Value [15:13] Reserved R/W None [12:11] Tx_SATOP_bundle_type R/W None [10:6] Reserved R/W None [5:4] Tx_cond_octet_type R/W None [3:2] Rx_SAToP/CESoPSN_ bundle_type R/W None [1:0] Protection_mode R/W None SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300+n*4 Reset Bits Data Element Name R/W Value [31] Reserved R/W None
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300+n*4 Reset Bits Data Element Name R/W Value [7:4] Port_num R/W None [3:2] Tx_VLAN_stack [1] Rx_Bundle_Identifier_valid R/W None [0] Reserved R/W None SAToP/CESoPSN_Bundle[n]_cfg[159:128] 0x400+n*4 Reset Bits Data Element Name R/W Value [31:24] Reserved [23] Last_value_insertion R/W None [22] Rx_RTP R/W None [21:20] Rx_L2TPV3_cookies R/W None [19:16
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.3 Counters Each counter can be read from two different addresses. Reading from the first address—0x10,000 + offset—does not affect the counter value. Reading from the second address—0x11,000 + offset—causes the counter to be cleared after it is read. Table 11-6.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ethernet Rx AAL1 Lost Cells / Rx SAToP/CESoPSN Discarded Packets Counter 0x400+n*4 Reset Bits Data Element Name R/W Description Value [31:16] [15:0] Reserved Lost_AAL1_Rxd_cells / R None None Discarded_SAToP/CESoPSN_ Rxd_packets SAToP/CESoPSN – Number of received packets that were discarded by SAToP/CESoPSN hardware machine.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.3.2 Per Jitter Buffer Index Counters In the register description in this section, the index n indicates the jitter buffer number: 0 to 255. Jitter Buffer Underrun/Overrun Events Counter 0x800+n*4 Reset Bits Data Element Name R/W Value [31:8] [7:0] Reserved JBC_events R None None Description Must be set to zero Number of jitter buffer underrun/overrun events.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.4 Status Tables The TDMoP status tables hold indications of hardware events. Except where noted, these are latched status bits. For each bit, the value 1 indicates that the event occurred. A bit set to 1 maintains its value unless the host CPU changes it. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value. The base address for the TDMoP status tables is 0x12,000. 11.4.4.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Tx Payload Type Machine Status 0x200+n*4 Bits [1] [0] Data Element Name R/W Tx_HDLC_align_err Tx_AAL1_framing_mismatch / Tx_HDLC_CRC_err / Tx_SAToP/CESoPSN_framing_ mismatch R/W R/W Tx Buffers Status 0x400+n*4 Bits [31:1] [0] Data Element Name Reserved TDM_to_ETH_buff_err R/W R/W Packet Classifier Status 0x600+n*4 Bits Data Element Name R/W Reset Value None None Reset Value None None Reset Value [31:8]
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.5 Timeslot Assignment Tables Each port has two banks of timeslot assignment (TSA) tables, bank 1 and bank 2. While one bank is actively used by the TDMoP block, the other bank can be written by the CPU. The active bank for the port is specified by the TSA_act_blk field in the Port[n]_cfg_reg register. The base address for the TDMoP status tables is 0x18,000.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Bank1 Timeslot Assignment Registers Bank2 Timeslot Assignment Registers Bits [31:21] [20] [19] Data Element Name Reserved Remote_loop Local_loop Ports 1 to 4: 0x000+(port-1)*0x80+ts*4 Ports 5 to 8: 0x400+(port-5)*0x80+ts*4 Ports 1 to 4: 0x200+(port-1)*0x80+ts*4 Ports 5 to 8: 0x600+(port-5)*0x80+ts*4 Reset R/W Description Value R/W R/W None None None [18] Structured_type R/W [17:16] Timeslot_width R/W No
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.6 CPU Queues The pools and queue referred to in this section are shown in the block diagram in Figure 10-49. Whenever a queue or pool level exceeds the associated threshold register, a latched status bit is set in the CPU_Queues_change register which generates an interrupt unless masked by the associated mask bit in the CPU_Queues_mask register.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 TDM_to_CPU_pool_level 0x04 (0x06) Bits [31:8] [7:0] Data Element Name R/W Reserved Level RO TDM_to_CPU_pool_thresh 0x08 (0x0A) Bits [31:8] [7:0] Data Element Name Reserved Threshold R/W RO Reset Value 0x0 0x0 Reset Value 0x0 0x0 Description Must be set to zero Number of buffers currently stored in the pool. These are the buffers that are still available to the Tx payload type machines. Range: 0 to 128.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 CPU_to_ETH_q_level 0x1C (0x1E) Bits [31:6] [5:0] Data Element Name R/W Reserved Level RO CPU_to_ETH_q_thresh 0x20 (0x22) Bits [31:6] [5:0] Data Element Name R/W Reserved Threshold RO Reset Value 0x0 0x0 Reset Value 0x0 0x0 Description Must be set to zero Number of buffers currently stored in the queue. Range: 0 to 32.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.6.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 CPU_to_TDM_q_thresh 0x5C (0x5E) Bits Data Element Name R/W Reset Value Description an interrupt is generated. Range: 0 to 32. 11.4.6.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Rx_return_q_level 0x70 (0x72) Bits [31:6] [5:0] Data Element Name R/W Reserved Level RO Rx_return_q_thresh 0x74 (0x76) Bits [31:6] [5:0] Data Element Name R/W Reserved Threshold RO Reset Value 0x0 0x0 Reset Value 0x0 0x0 Description Must be set to zero Number of buffers currently stored in the queue. Range: 0 to 32.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.8 Jitter Buffer Control The base address for the TDMoP jitter buffer control is 0x30,000. In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31. The index n indicates the bundle number: 0 to 63. See section 10.6.10 for more information. Table 11-8.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.8.1.2 Structured AAL1/CESoPSN Status_and_level (port-1)*0x100+ts*8 Bits Data Element Name R/W [31:26] [25:16] Reserved Current_level RO RO [15:2] [1:0] Reserved Status RO RO 11.4.8.1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Min_and_max_level (port-1)*0x100+ts*8+4 Bits Data Element Name [15:10] [9:0] Reserved Maximal_level R/W RO RO Reset Value 0x00 None Description These bits are always zero The maximal level that the jitter buffer has reached since the last time this register was read. After this register is read the TDMoP block resets this field to zero.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Bundle_ts[n] 0xF00+n*4 Bits Rev: 032609 Data Element Name R/W Reset Value Description Note: When the interface type is Nx64k this field should be set to all 1s.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.9 Transmit Software CAS The base address for the TDMoP transmit software CAS register space is 0x38,000. For the CAS information transmitted in packets in the TDM-to-Ethernet direction, the CAS signaling information stored in these registers can be used instead of CAS bits coming into the TDMoP block on the TDMn_RSIG_RTS signals.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Tx_SW_CAS_TS7_TS0 0x000+(port-1)*0x10 Bits [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Data Element Name TS7_CAS_nibble TS6_CAS_nibble TS5_CAS_nibble TS4_CAS_nibble TS3_CAS_nibble TS2_CAS_nibble TS1_CAS_nibble TS0_CAS_nibble R/W R/W R/W R/W R/W R/W R/W R/W R/W Tx_SW_CAS_TS15_TS8 0x004+(port-1)*0x10 Bits [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Data Element Name TS15_CAS_nibble TS1
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.10 Receive Line CAS The base address for the TDMoP Rx line CAS register space is 0x40,000. These read-only registers allow the CPU to examine the state of the CAS signaling recovered from received packets and transmitted out of the TDMoP block on the TDMn_TSIG signals. See section 10.6.5.2 for more details. When Rx line CAS bits change, an interrupt is generated.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.11 Clock Recovery The base address for the TDMoP clock recovery register space is 0x48,000. Most of the registers in this section of the TDMoP block are not documented. The HAL (Hardware Abstraction Layer) software manages these registers. In the register descriptions in this section, the index port indicates port number: 1-8 for DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101. Table 11-12.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.12 Receive SW Conditioning Octet Select The base address for the TDMoP Rx software conditioning octet select register space is 0x50,000. These registers specify which of four conditioning bytes (TDM_cond_octet_a through TDM_cond_octet_d in TDM_cond_data_reg) the TDMoP block transmits on the TDMn_TX signals during an unassigned timeslot.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.13 Receive SW CAS The base address for the TDMoP Rx software CAS register space is 0x58,000. These registers specify the CAS signaling bits the TDMoP block transmits on the TDMn_TSIG signals during unassigned timeslots and during timeslots where CAS is not assigned. See section 10.6.5.2 for more details.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.14 Interrupt Controller The base address for the interrupt controller register space is 0x68,000. The Intpend register and the “change” registers listed below have latched status bits that indicate various TDMoP hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Addr Offset 0x0E4 0x0EC 0x0F4 0x0FC 0x100 0x104 0x140 0x144 0x148 0x14C 0x180 0x1C0 0x1C4 Register Name Tx_CAS_change_mask_P5 Tx_CAS_change_mask_P6 Tx_CAS_change_mask_P7 Tx_CAS_change_mask_P8 RTS_change RTS_mask CW_bits_change_low_bundles CW_bits_mask_low_bundles CW_bits_change_high_bundles CW_bits_mask_high_bundles CW_bits_change_mask CPU_Queues_change CPU_Queues_mask Description Page Tx CAS change mask for Por
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Intpend 0x000 Bits Data Element Name R/W Reset Value [15] JBC_underrun_P8 R/W 0x0 [14] JBC_underrun_P7 R/W 0x0 [13] JBC_underrun_P6 R/W 0x0 [12] JBC_underrun_P5 R/W 0x0 [11] JBC_underrun_P4 R/W 0x0 [10] JBC_underrun_P3 R/W 0x0 [9] JBC_underrun_P2 R/W 0x0 [8] JBC_underrun_P1 R/W 0x0 [7] Rx_CAS_change_P8 R/W 0x0 [6] Rx_CAS_change_P7 R/W 0x0 [5] Rx_CAS_change_P6 R/W 0x0 [4
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Intmask 0x004 Bits [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Data Element Name CW_Bits_change RTS_changes Tx_CAS_change_P8 Tx_CAS_change_P7 Tx_CAS_change_P6 Tx_CAS_change_P5 Tx_CAS_change_P4 Tx_CAS_change_P3 Tx_CAS_change_P2 Tx_CAS_change_P1 JBC_underrun_P8 JBC_underrun_P7 JBC_underrun_P6 JBC_underrun_P5 JBC_underrun_P4 JBC_underrun_P3 JBC
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Tx_CAS_change 0xC0+(port-1)*8 Bits [31:0] Data Element Name Tx_CAS_change R/W R/W Tx_CAS_change_mask 0xC4+(port-1)*8 Bits [31:0] Data Element Name Tx_CAS_change_maxk R/W R/W RTS_change 0x100 Bits [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Data Element Name Reserved RTS8_ change RTS7_ change RTS6_ change RTS5_ change RTS4_ change RTS3_ change RTS2_ change RTS1_ change R/W R/W R/W R/W R/W R/W R/W R/W R/W RTS_mask
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 CW_bits_mask_low_bundles 0x144 Bits Data Element Name R/W CW_bits_change_high_bundles 0x148 Bits [31:0] Data Element Name CW_bits_change R/W R/W CW_bits_mask_high_bundles 0x14C Bits [31:0] Data Element Name CW_bits_mask R/W R/W CW_bits_change_mask 0x180 Bits Data Element Name R/W - Reset Value Reset Value 0xFFFF FFFF Reset Value 0xFFFF FFFF Reset Value [31:6] [5] Reserved Rx_sync_loss R/W 0x0 Non
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 CPU_Queues_mask 0x1C4 Bits [31:10] [9] [8] [7] [6] [5] [4:3] [2] [1] [0] Data Element Name Reserved TDM_to_CPU_pool_thresh TDM_to_CPU_q_thresh CPU_to_ETH_q_thresh ETH_to_CPU_pool_thresh ETH_to_CPU_q_thresh Reserved CPU_to_TDM_q_thresh Tx_return_q_thresh Rx_return_q_thresh Rev: 032609 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description Must be set to zero Mask T
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.15 Packet Classifier The base address for the packet classifier register space is 0x70,000. In the register descriptions in this section the index n indicates register number: 1 to 8. These registers can store eight possible OAM bundle numbers. Table 11-16.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 11.4.16 Ethernet MAC The base address for the Ethernet MAC register space is 0x72,000. Configuration and status registers are listed in subsection 11.4.16.1. Counters are listed in subsection 11.4.16.2. 11.4.16.1 Ethernet MAC Configuration and Status Registers Table 11-17.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 MAC_network_control 0x000 Bits Data Element Name R/W Reset Value [3] Transmit_enable R/W [2] Rx_enable R/W 0x0 [1:0] Reserved - 0x0 R/W Reset Value MAC_network_configuration 0x004 Bits Data Element Name 0x0 [31:20] [19] Reserved Ignore_Rx_FCS R/W [18] Enable_half_duplex_Rx R/W 0x0 [17] [16] Reserved Rx_length_field_checking_enabl e R/W 0x0 0x0 [15:14] [13] Reserved Pause_enable R/W 0
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 MAC_network_status 0x008 Bits [31:3] [2] [1:0] Data Element Name Reserved PHY_access_has_completed Reserved R/W RO - MAC_transmit_status 0x014 Bits Data Element Name R/W Reset Value 0x0 0x1 0x0 Reset Value [31:7] [6] Reserved Transmit_underrun R/W 0x0 0x0 [5:3] [2] Reserved Retry_limit_exceeded R/W 0x0 0x0 [1] [0] Collision_occurred Reserved R/W - 0x0 0x0 Description Must be set to zero 1 = PHY ma
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 MAC_interrupt_enable 0x028 Bits [5] [4] [3:1] [0] Data Element Name R/W Retry_limit_exceeded Ethernet_transmit_underrun Reserved Management_packet_sent WO WO WO MAC_interrupt_disable 0x02C Bits [31:14] [13] [12] [11:6] [5] [4] [3:1] [0] Data Element Name R/W Reserved Pause_time_zero Pause_packet_ Rxd Reserved Retry_limit_exceeded Ethernet_transmit_underrun Reserved Management_packet_sent WO WO WO WO WO MAC_
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 The MAC_PHY_maintenance register below enables the MAC to communicate with a PHY by means of the MDIO interface. It is used during auto negotiation to ensure that the MAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 MAC_transmit_paulse_quantum 0x0BC Bits [31:16] [15:0] Data Element Name Reserved Pause_time R/W R/W 0x0000 0xFFFF R/W Reset Value PHY_SMII_status 0x0C0 Bits Data Element Name Reset Value [31:21] [20] Reserved SMII_speed RO RO 0x0000 None [19] SMII_Duplex RO None [18] SMII_Link RO None [17] SMII_Jabber RO None [16] SMII_False_Carrier RO None [15:0] Reserved RO 0x0000 Description Must b
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Pause_packets_Rxd_OK 0x03C Bits [31:16] [15:0] Data Element Name Reserved Pause_packets_Rxd_OK R/W R/W Packets_transmitted_OK 0x040 Bits [31:0] Data Element Name Packets_transmitted_OK R/W R/W Single_collision_packets 0x044 Bits [31:16] [15:0] Data Element Name Reserved Single_collision_packets R/W R/W Multiple_collision_packets 0x048 Bits [31:16] [15:0] Data Element Name Reserved Multiple_collision_packets
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Alignment_errors 0x054 Bits [31:8] [7:0] Data Element Name Reserved Alignment_errors R/W R/W Deferred_transmission_packets 0x058 Bits [31:16] [15:0] Data Element Name Reserved Deferred_transmission_packets R/W R/W Late_collisions 0x05C Bits [31:8] [7:0] Data Element Name Reserved Late_collisions R/W R/W Excessive_collisions 0x060 Bits [31:8] [7:0] Data Element Name Reserved Excessive_collisions R/W R/W Tr
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Carrier_sense_errors 0x068 Bits [31:8] [7:0] Data Element Name Reserved Carrier_sense_errors R/W R/W Rx_symbol_errors 0x074 Bits [31:8] [7:0] Data Element Name Reserved Rx_symbol_errors R/W R/W Excessive_length_errors 0x078 Bits [31:8] [7:0] Data Element Name Reserved Excessive_length_packets R/W R/W Rx_jabbers 0x07C Bits [31:8] [7:0] Data Element Name Reserved Rx_jabbers R/W R/W Undersize_packets 0x080 B
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 SQE_test_errors 0x084 Bits [31:8] [7:0] Data Element Name Reserved SQE_test_errors R/W R/W Transmitted_pause_packets 0x08C Bits [31:16] [15:0] Data Element Name R/W Reserved Transmitted_pause_packets R/W Rev: 032609 Reset Value 0x0 0x0 Reset Value 0x0 0x0 Description Must be set to zero An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interpacket gap
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 12. JTAG Information For the latest JTAG model, search under http://www.maxim-ic.com/tools/bsdl/. JTAG Description The device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP and IDCODE. See Figure 12-1 for a block diagram. The device contains the following items which meet the requirements set by the IEEE 1149.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 12-2. JTAG TAP Controller State Machine Test-Logic-Reset 1 0 0 Run-Test/Idle 1 Select DR-Scan 1 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 Exit1-IR 0 0 Pause-DR 1 Pause-IR 0 0 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 Exit1-DR 0 1 Select IR-Scan 0 Update-IR 1 0 Test-Logic-Reset.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the PauseDR state. Pause-DR. Shifting of the Test registers is halted while in this state. All Test registers selected by the current instruction retain their previous state.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Table 12-1. JTAG Instruction Codes Instructions SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Selected Register Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification Instruction Codes 010 111 000 011 100 001 SAMPLE/PRELOAD. A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Identification Register. The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state. Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is 32 bits in length.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 13. DC Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input, Bi-directional or Open Drain Output Lead with Respect to DVSS .............................................................................................-0.5V to +5.5V Supply Voltage (DVDDIO) with Respect to DVSS...............................................................................-0.5V to +3.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 14. AC Timing Characteristics Table 14-1. Input Pin Transition Time Requirements PARAMETER SYMBOL CONDITIONS Rise Time tr Fall Time tf MIN TYP MAX UNITS 10 to 90% of DVDDIO 6 ns 90 to 10% of DVDDIO 6 ns 14.1 CPU Interface Timing Table 14-2.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-2. CPU Interface Write Cycle Timing T43 H_CS_N T35 T36 T33 T34 H_R_W_N H_AD[24:1] T40 H_WR_BEx_N[3:0] T31 T32 H_D[31:0](input) T26 T37 H_READY_N Figure 14-3. CPU Interface Read Cycle Timing T43 H_CS_N T35 T36 T33 T34 H_R_W_N H_AD[24:1] T22 H_D[31:0](output) T26 T44 T37 H_READY_N 14.2 SPI Interface Timing Table 14-3.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-4. SPI interface Timing (SPI_CP = 0) T230 SPI_SEL_N T231 SPI_CLK(CI=0) SPI_CLK(CI=1) T236 T233 T233 T232 T232 T237 SPI_MISO(output) T235 T234 SPI_MOSI(input) Figure 14-5. SPI interface Timing (SPI_CP = 1) T230 SPI_SEL_N T231 SPI_CLK(CI=0) SPI_CLK(CI=1) T233 T236 T232 T233 T237 SPI_MISO(output) T235 T234 SPI_MOSI(input) 14.3 SDRAM Interface Timing Table 14-4.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-6.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-7.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 14.4 TDM-over-Packet TDM Interface Timing Table 14-5.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-9. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) T105 T100 TDMn_TCLK T101 T102 T101 T102 DMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC TDMn_TX_MF_CD,TDMn_TX_SYNC T104 T103 TDMn_TX,TDMn_TSIG_CTS Figure 14-10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-12. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1) T106 T107 TDMn_RCLK T109 T110 TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC T106 TDMn_TCLK T104 T103 TDMn_TX,TDMn_TSIG_CTS T101 T102 TDMn_TX_MF_CD,TDMn_TX_SYNC Figure 14-13.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 14.5 Ethernet MII/RMII/SSMII Interface Timing Table 14-7. MII Management Interface AC Characteristics PARAMETER SYMBOL MDC Period (Note 1) MDC to MDIO Output Hold (Note 1) MDC to MDIO Output Valid (Note 1) MDIO Input Setup Prior to MDC Rising MDIO Input Hold After MDC Rising T150 T151 T152 T153 T154 NOTES: 1. Valid for 50 MHz CLK_SYS and MDC_frequency = 0x02.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-16. MII Interface Input Signal Timing T158 T180 CLK_MII_RX T159 T160 MII_RXD,MII_RX_DV,MII_RX_ERR Table 14-10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 14-19. SSMII Interface Output Signal Timing T171 T189 CLK_SSMII_TX T172 MII_TXD_0(SSMII_TXD) T172 MII_TXD_1(SSMII_TX_SYNC) Figure 14-20. SSMII Interface Input Signal Timing T171 T189 CLK_MII_RX(CLK_SSMII_RX) T175 T176 T175 T176 MII_RXD_0(SSMII_RXD) MII_RXD_1(SSMII_RX_SYNC) NOTES FOR SECTION 14.5: 1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 14.7 JTAG Interface Timing Table 14-15. JTAG Interface Timing PARAMETER JTCLK Clock Period JTCLK Clock High / Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO Hi-Z Delay JTRST_N Width Low Time NOTES: 1. Clock can be stopped high or low. 2. Not tested during production test.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 15. Applications 15.1 Connecting a Serial Interface Transceiver Figure 15-1 below shows the connection of one port of a DS34S10x chip to a serial interface transceiver such as V.35 or RS-530. The figure shows one port in a DCE (Data Communications Equipment) application. All other ports can be connected in the same way. Each direction (Tx and Rx) has its own clock.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 15.2 Connecting an Ethernet PHY or MAC The figures below show the connection of the Ethernet port to a PHY or MAC device, in MII, RMII, and SSMII modes. Figure 15-2.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode MII _TXD[3:2] TXD [1:0] MII _RXD[3:2] RXD [1:0] MII _TX_EN TX_EN MII _RX_DV RX_DV DS34S10x MII _RX _ERR RX_ERR CLK_MII _TX CLK MAC 50 MHz OSC. Figure 15-6.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 For the applications above, apply the following layout considerations: • • • • • Provide termination on all high-speed interface signals and clock lines. Provide impedance matching on long traces to prevent reflections. Keep the clock traces away from all other signals to minimize mutual interference. In RMII mode, a very low skew clock buffer/driver is recommended to maximize the timing budget.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 15-9.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 15-10.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 15.4.2 Connecting the H_READY_N Signal The H_READY_N output should be connected to the MPC860 TA input. The CPU bus operates asynchronously. The TA of the MPC860 is a synchronous input (i.e., needs to meet set-up and hold times). The designer should synchronize H_READY_N to the MPC860 clock by means of a CPLD, which uses the MPC860 reference clock.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 15.5 Working in SPI Mode The following table shows the I/O connections for operating in SPI mode. Table 15-1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 16. PIN ASSIGNMENTS 16.1 Board Design for Multiple DS34S101/2/4 Devices The DS34S101, DS34S102 and DS34S104 require the same footprint on the board. It is recommended that boards be design to support the use of higher port-count devices in a lower port-count socket. If this is done, unused inputs, input/outputs, and outputs must be biased appropriately.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ball DS34S104 Socket DS34S102 Socket DS34S101 Socket L12 L5 M5 N10 DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO N7 N8 N9 G10 DVDDIO DVDDIO DVDDIO DVSS DVDDIO DVDDIO DVDDIO DVSS DVDDIO DVDDIO DVDDIO DVSS G11 G6 G7 G8 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS G9 H10 H11 H5 H6 H7 H8 H9 J10 J11 J6 J7 J8 J9 K10 K11 K6 K7 K8 K9 L10 L11 L6 L7 L8 L9 R13
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ball DS34S104 Socket DS34S102 Socket DS34S101 Socket B10 D13 P14 A10 H_AD[19] H_AD[2] H_AD[20] H_AD[21] H_AD[19] H_AD[2] H_AD[20] H_AD[21] H_AD[19] H_AD[2] H_AD[20] H_AD[21] B11 N14 A11 P13 H_AD[22] H_AD[23] H_AD[24] H_AD[3] H_AD[22] H_AD[23] H_AD[24] H_AD[3] H_AD[22] H_AD[23] H_AD[24] H_AD[3] D10 E13 D11 N13 H_AD[4] H_AD[5] H_AD[6] H_AD[7] H_AD[4] H_AD[5] H_AD[6] H_AD[7] H_AD[4] H_AD[5] H_AD[6] H_AD[7
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ball DS34S104 Socket DS34S102 Socket DS34S101 Socket T13 N12 R12 C13 H_INT[0] H_R_W_N/SPI_CP H_READY_N H_WR_BE0_N/SPI_CLK H_INT[0] H_R_W_N/SPI_CP H_READY_N H_WR_BE0_N/SPI_CLK H_INT[0] H_R_W_N/SPI_CP H_READY_N H_WR_BE0_N/SPI_CLK P12 E10 C11 N11 H_WR_BE1_N/SPI_MOSI H_WR_BE2_N/SPI_SEL_N H_WR_BE3_N/SPI_CI HIZ_N H_WR_BE1_N/SPI_MOSI H_WR_BE2_N/SPI_SEL_N H_WR_BE3_N/SPI_CI HIZ_N H_WR_BE1_N/SPI_MOSI H_WR_BE2_N/SPI_
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ball DS34S104 Socket DS34S102 Socket DS34S101 Socket C1 B2 C2 E4 SD_CAS_N SD_CLK SD_CS_N SD_D[0] SD_CAS_N SD_CLK SD_CS_N SD_D[0] SD_CAS_N SD_CLK SD_CS_N SD_D[0] B5 B6 F3 A6 SD_D[1] SD_D[10] SD_D[11] SD_D[12] SD_D[1] SD_D[10] SD_D[11] SD_D[12] SD_D[1] SD_D[10] SD_D[11] SD_D[12] F4 B8 D7 F5 SD_D[13] SD_D[14] SD_D[15] SD_D[16] SD_D[13] SD_D[14] SD_D[15] SD_D[16] SD_D[13] SD_D[14] SD_D[15] SD_D[16] C7 A7
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Ball DS34S104 Socket DS34S102 Socket DS34S101 Socket P6 T4 R7 R6 TDM1_TSIG_CTS TDM1_TX TDM1_TX_MF_CD TDM1_TX_SYNC TDM1_TSIG_CTS TDM1_TX TDM1_TX_MF_CD TDM1_TX_SYNC TDM1_TSIG_CTS TDM1_TX TDM1_TX_MF_CD TDM1_TX_SYNC R1 P4 T3 P2 TDM2_ACLK TDM2_RCLK TDM2_RSIG_RTS TDM2_RX TDM2_ACLK TDM2_RCLK TDM2_RSIG_RTS TDM2_RX NC NC NC NC T1 P3 T2 P1 TDM2_RX_SYNC TDM2_TCLK TDM2_TSIG_CTS TDM2_TX TDM2_RX_SYNC TDM2_TCLK TDM2_T
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 16.2 DS34S101 Pin Assignment Figure 16-1.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 16.3 DS34S102 Pin Assignment Figure 16-2.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 16.4 DS34S104 Pin Assignment Figure 16-3.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 16.5 DS34S108 Pin Assignment Table 16-2.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Signal Name DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVDDIO DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS Rev: 032609 Ball L9 M14 M9 N14 N9 P10 P11 P12 P13 R2 U2 V3 W1 A10 A14 A16 A8 AA1 AB11 AB13 AB15 AB9 B1 B
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Signal Name DVSS DVSS DVSS DVSS DVSS DVSS DVSS H_AD[1] H_AD[10] H_AD[11] H_AD[12] H_AD[13] H_AD[14] H_AD[15] H_AD[16] H_AD[17] Rev: 032609 Ball U17 U6 W19 W2 W4 Y12 Y3 L18 N22 L15 P21 N16 N20 P22 N19 R21 Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ball AB14 AB2 AB3 AB4 AB5 AB6 AB7 AB8 B13 B15 B3 B4 B5 B6 B7 B9 Signal Name SD_A[10] SD_A[11] SD_A[2] SD_A[3] SD_A[4] SD_A[5] SD_A[6] SD_A[7] SD_A[8]
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 Figure 16-4.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 17. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. DS34S101, DS34S102 and DS34S108 have a 256-lead thermally enhanced chip-scale ball grid array (TECSBGA) package. The TECSBGA package dimensions are shown in Maxim document 21-0353. DS34S108 has a 484-lead thermally enhanced ball grid array (TEBGA) package.
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108 19. Data Sheet Revision History REVISION DATE 071108 100108 DESCRIPTION Initial release. In the Ordering Information table on page 1, removed the asterisks and footnotes that indicated DS34S101, DS34S102 and DS34S104 were future products. In Table 11-11, Table 11-13, Table 11-14 and Table 11-15, corrected the index variable in the Description column from n to ts to match the other columns.