9-4835; 8/09 DS34T101, DS34T102, DS34T104, DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table of Contents 1 INTRODUCTION ...................................................................................................................................10 2 ACRONYMS AND GLOSSARY............................................................................................................10 3 APPLICABLE STANDARDS ...............................................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.9.1 TDMoP Interrupts .................................................................................................................................. 104 10.9.2 LIU, Framer and BERT Interrupts ......................................................................................................... 106 10.10 ELASTIC STORES AND FRAMER SYSTEM INTERFACE ..............................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.13 Receive SW CAS ................................................................................................................................ 206 11.4.14 Interrupt Controller............................................................................................................................... 207 11.4.15 Packet Classifier...............................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 List of Figures Figure 5-1. TDMoP in a Metropolitan Packet Switched Network .............................................................................. 16 Figure 5-2. TDMoP in Cellular Backhaul ................................................................................................................... 17 Figure 6-1. Top-Level Block Diagram ...................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-48. Jitter Buffer Parameters ..................................................................................................................... 82 Figure 10-49. TDM-over-Packet Data Flow Diagram ............................................................................................... 84 Figure 10-50. Free Buffer Pool Operation ........................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-19. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1) ............... 337 Figure 14-20. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0) ............... 337 Figure 14-21. MII Management Interface Timing ................................................................................................... 338 Figure 14-22. MII Interface Output Signal Timing....
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-14. IPv6 Header Fields (L2TPv3) .............................................................................................................. 60 Table 10-15. Control Word Fields............................................................................................................................. 60 Table 10-16. RTP Header Fields .........................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 11-10. Transmit Software CAS Registers..................................................................................................... 201 Table 11-11. Receive Line CAS Registers ............................................................................................................. 203 Table 11-12. Clock Recovery Registers ..............................................................................
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 1 Introduction The DS34T101/2/4/8 family of products combine E1/T1 LIUs and framers and TDM-over-packet circuit emulation circuitry into one die. Dedicated payload-type engines are included for TDMoIP (AAL1), CESoPSN, SAToP, and HDLC.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 LIU LOF LOS MAC MEF MFA MII MPLS OC-3 OCXO OFE OSI OSI-RM PDU PDV PE PRBS PSN PSTN PWE3 QoS RMII Rx or RX SAR SAToP SDH SMII SN SONET SS7 SSMII STM-1 TDM TDMoIP TDMoP TSA Tx or TX UDP VoIP VPLS WAN Line Interface Unit Loss of Frame (i.e.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Glossary BERT – Bit Error Rate Tester, a function used to test the integrity of a data link. A two-block set consisting of a Tx BERT that generates pseudo-random or repetitive patterns and optionally inserts bit errors into the sequence, and an Rx BERT that synchronizes to an incoming pattern and count bit errors.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 3 Applicable Standards Table 3-1. Applicable Standards SPECIFICATION ANSI T1.102 T1.107 T1.231.02 T1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SPECIFICATION O.161 Y.1413 Y.1414 Y.1452 Y.1453 MEF MEF 8 MFA MFA 4.0 MFA 5.0.0 MFA 8.0.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e. frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service interruption.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 5 Application Examples In Figure 5-1, a DS34T10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc. Figure 5-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 5-2. TDMoP in Cellular Backhaul Other Possible Applications Point-to-Multipoint TDM Connectivity over IP/Ethernet The DS34T10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used as a virtual cross-connect.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 6 Block Diagram Figure 6-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 6-2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 7 FEATURES Global Features TDMoP Interfaces o DS34T101: 1 E1/T1 LIU/Framer/TDMoP interface o DS34T102: 2 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T104: 4 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T108: 8 E1/T1 LIUs/Framers/TDMoP interfaces o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDMoP interface o All four devices: each interface optionally configurable for serial oper
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 T1 DSX-1 line build-outs T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB E1 waveforms include G.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Ability to generate RAI (yellow alarm) according to the Japanese standard T1 to E1 conversion Framer/Formatter TDM Interface Independent two-frame receive and transmit elastic stores Independent control and clocking Controlled slip capability with status Support for T1-to-E1 conversion Ability to pass the T1 F-bit position through the elastic stores in the 2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Each bundle carries a data stream from one TDM interface over IP/MPLS/Ethernet PSN from TDMoP source device to TDMoP destination device Each bundle may be for N x 64kbps, an entire E1, T1, E3, T3 or STS-1, or an arbitrary serial data stream Each bundle is unidirectional (but frequently coupled with opposite-direction bundle for bidirectional communication) Multiple bundles can be transported between
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Test and Diagnostics IEEE 1149.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 8 Overview of Major Operational Modes 8.1 Internal Mode The default mode of the device is internal one-clock mode. Internal mode is used to internally connect the framers to the TDMoP block. Internal mode additionally configures many unused TDM interface output pins to drive low. Unused TDM interface input pins are ignored.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 8.1.1 Internal One-Clock Mode In internal one-clock mode (GCR1.CLKMODE=0) the receive direction of each TDM port uses the same clock as the transmit direction of that port. The transmit formatter and the receive framer are therefore synchronized together.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 8-3. Internal Two Clock Mode (Framed) RCLK[8..1] ACLK[8..1] E1CLK T1CLK ECLK[8..1] pin CLKCNTL bits Framer port n SYNCNTL bits Connected to LIU TCLKOn TPOSn TNEGn TCLKn TSERn TSYNCn TSYNC[8..
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 9 PIN DESCRIPTIONS 9.1 Short Pin Descriptions Table 9-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) TYPE(2) CLK_MII_RX MII_RXD[3:0] MII_RX_DV MII_RX_ERR MII_COL MII_CRS MDC MDIO I I I I I I O IOpu PIN DESCRIPTION MII Receive Clock Input MII Receive Data Inputs MII Receive Data Valid Input MII Receive Error Input MII Collision Input MII Carrier Sense Input PHY Management Clock Output PHY Management Data Input/Output Global Clocks CLK_SYS_S CLK_SYS CLK_CMN CLK_HIGH MCLK I I I I I System Clock Selec
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Note 1: In pin names, the suffix “n” stands for port number: n=1 to 8 for DS34T108; n=1 to 4 for DS34T104; n=2 for DS34T102; n=1 for DS34T101. All pin names ending in “_N” are active low. Note 2: All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-3. External E1/T1 LIU Line Interface Pins TYPE(2) PIN DESCRIPTION PIN NAME(1) TCLKOn O Transmit Clock Output 8mA TCLKOn: This signal is normally synchronous with TCLKFn. However, when framer loopback or payload loopback is enabled (RCR3.FLB=1, PLB=1) it becomes synchronous with RCLKFn/RCLKn. When the internal LIU is disabled (GCR2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-4. Framer TDM Interface Pins TYPE(2) PIN DESCRIPTION PIN NAME(1) TCLKFn I Transmit Clock Input to Formatter This pin is only active in external mode (GCR1.MODE=1). In this mode, TCLKFn is the 1.544MHz or 2.048MHz clock that clocks the transmit formatter. When the transmit elastic store is disabled (TESCR.TESE=0), TSERn and TSYNCn/TSSYNCn are latched on the falling edge of TCLKFn.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) RSYSCLKn TYPE(2) I RSERn O 8mA RSYNCn IO 8mA PIN DESCRIPTION Receive System Clock Input This pin is only active in external mode (GCR1.MODE=1). When the receive elastic store is enabled (RESCR.RESE=1), RSERn, RFSYNCn/ RMSYNCn and RSYNCn (configured as an output) are clocked out of the system side (i.e. the cross-connect side) of the receive elastic store on the rising edge of RSYSCLKn.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) RLOFn/RLOSn TYPE(2) O 8mA PIN DESCRIPTION the cross-connect side) side of the elastic store. In E1 mode, RIOCR.RSMS2 specifies whether RMSYNCn pulses on CAS (0) or CRC-4 (1) multiframe boundaries. GCR1.LOSS=0 configures this pin to be RLOFn while LOSS=1 configures it to be RLOSn.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) TDMn_TX_MF_CD TYPE(2) IOpd PIN DESCRIPTION positive integer (example: if N=16, it pulses every 2ms). Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0). This pin is only active in external mode (GCR1.MODE=1). See the timing diagrams in Figure 14-15 through Figure 14-20.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) TYPE(2) PIN DESCRIPTION present on the TDMn_RX pin. This pulse must be repeated every N*125s where N is a positive integer (example: if N=16, it pulses every 2ms). In one-clock mode, this signal is ignored and TDMn_TX_SYNC specifies frame alignment for both the transmit and receive interfaces of the TDMoP engine. TDMn_RSIG_RTS Ipu Port[n]_cfg_reg.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-7. Ethernet PHY Interface Pins (MII/RMII/SSMII) The PHY interface type is configured by General_cfg_reg0.MII_mode_select[1:0]. 00=MII, 01=Reduced MII (RMII), 11=Source Synchronous Serial MII (SSMII). The MII interface is described in IEEE 802.3-2005 Section 22. The RMII interface is described in this document: http://www.national.com/appinfo/networks/files/rmii_1_2.pdf.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) MII_RXD[3:0] TYPE(2) I PIN DESCRIPTION MII Receive Data Inputs In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0], on the rising edge of CLK_MII_RX. See the timing diagram in Figure 14-23. In RMII mode, receive data comes from the PHY two bits at a time on MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX. MII_RXD[1:0] are not used.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-8. Global Clock Pins TYPE(2) PIN DESCRIPTION PIN NAME(1) CLK_SYS_S Ipd System Clock Selection Input This pin specifies the frequency of the clock applied to the CLK_SYS pin. See section 10.4. 0 = 50 or 75 MHz 1 = 25 MHz CLK_SYS I System Clock Input A 25 MHz, 50 MHz or 75 MHz clock (50 ppm or better) must be applied to this pin to clock TDM-over-Packet internal circuitry and the SDRAM interface (SD_CLK).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-9. CPU Interface Pins See the parallel interface timing diagrams in Figure 14-9 and Figure 14-10 and the SPI timing diagrams in Figure 14-11 and Figure 14-12.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 PIN NAME(1) H_WR_BE2_N / SPI_SEL_N H_WR_BE3_N / SPI_CI H_READY_N TYPE(2) I I O 8mA PIN DESCRIPTION H_WR_BE2_N: Host Write Enable Byte 2 (Active Low) In 32-bit parallel interface mode during a write access this pin specifies whether or not byte 2 (H_D[15:8]) should be written to the device. In 16-bit parallel interface mode this pin is ignored and should be pulled high or low.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-10. JTAG Interface Pins See the JTAG interface timing diagram in Figure 14-28. PIN NAME(1) JTRST_N TYPE(2) Ipu JTCLK I JTMS Ipu JTDI Ipu JTDO Oz 8mA PIN DESCRIPTION JTAG Test Reset (Active Low) This signal is used to asynchronously reset the test access port controller. After power up, JTRST_N must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 9-12. Power and Ground Pins TYPE(2) PIN DESCRIPTION PIN NAME(1) DVDDC P 1.8V Core Voltage for Framers and TDM-over-Packet Digital Logic (17 pins) DVDDIO P 3.3V for I/O Pins (16 pins) DVSS P Ground for Framers, TDM-over-Packet and I/O Pins (31 pins) DVDDLIU P 3.3V for LIU Digital Logic (2 pins) DVSSLIU P Ground for LIU Digital Logic (2 pins) ATVDDn P 3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10 Functional Description 10.1 Power-Supply Considerations Due to the dual-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a 3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes because it could cause latchup. Two methods are available to prevent this.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-1. CPU Data Bus Widths Access to DAT_32_16_N Data Bus Chip Internal Value Width Resources 1 0 32 bits 16 bits 32 bit only 16 bit only Access to SDRAM Data Bus Bits MSB H_WR_BE Pins Used 8, 16, 32 bit 8, 16 bit H_D[31:0] H_D[15:0] H_D[31] H_D[15] 3:0 1:0 Burst accesses are not supported. The device uses the big-endian byte order, as explained in section 11.1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The write access to the SDRAM is different than the write access to the chip. The SDRAM can be written with byte resolution using the four byte write enables. In contrast, internal chip resources are always written at full CPU data bus width (32 bits in Figure 10-2). The write byte enable signals should always be asserted when writing to internal device registers.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-5. Write Access to the SDRAM, 16-Bit Bus 16 bit data bus DAT_32_16_N[0] H_CS_N[0] H_AD[24:1] H_R_W_N[0] H_READY_N[0] [0] H_D[15:8] SDRAM WRITE ACCESS valid H_D[7:0] data ignored H_WR_BE1_N[0] H_WR_BE0_N[0] In 16-bit bus mode, read accesses to SDRAM are always 16 bits, as in Figure 10-6. Figure 10-6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SPI_MISO is master data input, slave data output. SPI_SEL_N is the slave chip select. The master initiates a data transfer by asserting SPI_SEL_N (low) and generating a sequence of SPI_CLK cycles accompanied by serial data on SPI_MOSI. During read cycles the slave outputs data on SPI_MISO. Each additional slave requires an additional slave chip-select wire.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.3.3 SPI Signals In SPI mode, the following CPU bus pins change their functionality and operate as SPI signals. Inputs o SPI_CLK is shared with H_WR_BE0_N o SPI_MOSI is shared with H_WR_BE1_N o SPI_SEL_N is shared with H_WR_BE2_N. Outputs o SPI_MISO is shared with H_D[0].
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 signals in CPU bus mode (including being active low). At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care). The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending with A1 (LSB).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 signals in CPU bus mode (including being active low). For a read access, all four of these bits should be 1. At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. The next bit on SPI_MOSI and SPI_MISO is reserved (don’t care). The next 24 bits the master transmits on SPI_MOSI are address bits, starting from A24 (MSB) and ending with A1 (LSB).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The first bit on SPI_MOSI and SPI_MISO is reserved (don’t care). The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status command. The value 00b represents a status command. At the same time, the slave transmits the opcode bits of the previous command on SPI_MISO. The master then transmits 4 don’t care bits on SPI_MOSI.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 In addition to producing 38.88 MHz for the adaptive clock recovery machines, CLAD1 also make E1 and T1 master clocks for the LIUs and Framers. CLAD1 can make these E1 and T1 master clocks from the CLK_HIGH signal if available. This is not affected by the state of the GCR1.CLK_HIGHD bit. If a clock is not applied to the CLK_HIGH pin because clock recovery is disabled, CLAD1 must have a 2.048MHz or 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 RESET FUNCTION LOCATION COMMENTS HDLC Receive Reset RHC.RHR This bit resets the Receive HDLC controller. HDLC Transmit Reset THC1.THR This resets the Transmit HDLC controller. Elastic Store Receive Reset RESCR.RESR This bit resets the Receive Elastic Store. Elastic Store Transmit Reset TESCR.TESR This bit resets the Transmit Elastic Store. Bit Oriented Code Receive Reset RBOCC.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-10. TDM-over-Packet Encapsulation Formats Table 10-6. Ethernet Frame Fields Field Preamble Start of Frame Delimiter (SFD) Destination Address and Source Address Type Data and Padding Frame Check Sequence (FCS) Description A sequence of 56 bits (alternating 1 and 0 values) Gives components in the network time to detect the presence of a signal and synchronize to the incoming bit stream.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.1 VLAN Tag As specified in IEEE Standard 802.1q, the twelve-bit VLAN identifiers enable the construction of a maximum of 4,096 distinct VLANs. For cases where this VLAN limit is inadequate VLAN stacking provides a two-level VLAN tag structure, which extends the VLAN ID space to over 16 million VLANs. Each packet may be sent without VLAN tags, with a single VLAN tag or with two VLAN tags (VLAN stacking).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-7. IPv4 Header Fields (UDP) Field IPVER IHL IP TOS Total Length Identification Flags Fragment Offset Time To Live Protocol IP Header Checksum Source IP Address Destination IP Address Description IP version number.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-9. IPv6 Header Fields (UDP) Field IPVER Traffic Class Flow Label Description IP version number, for IPv6 IPVER = 6 An 8-bit field similar to the type of service (ToS) field in IPv4. The 20-bit Flow Label field can be used to tag packets of a specific flow to differentiate the packets at the network layer. Similar to the Total Length field in IPv4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.6 L2TPv3/IPv4 Header L2TPv3 HEADER IP HEADER Figure 10-17. L2TPv3/IPv4 Header Format Table 10-12. IPv4 Header Fields (L2TPv3) Field IPVER IHL IP TOS Total Length Identification Flags Fragment Offset Time To Live Protocol IP Header Checksum Source IP Address Destination IP Address See Table 10-7. Must be set to 0x73 to signify L2TPv3 See Table 10-7. Table 10-13.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.7 L2TPv3/IPv6 Header L2TPv3 HEADER IP HEADER Figure 10-18. L2TPv3/IPv6 Header Format Table 10-14. IPv6 Header Fields (L2TPv3) Field IPVER Traffic Class Flow Label Payload Length Next Header Hop Limit Source Address Destination Address Description See Table 10-9. Must be set to 0x73 to signify LTPv3 See Table 10-9. 10.6.1.8 Control Word Figure 10-19. Control Word Format Table 10-15.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Field M FRG Length Sequence Number Description there is a failure of that direction of the bi-directional connection. This indication can be used to signal congestion or other network related faults. Receiving remote failure indication may trigger fall-back mechanisms for congestion avoidance.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Field Description SSRC Identifies the synchronization source. This identifier should be chosen randomly, with the intent that no two synchronization sources within the same RTP session have the same SSRC identifier. 10.6.1.10 TDM-over-Packet Payload This field can contain the following payload types: AAL1 HDLC RAW (SAToP or CESoPSN formats) OAM (VCCV or UDP/IP-specific).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-22. UDP/IP-Specific OAM Packet Format Table 10-18. UDP/IP-Specific OAM Payload Fields Field L, R, M Length OAM Sequence Number OAM Msg Type OAM Msg Code Description Identical to those of the bundle being tested OAM message packet length (in bytes) Uniquely identifies the message. Its value is unrelated to the sequence number of the TDM data packets for the bundle in question.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-23. TDM Connectivity over a PSN Figure 10-24. TDMoP Packet Format in a Typical Application DA SA VLAN Tag Ethertype IP Header Optional IP Src. IP=X Dst. IP=Y UDP or L2TPv3 Header Bundle ID=A Control Word Payload Type AAL1/ HDLC/SAToP/ CESoPSN/ OAM CRC-32 DA SA VLAN Tag Ethertype IP Header Optional IP Src. IP=Y Dst.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.3 Clock Recovery The TDM-over-Packet block’s innovative clock recovery process is divided into two successive phases. In the acquisition phase, rapid frequency lock is attained. In the tracking phase, frequency lock is sustained and phase is also tracked.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.4 Timeslot Assigner (TSA) The TDM-over-Packet block contains one Timeslot Assigner for each E1/T1 port (framed or multiframed) using a PCM interface. The TSA is bypassed in high-speed mode (i.e. when High_speed=1 in General_cfg_reg0.) The TSA tables are described in section 11.4.5. 2 The TSA assigns 2-, 7- or 8-bit wide timeslots to a specific bundle and a specific receive queue.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.5 CAS Handler 10.6.5.1 CAS Handler, TDM-to-Ethernet Direction In the TDM-to-Ethernet direction, the CAS handler receives the CAS bits (for structured-with-CAS AAL1 or CESoPSN bundles) on the TDMn_RSIG_RTS signal.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces 31 0 ABCD (TS7) ABCD (TS6) ABCD (TS5) ABCD (TS4) ABCD (TS3) ABCD (TS2) ABCD (TS1) ABCD (TS0) ABCD (TS15) .. .. .. .. .. .. ABCD (TS8) ABCD (TS23) .. .. .. .. .. .. ABCD (TS16) ABCD (TS31) .. .. .. .. .. .. ABCD (TS24) Figure 10-28.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0) TDMn_TCLK Once in 3milliseconds TDMn_RX_SYNC TDMn_RSIG A B C D A Timeslot 22 B C D A Timeslot 23 B C D Timeslot 0 Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram TDMn_TCLK Once in 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-32.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-33. E1 MF Interface TSIG Timing Diagram TDMn_TCLK once in 2 milliseconds TDMn_TX_MF_CD TDMn_TSIG A B C D A Timeslot 30 B C Timeslot 31 D Timeslot 0 Figure 10-34. T1 ESF Interface TSIG Timing Diagram TDMn_TCLK Once in 3 milliseconds TDMn_TX_MF_CD TDMn_TSIG A B C D A Timeslot 22 B C D Timeslot 23 A B C D Timeslot 0 Figure 10-35.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-36. AAL1 Mapping, General The structure of the AAL1 header is shown in Table 10-21 below. Table 10-21. AAL1 Header Fields Length Field Description (bits) C SN CRC P 1 3 3 1 E Pointer 1 7 Indicates if there is a pointer in the second octet of the AAL1 SAR PDU. When set, a pointer exists.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SAR PDU payload contains 47 octets (376 bits) of TDM data without regard to frame alignment or timeslot byte alignment. All AAL1 SAR PDUs are non-P format for unstructured bundles. Structured-without-CAS bundles, for E1/T1 interfaces, support rates of N 64 kbps, where N is the number of timeslots configured to be assigned to a bundle.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.7 HDLC Payload Type Machine Handling HDLC in TDM-over-Packet ensures efficient transport of CCS (common channel signaling, such as SS7), embedded in the TDM stream or other HDLC-based traffic, such as Frame Relay, according to IETF RFC 4618 (excluding clause 5.3 – PPP) and RFC 5087 (TDMoIP).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.8 RAW Payload Type Machine The RAW payload type machine support the following bundle types: Unstructured According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553 (SAToP). Structured without CAS According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN). Structured with CAS According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN). 10.6.8.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-40. CESoPSN Structured-Without-CAS Mapping The packetization delay of a CESoPSN structured-without-CAS bundle is: T = N x 125 s (i.e. N x the frame rate) The minimum packetization time of an Ethernet packet for a structured (with or without CAS) bundle is 125 s. 10.6.8.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example) In T1 SF, the multiframe structure is composed of 2 superframes resulting total of 24 TDM frames. The CAS info at the end of the structure contains the CAS info of the 2 corresponding superframes as well. Figure 10-43.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-44.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.9 SDRAM and SDRAM Controller The device requires an external SDRAM for its operation. The following describes how the TDMoP block and the CPU use the SDRAM: The TDMoP block accesses these sections of the SDRAM: Transmit buffers section This area stores outgoing packets created by the payload-type machines. It is a 1-Mbyte area with base address specified by the Tx_buf_base_add field in General_cfg_reg1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-45. SDRAM Access through the SDRAM Controller SDRAM CLOCK SDRAM CONTROLLER ARBITER ACCESS FROM HW BLOCKS RESET_N CPU PORT CONFIGURATION BITS OTHER PORTS CONFIGURATION REGISTER TDMoPacket CPU 10.6.10 Jitter Buffer Control (JBC) 10.6.10.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-47. Timing in TDM-over-Packet The jitter buffer, located in the SDRAM, has two main roles: Compensate for packet delay variation Provide fill level information as the independent variable used by the clock recovery machines to reconstruct the TDM clock on a slave TDMoP device. The data enters the buffer at a variable rate determined by packet arrival times and leaves it at a constant TDM rate.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 For T1 structured-with-CAS, multiply the above formula by 0.75. The jitter buffer depth is defined by the Rx_max_buff_size parameter found in the Bundle Configuration Tables. When the jitter buffer level reaches the value of Rx_max_buff_size, an overrun situation is declared.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 For AAL1/HDLC/RAW structured bundles: the Jitter_buffer_index value is the number of the lowest timeslot in the bundle. For example, if the bundle consists of timeslots 2, 4, 17 on port 3, Jitter_buffer_index=0x2. For unstructured bundles the Jitter_buffer_index value is 0x0. 10.6.10.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-49. TDM-over-Packet Data Flow Diagram 10.6.11.1 Buffer Descriptor Data is transferred between the Ethernet MAC, internal payload-type machines and the external CPU by means of buffers in the SDRAM. Payload data is stored in 2 kB SDRAM buffers along with a buffer descriptor located in the buffer’s first dwords.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.2 Buffer Descriptor First Dword Used for all paths. Located at offset 0x0 from the start of the buffer. Table 10-24.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.3 Buffer Descriptor Second Dword Located at offset 0x4 from the start of the buffer. 10.6.11.3.1 TDM ETH and CPU ETH Packets Table 10-25. Buffer Descriptor Second Dword Fields (TDM ETH and CPU ETH) Bits Data Element Description 31:15 14 Reserved Stamp 13:7 Ts_offset 6:0 Hdr2_length Must be set to zero. Indicates whether the packet should be time-stamped.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.4 Buffer Descriptor Third Dword Used for ETH CPU packets. Located at offset 0x8 from start of the buffer. Table 10-27. Buffer Descriptor Third Dword Fields (ETH CPU) Bits Data Element Description 31:0 Timestamp 32 bits timestamp latched by the packet classifier upon packet reception. Timestamp resolution is 100 s or 1 s as specified by the OAM_timestamp_resolution field in General_cfg_reg0. 10.6.11.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The CPU must define the number of buffers for each bundle by initializing the linked list for the bundle. Software prepares these buffers by writing the Ethernet, IP/MPLS/L2TPv3/MEF headers in advance, so that the payloadtype machines need only to write the packet payload. Since the headers contain bundle-specific data (e.g.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.8 TDM to Ethernet Flow Each payload-type machine receives the data of specific bundle timeslots and maps it into packets. To store a new packet in preparation, the machine extracts a pointer from the free buffer pool (section 10.6.11.7) and fills the associated buffer with TDM timeslot data, one by one.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.9 Ethernet to TDM Flow A packet arriving from the Ethernet port passes through the Ethernet MAC block. The MAC block does not store the packet, but it does calculate the CRC to verify packet data integrity. If the packet is bad, the MAC signals this to the packet classifier on the last word of the packet, and the packet classifier discards it.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.10 TDM to TDM (Cross-Connect) Flow Each payload-type machine receives the data of bundle-specific TDM timeslots and maps the data into Ethernet packets. To store a packet, the payload-type machine needs an SDRAM buffer which it gets by extracting a buffer pointer from the free buffer pool. It then fills the buffer as it processes the TDM timeslots.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.11 TDM to CPU Flow The payload-type machines identify the destination of their packets according to the per-bundle configuration. Upon getting the first byte of a packet in a bundle destined to the CPU, the machine needs a buffer to store the packet. It therefore checks whether a buffer is available in the TDM-to-CPU pool. If the pool is empty, the machine discards the current data.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.12 CPU to TDM Flow The Rx arbiter polls the CPU-to-TDM queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and there are no buffers pending in the Rx FIFO or the cross-connect queue, the Rx arbiter extracts the pointer and copies the relevant data from the SDRAM buffer to the appropriate payload-type machine.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.13 CPU to Ethernet Flow The Tx Ethernet interface polls the CPU-to-Ethernet queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and no buffers from the payload-type machines are waiting in the Ethernet Tx queue, the Tx Ethernet interface extracts the pointer and copies the relevant data from the SDRAM buffer to the Ethernet MAC block.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.14 Ethernet to CPU Flow Ethernet packets enter the chip via the Ethernet MAC block and the packet classifier into the Rx arbiter. When the Rx arbiter identifies that a packet is destined to the CPU, it extracts a pointer from the Ethernet-to-CPU pool (if the pool is empty, the Rx arbiter discards the packet) and stores the packet data into the SDRAM in the buffer indicated by the pointer.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 In half-duplex mode the start of transmission is deferred if MII_CRS (carrier sense) is active. If MII_COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. MII_CRS and MII_COL have no effect in full-duplex mode. Figure 10-58.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.12.2 Pause Packet Support Ethernet transmission pause in response to a received pause packet is enabled when Pause_enable=1 in the MAC_network_configuration register. 2 When a valid pause packet is received, the MAC_pause_time register is updated with the packet’s pause time regardless of its current contents and regardless of the state of Pause_enable bit.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.13 Packet Classifier The Packet Classifier is part of the receive path, immediately following the Ethernet MAC block. It analyzes the header of each incoming packet, by comparing the header fields to the chip’s configured parameters, and then decides whether to discard the packet or add a buffer descriptor and forward the packet to the CPU or one of the payload-type machines. Section 11.4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 assigned to the chip’s internal bundles, is discarded if Discard_Switch_6 is set. Otherwise it is transferred to the CPU. Discard_Switch_7: A packet recognized as OAM packet (see section 10.6.13.3) is discarded if Discard_Switch_7 is set. Otherwise it is transferred to the CPU. Discard_Switch_8: A packet with Ethertype equal to CPU_dest_ether_type configuration is discarded when Discard_Switch_8 is set.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.13.1 TDMoIP Port Number The TDMoIP_port_num1 and TDMoIP_port_num2 configuration fields are used by the block to identify UDP/IP TDMoIP packets. Although the chip has two of these fields, in most cases both fields should have the default value (0x085E) as assigned by IANA for TDM-over-Packet.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.6.13.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-62. Structure of Packets with Trailer The CRC is calculated over all packet bytes including over the trailer bytes. The transmitted bytes counter and the received bytes counter (section 11.4.3.3) do not count the trailer bytes. 10.6.15 Counters and Status Registers For information about counters and registers in the TDMoP block, see section 11.4. 10.6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The destination MAC/IP (and/or VLAN) of the duplicated packets can be different as the chip supports more than one MAC/IP address in the packet classifier. 10.6.17 OAM Signaling TDMoP bundles require a signaling mechanism to provide feedback regarding problems in the communications environment. In addition, such signaling can be used to collect statistics related to the performance of the underlying PSN.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.7 Global Resources See the top-level block diagram in Figure 6-1. Global resources in the device include CLAD1, CLAD2, the CPU Interface block, and the TDM Cross-Connection and External Interfaces block. These resources are configured in the global registers described in section 11.3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-63. Interrupt Pin Logic The TDMoP interrupts indicated in the Intpend register are of two types. The first type consists of interrupts generated by a single source. The second type consists of interrupts that can originate from any of several possible interrupt sources including the ETH_MAC, CW_bits_change, Rx_CAS_change, Tx_CAS_Change, and JB_underrun interrupts.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Interrupt Type CW_bits_change Interrupt Procedure 1. Clear the CW_bits_change bit in the Intpend register by writing 1 to it. 2. Read the CW_bits_change_low_bundles and CW_bits_change_high_bundles registers to determine which bundles(s) have control bits that have changed. 3. Clear the set bits in the CW_bits_change_low_bundles and CW_bits_change_high_bundles registers by writing 1 to them. 4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-64. LIU, Framer and BERT Interrupt Information Flow Diagram Interrupts Allowed No Interrupt Condition Exists? Yes Read GTISR status register. What FRAMER, LIU or BERT set an interrupt condition? LIUn BERTn FRAMERn Read corresponding LLSR register. Read corresponding RIIR & TIIR Framer status register. Read corresponding BLSR register. Read Corresponding Framer status register.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.10 Elastic Stores and Framer System Interface The framer and formatter provide versatile system interfaces with the following capabilities: Elastic stores can be enabled in the Tx path, the Rx path or both to support controlled slips T1 channels can be mapped/demapped to/from a 2.048MHz TDM data stream E1 channels can be mapped/demapped to/from a 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-33. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align REGISTER BIT DELAY RESCR.RESR TESCR.TESR RESCR.RESALGN TESCR.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 For example, if the desired configuration is to transmit channels 2-16 and 18-26 from the 2.048MHz TSER data stream, the TBCS registers should be programmed as follows: TBCS1 = 0x01 :: ignore TSER channel 1 :: TBCS2 = 0x00 TBCS3 = 0x01 :: ignore TSER channel 17 :: TBCS4 = 0xFC :: ignore TSER channels 27-32 :: 10.10.3.2 Mapping T1 Channels Into a 2.048MHz TDM Stream The receive elastic store operates with a 2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 For example, if the desired configuration is to ignore E1 timeslot 0 (channel 1) and timeslot 16 (channel 17), the RBCS registers should be programmed as follows: RBCS1 = 0x01 :: ignore E1 channel 1 :: RBCS2 = 0x00 :: ignore E1 channel 17 :: RBCS3 = 0x01 RBCS4 = 0xFC :: ignore E1 channels 27-32 :: 10.11 Framers The framer cores are software selectable for E1, T1 or J1. (J1 is a variant of T1 used in Japan.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 FRAME NUMBER 8 9 10 11 12 Ft Fs SIGNALING 1 1 1 0 0 B Table 10-35. T1-ESF Framing Pattern and Signaling Bits FRAME FRAMING FDL CRC SIGNALING NUMBER 1 2 CRC1 3 4 0 5 6 CRC2 7 8 0 9 10 CRC3 11 12 13 14 CRC4 15 16 0 17 18 CRC5 19 20 1 21 22 CRC6 23 24 1 Table 10-36.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 FRAME NUMBER 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ft Fs SIGNALING 1 C 1 0 1 1 1 0 C1 (concentrator bit) D 1 C2 (concentrator bit) 0 C3 (concentrator bit) 1 C4 (concentrator bit) A 0 C5 (concentrator bit) 1 C6 (concentrator bit) 0 C7 (concentrator bit) B 1 C8 (concentrator bit)
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.11.1.2 E1 Framing Formats E1 frames contain 32 8-bit channels. The first DS0 of each frame is used to carry overhead bits for frame alignment, alarm indication and node-to-node communication. The other 31 DS0 channels are available to carry voice and data. In many applications the 17th channel of each frame carries voice-channel signaling information and other overhead.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name Description Functions Page TCR2-E1 TCR3 TSLC TAF TNAF RMMR Transmit Control Register 2 (E1 Mode) Transmit Control Register 3 Transmit SLC96 Control Register 1,2,3 Transmit Align Frame Transmit Non-Align Frame Receive Master Mode Register Tx enable for auto-E bit setting Tx or D4 mode, CRC-4 recalc Tx SLC-96 Bits Tx possible source of Si, FAS bits Tx possible source of Si, A, Sa bits Rx E1/T1 mode,
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-40.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.11.3.1.2 Hardware Signaling In the hardware signaling method, signaling data is provided to the transmit formatter using the TSIG input. The signaling information on TSIG is buffered and inserted into the outgoing framed T1 or E1 signal. In both T1 and E1 modes, signaling data can be sourced from TSIG on a per-channel basis by using the THSCS registers.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.11.3.2.4 Receive Signaling Reinsertion at RSER In this mode, the system provides a multiframe sync at the framer’s RSYNC input, and the signaling data is reinserted based on this alignment. In T1 mode, this results in two versions of the signaling data: the original signaling data based on the Fs/ESF frame positions, and the realigned data based on the system-supplied multiframe sync applied at RSYNC.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-43.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 in RIM7-T1. The CPU has 2ms (8 * 2 * 125s) to read the data from RFDL before it is lost. Note that in this mode, no zero stuffing is applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL messaging applications. In the SF framing mode, the framer writes the received Fs framing pattern into the lower six bits of the RFDL register, and RLS7-T1.RFDLF is set every 1.5ms (12 * 125s).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.11.5.3 Sa Bit Monitoring and Reporting In addition to the registers outlined above, the framer provides status and interrupt capability in order to detect changes in the state of selected Sa bits. The RSAIMR register can be used to select which Sa bits are monitored for a change of state. When a change of state is detected in one of the enabled Sa bit positions, the RLS7E1.SaXCD status bit is set.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.11.6.1 Real-Time Status, Latched Status, and Interrupt Mask Bits The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-48. E1 Alarm Criteria ALARM LOS SET CRITERIA CLEAR CRITERIA 255 or 2048 consecutive zeros received (determined by RLS1.RLOSC) LOF At least 32 ones received in 255 bit times ITU SPEC G.775 4.2 See Table 10-49.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 When automatic remote alarm (RAI) generation is enabled (TCR2-E1.ARA=1), if the receive framer detects any of the following conditions then the transmit formatter automatically transmits RAI: Rx loss of signal, Rx loss of frame synchronization, Rx AIS alarm or CRC-4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC-4 is enabled). RAI generation conforms to ETS 300 011 and ITU G.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 In E1 operation, CRC-4 errors are counted and reported in the PCVCR registers.. Since the maximum CRC-4 count in a one second period is 1000, this counter cannot saturate in that length of time. The counter stops counting during loss of frame at either the FAS or CRC-4 level, but it continues to count if only CAS multiframe sync is lost. Table 10-52.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name TDS0M RDS0SEL RDS0M Description Transmit DS0 Monitor Register Rx DS0 Monitor Select Register Rx DS0 Monitor Register Functions Tx channel data Rx channel to be monitored Rx monitored data Page 301 228 237 In the transmit direction TCM[4:0] field in TDS0SEL specifies the channel to be monitored. In the Rx direction, the RCM[4:0] field in RDS0SEL specifies the channel to be monitored.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 specify the 8-bit idle code for each channel and the TCICE registers enable idle code insertion on a per-channel basis. 10.11.13 Digital Milliwatt Code Generation The Rx digital milliwatt registers (RDMWE) specify which of the Rx E1/T1 channels should be overwritten with a digital milliwatt code. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 10-57.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name TLS1 RCR2-T1 RSLC RLS7 Description Transmit Latched Status Register 1 Receive Control Register 2 Receive SLC-96 Data Link Registers 1 to 3 Receive Latched Status Register 7 Functions Page Tx SLC-96 multiframe alignment event Rx SLC-96 enable control bit Rx SLC-96 overhead values Rx SLC-96 multiframe alignment event 296 229 238 258 10.11.16.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name RHPBA RHF RRTS5 RLS5 RIM5 THC1 THBSE THC2 THFC TRTS2 TLS2 TIM2 TFBA THF Description Rx HDLC Packet Bytes Available Register Rx HDLC FIFO Register Rx Real-Time Status Register 5 Rx Latched Status Register 5 Rx Interrupt Mask 5 Transmit HDLC Control 1 Transmit HDLC Bit Suppress Transmit HDLC Control 2 Transmit HDLC FIFO Control Transmit HDLC Status Transmit HDLC Latched Status Transmit Interrupt Mask Reg
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-66. Receive HDLC Servicing Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.RHR) Start New Message Buffer Enable Interrupts RPE and RHWM NO Interrupt? No Action Required Work Another Process. YES Read Register RHPBA Start New Message Buffer NO RHPBA.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.12.2 Transmit HDLC Controller The transmit HDLC controller is enabled when THC2.THCE=1. A low-to-high transition on THC1.THR resets the transmit HDLC controller and flushes the transmit HDLC FIFO. In T1 ESF mode, the transmit HDLC controller can be connected to the FDL (THC1.THMS=1) or to any DS0 channel (THMS=0). In E1 mode, it can be connected to an Sa bit channel (THMS=1) or to any DS0 channel (THMS=0).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-67. Transmit HDLC Servicing Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC1.THR) Enable TLWM Interrupt and Verify TLWM Clear Set THC1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.13 Line Interface Units (LIU) Each TDM port of the device has an on-chip line interface unit (LIU). The LIU contains three sections: the transmitter, which drives pulses with standards-compliant waveshapes onto the outbound cable; the receiver, which recovers clock and data from the inbound cable; and the jitter attenuator.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Note 6: The 1F capacitor in series with TTIPn is only necessary in G.703 2048kHz mode (LTISR.TXG703=1). Note 7: The 560pF on TTIPn/TRINGn must be tuned for your application. Note 8: Resistor RT is not necessary if receiver termination is internal. See LRISMR.RIMPM[2:0]. Table 10-60. Transformer Specifications Specification Turns Ratio, 3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.13.2 LIU Transmitter The LIU is configured for E1 or T1/J1 mode by setting the LTRCR.T1J1E1S bit appropriately. 10.13.2.1 Waveshaping The LIU transmitter uses a sequencer and a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the outbound cable. The waveforms meet the latest ANSI, ETSI, ITU and Telcordia specifications (see Figure 10-69 and Figure 10-70). The LTRCR.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-69. T1/J1 Transmit Pulse Templates 1.2 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.7 NORMALIZED AMPLITUDE MINIMUM CURVE UI Time Amp. MAXIMUM CURVE UI Time Amp. 1.1 0.6 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 0.5 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.13.3 LIU Receiver The LIU is configured for E1 or T1/J1 mode by setting the LTRCR.T1J1E1S bit appropriately. 10.13.3.1 Interfacing to the Line The LIU receiver accepts incoming T1, E1 and J1 physical layer signals on the RTIP/RRING differential pair. The receiver is designed to be fully software-selectable for E1, T1 or J1 without changing any external components.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 incoming signal to recover clock and data. The receiver has excellent jitter tolerance as shown in Figure 10-72 and Figure 10-73. Figure 10-72. Jitter Tolerance, T1 Mode UNIT INTERVALS (UIpp) 1K DS3100 Jitter Tolerance 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 10-73.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.13.3.6 Loss-of-Signal Detection In T1 mode, LOS is declared when no pulses are detected (i.e., when the signal level is 3dB below the Rx sensitivity level set by LRISMR.RSMS[1:0]) in a window of 192 consecutive pulse intervals. When LOS occurs, the receiver sets the real-time LOS status bit in LRSR and the latched LOS status bit in LLSR. LLSR.LOS in turn can cause and interrupt request if enabled by LSIMR.LOS.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 It is acceptable to provide a gapped/bursty clock at the TCLKFn pin if the jitter attenuator is placed in the transmit side. If the incoming jitter exceeds 120UIP-P (when buffer depth is 128 bits) or 28UIP-P (when buffer depth is 32 bits), then the device sets the jitter attenuator limit trip (LLSR.JALTS). Figure 10-74. Jitter Attenuation ITU G.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.13.5.2 Local Loopback In local loopback the AMI-, HDB3- or B8ZS-encoded transmit signal from the transmit formatter is looped back toward the Rx framer. The data is transmitted normally on TTIP/TRING if the line driver is enabled, but the recovered clock and data from the LIU receiver is ignored. This loopback is shown in Figure 10-76. Figure 10-76.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-78.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.14 Bit Error Rate Test Functions (BERTs) 10.14.1 BERT General Description The BERT (Bit Error Rate Tester) is a software-programmable test-pattern generator and monitor capable of meeting most error performance monitoring requirements for digital transmission equipment. It is used to test and stress communication links. Each E1/T1 transceiver has its own dedicated BERT circuitry.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The BERT function must be enabled and configured for each port (see the TXPC and RXPC registers). The BERT can be assigned to any combination of 64kbps channels within the E1/T1 signal using the bits in the TBPCS and RBPCS registers. Individual bit positions within the channels can be suppressed (i.e. not used for patterns) using the bits in the TBPBS and RBPBS registers.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 programmable (1 to 32, y < n) in the BPCR register. The output of the Rx pattern generator is the feedback. If QRSS is enabled (BPCR.QRSS=1) is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through 31 are all zeros.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-80. Repetitive Pattern Synchronization State Diagram Sync 32 bits without errors 6 of 64 bits with errors 1 bit error Verify Match Pattern Matches 10.14.4.3 Rx Pattern Monitoring Rx pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out Of Synchronization (BSR.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 10.14.5.1 Transmit Error Insertion Errors can be inserted into the generated pattern one at a time or at a rate of one out of every 10n bits. The value of n is programmable (1 to 7 or off) in the TEICR.TEIR[2:0] configuration field.. Single bit error insertion is enabled by setting TEICR.BEI and can be initiated by a zero-to-one transition of TEICR.TSEI. 10.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11 Device Registers 11.1 Addressing Device registers and memory can be accessed either 2 or 4 bytes at a time, as specified by configuration pin DAT_32_16_N. In the 16-bit addressing mode, addresses are multiples of 2, while in 32-bit addressing, addresses are multiples of 4. The prefix “0x” indicates hexadecimal (base 16) numbering, as does the suffix “h” (Example: 2FFh).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 11-4. Partial Data Elements (16 to 32 bits long) SPI interface mode (H_CPU_SPI_N=0) always uses 32-bit addressing. See section 10.3. 11.2 Top-Level Memory Map Table 11-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.3 Global Registers Functions contained in the global registers include device ID, CLAD configuration, TDMoP to framer connections, block resets, and block interrupt status. The global register base address is 0x108,000. Table 11-2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 GCR1 (Global Control Register) 0x00 Bits Data Element Name R/W Default Description [10] MODE R/W 0 [9] CLKMODE R/W 0 [8] CLK_HIGHD R/W 0 [7] MCLKS R/W 0 [6] MCLKE R/W 0 [5] GFCLE R/W 0 [4] LOSS R/W 0 [3] RFMSS R/W 0 [2] IPOR R/W 0 [1] IPI1 R/W 0 Mode Select Specifies internal mode or external mode connections for the cross-connect side of the framers and the TDMoP block.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 GCR1 (Global Control Register) 0x00 Bits Data Element Name R/W [0] IPI0 R/W Default 0 Description 1 = H_INT[1] forced inactive (high) See Figure 10-63. Interrupt Pin Inhibit 0 0 = H_INT[0] normal interrupt output behavior 1 = H_INT[0] forced inactive (high) See Figure 10-63.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 GTRR (Global Transceiver Reset Register) 0x08 Bits Data Element Name R/W Default [15:8] LIRSTn R/W 0 [7:0] LSRSTn R/W 0 Description LIU Line Interface Reset n Bit 15 is LIRST8; bit 8 is LIRST1. A zero-to-one transition resets the receiver’s clock recovery state machine and re-centers the jitter attenuator (JA) FIFO pointers for the corresponding LIU. This is an asynchronous reset. See section 10.5.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 GTIMR (Global Transceiver Interrupt Mask Register) 0x14 Bits Data Element Name R/W Default [31:25] [24] Not used. TDMoPIM R/W 0 [23:16] LIMn R/W 0 [15:8] BIMn R/W 0 [7:0] FIMn R/W 0 0 Description Must be set to zero. TDM-over-Packet Interrupt Mask This bit is the interrupt mask for GTISR.TDMoPIS. 0 = Interrupt masked. 1 = Interrupt enabled. LIU Interrupt Mask n Bit 23 is LIM8; bit 16 is LIM1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM1 (Framer and TDM-over-Packet Internal Signal Manager 1) 0x18 Bits Data Element Name R/W Default [4:0] CLKCNTL1 R/W 0x0 Description Clock Control, Port 1 In external mode (GCR1.MODE=1) this field is ignored. In internal mode (MODE=0), this field specifies the port 1 clock signal, ref_clk[1]. See the ref_clk[n] signal in Figure 6-2. See also Figure 8-2 and Figure 8-3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM3 (Framer and TDM-over-Packet Internal Signal Manager 3) 0x20 Bits Data Element Name R/W Default [31] TDMRCLKS8 R/W 0x0 [30:28] TDMI8 R/W 0x7 [27] TDMRCLKS7 R/W 0x0 [26:24] TDMI7 R/W 0x6 [23] TDMRCLKS6 R/W 0x0 [22:20] TDMI6 R/W 0x5 [19] TDMRCLKS5 R/W 0x0 [18:16] TDMI5 R/W 0x4 [15] TDMRCLKS4 R/W 0x0 [14:12] TDMI4 R/W 0x3 [11] TDMRCLKS3 R/W 0x0 [10:8] TDMI3 R/W
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM4 (Framer and TDM-over-Packet Internal Signal Manager 4) 0x24 Bits Data Element Name R/W Default [31] [30:28] Reserved FRMR8 R/W 0x0 0x7 [27] [27:24] Reserved FRMR7 R/W 0x0 0x6 [23] [22:20] Reserved FRMR6 R/W 0x0 0x5 [19] [18:16] Reserved FRMR5 R/W 0x0 0x4 [15] [14:12] Reserved FRMR4 R/W 0x0 0x3 [11] [10:8] Reserved FRMR3 R/W 0x0 0x2 [7] [6:4] Reserved FRMR2 R/W 0x0 0x1 [3] [2
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4 TDM-over-Packet Registers The base address for the TDMoP registers is 0x0. Table 11-3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.1 Configuration and Status Registers The base address for the TDMoP configuration and status registers is 0x0,000. Table 11-4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 110 114 118 11C 120 124 128 12C 130 134 138 13C 140 144 Register Name Port2_status_reg1 Port2_status_reg2 Port3_status_reg1 Port3_status_reg2 Port4_status_reg1 Port4_status_reg2 Port5_status_reg1 Port6_status_reg2 Port6_status_reg1 Port6_status_reg2 Port7_status_reg1 Port7_status_reg2 Port8_status_reg1 Port8_status_reg2 Description Page Port 2 status bit register 1 Port 2 status bit register 2 Port 3
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 General_cfg_reg0 0x00 Bits Data Element Name R/W Reset Value [6:5] Fq R/W 0x0 [4:3] Col_width R/W 0x0 [2:1] CAS_latency R/W 0x2 [0] Rst_SDRAM_n R/W 0x0 R/W Reset Value Description SDRAM clock: 00 = 50 MHz 01 = 75 MHz 10 = Reserved 11 = Reserved for 100 MHz SDRAM columns and rows 00 = 8 bit (256 columns) 01 = 9 bit (512 columns) 10 = 10 bit (1K columns) 11 = 11 bit (2K columns) SDRAM CAS latency:
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 General_cfg_reg2 0x08 Bits Data Element Name R/W Reset Value [31:29] Rx_HDLC_min_flags R/W 0x0 [28:24] Reserved R/W 0x0 [23:20] Rx_SAToP/CESoPSN_discard_ mask R/W 0x0 [19:0] Reserved R/W 0x0 Description Minimum number flags between 2 adjacent HDLC frames transmitted towards the cross-connect block. The number of flags is equal to Rx_hdlc_min_flags + 1. Range: 1 – 8.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Port[n]_cfg_reg 0x08+n*4 Bits Data Element Name R/W Reset Value [22:21] Tx_defect_modifier R/W 0x0 [20] Port_Rx_enable (Rx means from Ethernet MII) R/W 0x0 Description Used in the control word M field for packets in all bundles associated with TDMoP port n.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Port[n]_cfg_reg 0x08+n*4 Bits Data Element Name R/W Reset Value Description In two-clock mode (Two-clocks=1) this field specifies the TDMn_TCLK edge on which TDMn_TX_SYNC, TDMn_TX_MF_CD are sampled and the edge on which TDMn_TX and TDMn_TSIG_CTS are updated. The Rx_sample field (above) specifies the TDMn_RCLK edge for the Rx-side signals.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Rst_reg 0x2C Bits Data Element Name R/W Reset Value - 0x0 [31:28] Reserved [27:24] Rst_tx_port_num R/W 0x0 [23:18] Rst_tx_internal_bundle_num R/W 0x00 [17] Rst_tx_open/close R/W 0x0 [16] Rst_tx R/W 0x0 [15:7] [6:1] Reserved Rst_rx_internal_bundle_num R/W R/W 0x0 0x00 [0] Rst_rx R/ set 0x0 Description Must be set to zero Port number associated with Rst_tx field (below).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The TDM_cond_data_reg register below holds four octets to be transmitted as conditioning data in the TDM direction (i.e. toward the cross-connection block) during jitter buffer underrun. This data applies to all bundle types.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg2 0x40 Bits Data Element Name R/W Reset Value Description Packet_classifier_cfg_reg6. Relevant only for packets received from Ethernet port.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg3 0x44 Bits Data Element Name R/W Reset Value [16] Discard_switch_0 R/W 0x0 [15:0] MAC_add1 R/W 0x0000 R/W Reset Value Description ARP packets whose IP destination address does not match chip’s addresses. See section 10.6.13. 0 = Forward to CPU 1 = Discard This field holds bits 47:32 of the first of two MAC addresses for the device.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg7 0x54 Bits [15:0] Data Element Name vlan_2nd_tag_identifier R/W Reset Value R/W 0x8100 R/W Reset Value Description section 10.6.13.5. Second VLAN tag protocol identifier (the first is 0x8100). See section 10.6.13.4. Packet_classifier_cfg_reg8 0x58 Bits Data Element Name Description This field holds the third of three IPv4 addresses for the device.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg13 0x6C Bits [31:0] Data Element Name Ipv6_add1[31:0] Reset Value Description R/W 0x0 This field holds bits 31:0 of the first of two IPv6 addresses for the device. The other address is held in registers starting with Packet_classifier_cfg_reg14. Relevant only for packets received from the Ethernet port.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg18 0x80 Bits [15:0] Data Element Name VCCV_oam_value R/W Reset Value R/W 0x0000 R/W Reset Value R/W 0x00 - 0x0000 R/W 0x000 Description in the VCCV_oam_value field below. See section 10.6.13.3. Indicates the value of the 16 most significant bits of the control word for identifying VCCV OAM packets.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.1.2 TDMoP Status Registers The General_stat_reg register has latched status registers that indicate hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The Port[n]_stat_reg1 register has real-time (not latched) status fields. The index n indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[63:32] 0x100+n*4 Bits Data Element Name R/W Reset Value [31:22] Rx_max_buff_size R/W None [21:20] Payload_type_machine R/W None [19] Tx_RTP (Tx is toward Ethernet MAC) R/W None [18] Control_Word_exists R/W None [17:16] Tx_dest R/W None [15:9] Rx_max_lost_packets R/W None [8:4] Number_of_ts R/W None [3] Rx_ discard_sanity_fail R/W None [2:1] Header_type R/W Non
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[95:64] 0x200+n*4 Bits Data Element Name R/W Reset Value [10:6] Reserved R/W None [5:4] Tx_cond_octet_type R/W None [3:2] Rx_AAL1_bundle_type R/W None [1:0] Protection_mode R/W None Description 00 = Unstructured 01 = Structured 10 = Structured with CAS 11 = Reserved Must be set to zero Selects the ETH_cond_octet from ETH_cond_data_reg to be transmitted towards packet network: 00
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[127:96] 0x300+n*4 Bits Data Element Name R/W Reset Value [7:4] Port_num R/W None [3:2] Tx_VLAN_stack R/W None [1] Rx_bundle_identifier_valid R/W None [0] Reserved R/W None Description 00 = No cookies in the TX L2TPv3 header 01 = One cookie in the TX L2TPv3 header 10 = Two cookies in the TX L2TPv3 header 11 = Reserved The port number which the bundle is assigned to: 0000 = Port 1
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bits Data Element Name R/W Reset Value [31:22] Reserved R/W None [21:20] Payload_type_machine R/W None [19] Tx_RTP R/W None [18] Control_Word_exists R/W None [17:16] Tx_dest R/W None [15:11] Reserved R/W None [10:9] Packet_SN_mode R/W None [8:3] Reserved R/W None [2:1] Header_type R/W None [0] Tx_R_bit R/W None Description Must be set to zero 00 = HDLC 01 = AAL1 10 = Reserv
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 HDLC_Bundle[n]_cfg[127:96] 0x300+n*4 Bits Data Element Name R/W Reset Value [7:4] Port_num R/W None [3:2] Tx_VLAN_stack R/W None [1] Rx_Bundle_Identifier_valid R/W None [0] Reserved R/W None Description 00 = No cookies in the TX L2TPv3 header 01 = One cookie in the TX L2TPv3 header 10 = Two cookies in the TX L2TPv3 header 11 = Reserved The port number which the bundle is assigned to: 0000 = Port 1
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.2.3 SAToP/CESoPSN Bundle Configuration In the register descriptions below, the index n indicates bundle number: 0 to 63.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[95:64] 0x200+n*4 Reset Bits Data Element Name R/W Value [30] Tx_cond_data R/W None [29] Tx_dest_framing R/W None [28] Tx_CAS_source R/W None [27] Reserved R/W None [26:16] TDM_frames_in_packet or TDM_bytes_in_packet R/W None [15:13] Reserved R/W None [12:11] Tx_SATOP_bundle_type R/W None [10:6] Reserved R/W None [5:4] Tx_cond_octet_type R/W None [3:2] R
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300+n*4 Reset Bits Data Element Name R/W Value [15] Rx_CAS_src R/W None [14] Rx_enable_reorder R/W None [13] Reserved R/W None [12] OAM_ID_in_CW R/W None [11] Rx_discard R/W None [10] Rx_dest R/W None [9:8] Tx_MPLS_lables_l2tpv3_cookies R/W None [7:4] Port_num R/W None [3:2] Tx_VLAN_stack [1] Rx_Bundle_Identifier_valid R/W None [0] Reserved
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[159:128] 0x400+n*4 Reset Bits Data Element Name R/W Value [19:16] [15:0] Reserved Tx_IP_checksum R/W R/W None None Description 01 = One cookie in the received L2TPv3 header 10 = Two cookies in the received L2TPv3 header 11 = Reserved Must be set to zero IP header checksum for IP total length equal to zero 183 of 366
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.3 Counters Each counter can be read from two different addresses. Reading from the first address—0x10,000 + offset—does not affect the counter value. Reading from the second address—0x11,000 + offset—causes the counter to be cleared after it is read. Table 11-6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Ethernet Rx AAL1 Lost Cells / Rx SAToP/CESoPSN Discarded Packets Counter 0x400+n*4 Reset Bits Data Element Name R/W Description Value [31:16] [15:0] Reserved Lost_AAL1_Rxd_cells / Discarded_SAToP/CESoPSN_R xd_packets R None None Must be set to zero AAL1 – Number of lost AAL1 SAR PDUs SAToP/CESoPSN – Number of received packets that were discarded by SAToP/CESoPSN hardware machine.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Jitter Buffer Underrun/Overrun Events Counter 0x800+n*4 Reset Bits Data Element Name R/W Value Description AAL1/SAToP/CESoPSN bundles – count of underrun events. AAL1 counter does not include underruns caused by pointer mismatches. HDLC bundles – count of overrun events. Counter sticks at its maximum value and does not roll over to 0. 11.4.3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.4 Status Tables The TDMoP status tables hold indications of hardware events. Except where noted, these are latched status bits. For each bit, the value 1 indicates that the event occurred. A bit set to 1 maintains its value unless the host CPU changes it. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value. The base address for the TDMoP status tables is 0x12,000. 11.4.4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Tx Payload Type Machine Status 0x200+n*4 Bits [1] [0] Data Element Name R/W Reset Value Tx_HDLC_align_err Tx_AAL1_framing_mismatch / Tx_HDLC_CRC_err / Tx_SAToP/CESoPSN_framing_ mismatch R/W R/W None None R/W Reset Value R/W None None R/W Reset Value Description HDLC – received frame from TDM with alignment error AAL1 – Start of TDM frame or start of TDM multiframe mismatch HDLC – received frame from TDM
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.5 Timeslot Assignment Tables Each port has two banks of timeslot assignment (TSA) tables, bank 1 and bank 2. While one bank is actively used by the TDMoP block, the other bank can be written by the CPU. The active bank for the port is specified by the TSA_act_blk field in the Port[n]_cfg_reg register. The base address for the TDMoP status tables is 0x18,000.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bank1 Timeslot Assignment Registers Bank2 Timeslot Assignment Registers Bits [31:21] [20] [19] Data Element Name Reserved Remote_loop Local_loop Ports 1 to 4: 0x000+(port-1)*0x80+ts*4 Ports 5 to 8: 0x400+(port-5)*0x80+ts*4 Ports 1 to 4: 0x200+(port-1)*0x80+ts*4 Ports 5 to 8: 0x600+(port-5)*0x80+ts*4 Reset R/W Description Value R/W R/W None None None [18] Structured_type R/W [17:16] Timeslot_width R/W No
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.6 CPU Queues The pools and queue referred to in this section are shown in the block diagram in Figure 10-49. Whenever a queue or pool level exceeds the associated threshold register, a latched status bit is set in the CPU_Queues_change register which generates an interrupt unless masked by the associated mask bit in the CPU_Queues_mask register.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 TDM_to_CPU_pool_level 0x04 (0x06) Bits [31:8] [7:0] Data Element Name R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 None R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 0x0 R/W Reset Value WO 0x0 None Reserved Level Description Must be set to zero Number of buffers currently stored in the pool.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 CPU_to_ETH_q_level 0x1C (0x1E) Bits [31:6] [5:0] Data Element Name Reserved Level R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 0x0 R/W Reset Value WO 0x0 None R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 0x0 Description Must be set to zero Number of buffers currently stored in the queue. Range: 0 to 32.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 CPU_to_TDM_q_thresh 0x5C (0x5E) Bits Data Element Name R/W Reset Value Description an interrupt is generated. Range: 0 to 32. 11.4.6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Rx_return_q_level 0x70 (0x72) Bits [31:6] [5:0] Data Element Name R/W Reset Value RO 0x0 0x0 R/W Reset Value RO 0x0 0x0 Reserved Level Description Must be set to zero Number of buffers currently stored in the queue. Range: 0 to 32.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.8 Jitter Buffer Control The base address for the TDMoP jitter buffer control is 0x30,000. In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31. The index n indicates the bundle number: 0 to 63. See section 10.6.10 for more information. Table 11-8.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.8.1.2 Structured AAL1/CESoPSN Status_and_level (port-1)*0x100+ts*8 Bits Data Element Name R/W Reset Value Description [31:26] [25:16] Reserved Current_level RO RO 0x0 None [15:2] [1:0] Reserved Status RO RO 0x0 None Always zero The current jitter buffer level for the bundle. The resolution is 0.5ms.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Min_and_max_level (port-1)*0x100+ts*8+4 Bits Data Element Name [15:10] [9:0] Reserved Maximal_level R/W RO RO Reset Value 0x00 None Description underrun is reached, the value of this field remains zero until it is read by the CPU. The resolution is 0.5 ms.. These bits are always zero The maximal level that the jitter buffer has reached since the last time this register was read.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bundle_ts[n] 0xF00+n*4 Bits Data Element Name R/W Reset Value Description 1 = Timeslot is assigned to the bundle 0 = Timeslot is not assigned to the bundle Note: When the interface type is Nx64k this field should be set to all 1s.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.9 Transmit Software CAS The base address for the TDMoP transmit software CAS register space is 0x38,000. For the CAS information transmitted in packets in the TDM-to-Ethernet direction, the CAS signaling information stored in these registers can be used instead of CAS bits coming into the TDMoP block on the TDMn_RSIG_RTS signals.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Tx_SW_CAS_TS7_TS0 0x000+(port-1)*0x10 Bits [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Data Element Name TS7_CAS_nibble TS6_CAS_nibble TS5_CAS_nibble TS4_CAS_nibble TS3_CAS_nibble TS2_CAS_nibble TS1_CAS_nibble TS0_CAS_nibble R/W Reset Value R/W R/W R/W R/W R/W R/W R/W R/W None None None None None None None None Description CAS signaling (ABCD) for timeslot 7 CAS signaling (ABCD) for timeslot 6 CA
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.10 Receive Line CAS The base address for the TDMoP Rx line CAS register space is 0x40,000. These read-only registers allow the CPU to examine the state of the CAS signaling recovered from received packets and transmitted out of the TDMoP block on the TDMn_TSIG signals (i.e. toward the signal cross-connection block and the framers). See section 10.6.5.2 for more details.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.11 Clock Recovery The base address for the TDMoP clock recovery register space is 0x48,000. Most of the registers in this section of the TDMoP block are not documented. The HAL (Hardware Abstraction Layer) software manages these registers. In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. Table 11-12.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.12 Receive SW Conditioning Octet Select The base address for the TDMoP Rx software conditioning octet select register space is 0x50,000. These registers specify which of four conditioning bytes (TDM_cond_octet_a through TDM_cond_octet_d in TDM_cond_data_reg) the TDMoP block transmits on the TDMn_TX signals during an unassigned timeslot.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.13 Receive SW CAS The base address for the TDMoP Rx software CAS register space is 0x58,000. These registers specify the CAS signaling bits the TDMoP block transmits on the TDMn_TSIG signals during unassigned timeslots and during timeslots where CAS is not assigned. See section 10.6.5.2 for more details.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.14 Interrupt Controller The base address for the interrupt controller register space is 0x68,000. The Intpend register and the “change” registers listed below have latched status bits that indicate various TDMoP hardware events. For each bit, the value 1 indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 0x0E4 0x0EC 0x0F4 0x0FC 0x100 0x104 0x140 0x144 0x148 0x14C 0x180 0x1C0 0x1C4 Register Name Tx_CAS_change_mask_P5 Tx_CAS_change_mask_P6 Tx_CAS_change_mask_P7 Tx_CAS_change_mask_P8 RTS_change RTS_mask CW_bits_change_low_bundles CW_bits_mask_low_bundles CW_bits_change_high_bundles CW_bits_mask_high_bundles CW_bits_change_mask CPU_Queues_change CPU_Queues_mask 3 3 3 3 3 3 3 Description Page Tx CAS
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Intpend 0x000 Bits Data Element Name R/W Reset Value [15] JBC_underrun_P8 R/W 0x0 [14] JBC_underrun_P7 R/W 0x0 [13] JBC_underrun_P6 R/W 0x0 [12] JBC_underrun_P5 R/W 0x0 [11] JBC_underrun_P4 R/W 0x0 [10] JBC_underrun_P3 R/W 0x0 [9] JBC_underrun_P2 R/W 0x0 [8] JBC_underrun_P1 R/W 0x0 [7] Rx_CAS_change_P8 R/W 0x0 [6] Rx_CAS_change_P7 R/W 0x0 [5] Rx_CAS_change_P6 R/W 0x0 [4
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Intmask 0x004 Bits [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Data Element Name CW_Bits_change RTS_changes Tx_CAS_change_P8 Tx_CAS_change_P7 Tx_CAS_change_P6 Tx_CAS_change_P5 Tx_CAS_change_P4 Tx_CAS_change_P3 Tx_CAS_change_P2 Tx_CAS_change_P1 JBC_underrun_P8 JBC_underrun_P7 JBC_underrun_P6 JBC_underrun_P5 JBC_underrun_P4 JBC_underrun_P3 JBC
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Tx_CAS_change 0xC0+(port-1)*8 Bits [31:0] Data Element Name Tx_CAS_change R/W R/W Reset Value 0x0000 0000 Description Bit 31 represents timeslot 31 and bit 0 represents timeslot 0 for the port. When a bit is set it indicates a change in transmit (toward the Ethernet port) CAS bits in the corresponding timeslot. The current CAS bits can be read from the Tx formatter signaling registers (TS1 to TS16).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 CW_bits_mask_low_bundles 0x144 Bits Data Element Name R/W Reset Value Description CW_bits_change_low_bundles register. CW_bits_change_high_bundles 0x148 Bits [31:0] Data Element Name CW_bits_change R/W R/W Reset Value 0xFFFF FFFF Description Bit 31 represents bundle 63 and bit 0 represents bundle 32.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 CPU_Queues_mask 0x1C4 Bits [31:10] [9] [8] [7] [6] [5] [4:3] [2] [1] [0] Data Element Name Reserved TDM_to_CPU_pool_thresh TDM_to_CPU_q_thresh CPU_to_ETH_q_thresh ETH_to_CPU_pool_thresh ETH_to_CPU_q_thresh Reserved CPU_to_TDM_q_thresh Tx_return_q_thresh Rx_return_q_thresh R/W Reset Value R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description Must be set to zero Mask TDM_to_CPU_p
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.4.16 Ethernet MAC The base address for the Ethernet MAC register space is 0x72,000. Configuration and status registers are listed in subsection 11.4.16.1. Counters are listed in subsection 11.4.16.2. 11.4.16.1 Ethernet MAC Configuration and Status Registers Table 11-17.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 MAC_network_control 0x000 Bits Data Element Name R/W Reset Value [3] Transmit_enable R/W 0x0 [2] Rx_enable R/W 0x0 [1:0] Reserved - 0x0 R/W Reset Value Description 0 = Stop transmission immediately, clear the transmit FIFO and control registers, and reset the transmit queue pointer register to point to the start of the transmit descriptor list. 1 = Enable the MAC transmitter to send data.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 MAC_network_status 0x008 Bits [31:3] [2] [1:0] Data Element Name Reserved PHY_access_has_completed Reserved R/W Reset Value RO - 0x0 0x1 0x0 R/W Reset Value Description Must be set to zero 1 = PHY management logic is idle.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 MAC_interrupt_enable 0x028 Bits [5] [4] [3:1] [0] Data Element Name R/W Reset Value Retry_limit_exceeded Ethernet_transmit_underrun Reserved Management_packet_sent WO WO WO 0x0 0x0 0x0 0x0 Data Element Name R/W Reset Value Reserved Pause_time_zero Pause_packet_ Rxd Reserved Retry_limit_exceeded Ethernet_transmit_underrun Reserved Management_packet_sent WO WO WO WO WO 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 The MAC_PHY_maintenance register below enables the MAC to communicate with a PHY by means of the MDIO interface. It is used during auto negotiation to ensure that the MAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 MAC_transmit_paulse_quantum 0x0BC Bits [31:16] [15:0] Data Element Name Reserved Pause_time R/W Reset Value R/W 0x0000 0xFFFF R/W Reset Value Description Must be set to zero Transmit pause quantum. Used in hardware generation of transmitted pause packets as value for pause quantum.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Pause_packets_Rxd_OK 0x03C Bits [31:16] [15:0] Data Element Name Reserved Pause_packets_Rxd_OK R/W Reset Value R/W 0x0 0x0 Description Must be set to zero A 16-bit register counting the number of good pause packets received. A good packet has a length of 64 to 1518 (2000 if Rx_2000_byte_packets is set in the MAC_network_configuration register) and has no FCS, alignment or Rx symbol errors.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Alignment_errors 0x054 Bits [31:8] [7:0] Data Element Name Reserved Alignment_errors R/W Reset Value R/W 0x0 0x0 Description Must be set to zero An 8-bit register counting packets that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (2000 if Rx_2000_byte_packets is set in the MAC_network_configura
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Carrier_sense_errors 0x068 Bits [31:8] [7:0] Data Element Name Reserved Carrier_sense_errors R/W Reset Value R/W 0x0 0x0 R/W Reset Value R/W 0x0 0x0 R/W Reset Value R/W 0x0 0x0 Description Must be set to zero An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet wit
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 SQE_test_errors 0x084 Bits [31:8] [7:0] R/W Reset Value R/W 0x0 0x0 Data Element Name R/W Reset Value Reserved Transmitted_pause_packets R/W 0x0 0x0 Data Element Name Reserved SQE_test_errors Description Must be set to zero An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interpacket gap) of MII_TX_EN being deasserted in half duplex mode.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.5 Framer, LIU and BERT Registers Table 11-19. Framer, LIU, BERT Memory Map Port Rx Framer (p. 224) Tx Formatter (p. 272) LIU (p. 303) BERT (p.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 0BC 0C0 0C4 0C8 0CC 0D0 0D4 0D8 0DC 0E0 0E4 0E8 0EC 0F0 0F4 0F8 0FC 100 104 108 10C 110 114 118 11C 120 124 128 12C 130 134 138 13C 140 144 148 14C 150 154 158 15C 160 164 168 16C 180 184 188 18C 190 Register Name RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 RSAOI1 RIDR25 RSAOI2 RIDR26 RSAOI3 RIDR27 RIDR28 RDMWE1-T1 RIDR29 RDMWE2-T1 RIDR30 RDMWE3-T1 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 194 198 19C 1A0 1A4 1A8 1AC 1B0 1B4 1B8 1BC 200 204 208 20C 210 214 218 21C 224 228 22C 240 244 248 24C 250 258 260 264 268 26C 270 274 27C 280 284 288 28C 290 298 2A0 2A4 2A8 2AC 2B0 2B4 2B8 2BC Register Name RSLC2 RNAF RSLC3 RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 SABITS Sa6CODE RMMR RCR1-T1 RCR1-E1 RIBCC RCR2-E1 RCR3 RIOCR RESCR ERCNT RHFC RSCC RXPC RBPBS RLS1 RLS2-T1 RLS2-E1 RLS3-T1 RLS3-E1 RLS4 RL
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 2C0 2C8 2D0 2D4 2D8 300 304 308 30C 320 324 328 32C 340 344 348 34C 350 354 358 35C Register Name RRTS1 RRTS3-T1 RRTS3-E1 RRTS5 RHPBA RHF RBCS1 RBCS2 RBCS3 RBCS4 RSI1 RSI2 RSI3 RSI4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 Register Name: Register Description: Register Address: Read/Write or Read Only Description Rx Real-Time Status Register 1 Rx Real-Time Status Register 3 (T1 Mode) Rx
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 6: Receive HDLC Reset (RHR). Resets the receive HDLC controller and flushes the receive HDLC FIFO. Note that this bit is an acknowledged reset. The CPU sets this bit and the device clears it after the reset operation is complete. The device completes the HDLC reset within 2 frames. See section 10.12.1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name T1 Name E1 Default RSIGC Receive Signaling Control Register base address + 0x04C 7 0 6 0 5 0 4 RFSA1 CASMS 0 3 0 2 RSFF 0 1 RSFE 0 0 RSIE 0 Bit 4 (T1 Mode): Rx Force Signaling All Ones (RFSA1). See Section 10.11.3.2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 1: Rx RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE causes the RAI status from the framer to be integrated for 200ms. 0 = RAI detects when 16 consecutive patterns of 0x00FF appear in the FDL.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default RBOCC Receive BOC Control Register (T1 Mode Only) base address + 0x054 7 RBR 0 6 0 5 RBD1 0 4 RBD0 0 3 RIE 0 2 RBF1 0 1 RBF0 0 0 0 Bit 7: Rx BOC Reset (RBR). Setting this bit to 1 forces a reset of the BOC circuitry.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name : Register Description: Register Address: RSAOI1, RSAOI2, RSAOI3 Receive Signaling All-Ones Insertion Registers (T1 Mode Only) base address + 0x0E0, 0x0E4, 0x0E8 Bit # 7 6 5 4 3 2 RSAOI1 CH8 CH7 CH6 CH5 CH4 CH3 RSAOI2 CH16 CH15 CH14 CH13 CH12 CH11 RSAOI3 CH24 CH23 CH22 CH21 CH20 CH19 Note: These registers have alternate definitions for E1 mode. See E1RIDR25-27.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RS1 to RS16 Receive Signaling Registers base address + 0x100 + 0x04*(n-1), n = 1 to 16 T1 Mode : Bit # 7 RS1 CH1-A RS2 CH2-A RS3 CH3-A RS4 CH4-A RS5 CH5-A RS6 CH6-A RS7 CH7-A RS8 CH8-A RS9 CH9-A RS10 CH10-A RS11 CH11-A RS12 CH12-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line Code Violation Count Register 1 base address + 0x140 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 7 to 0: Line Code Violation Counter Bits 15 to 8 (LCVC15 to LCVC8). LCV15 is the MSB of the 16-bit line code violation count. See section 10.11.8.1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 FOSCR1 Frames Out-of-Sync Count Register 1 base address + 0x150 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS15 to FOS8). FOS15 is the MSB of the 16-bit frames out-of-sync count. See section 10.11.8.3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 FEACR15 0 FEACR1 Error Count A Register 1 base address + 0x160 6 FEACR14 0 5 FEACR13 0 4 FEACR12 0 3 FEACR11 0 2 FEACR10 0 1 FEACR9 0 0 FEACR8 0 Bits 7 to 0: Error Count A Register bits 15 to 8 (FEACR[15:8]). FEACR15 is the MSB of the 16-bit Far End A Counter.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive DS0 Monitor Register base address + 0x180 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 7 to 0: Rx DS0 Channel Bits (B1 to B8). Rx data for the channel specified by the Rx DS0 Monitor Select Register, RDS0SEL. B8 is the LSb of the DS0 channel (last bit to be received). See section 10.11.9.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 2: CRC-4 MF Sync Active (CRC4SA). This real-time status bit is set while the synchronizer is searching for the CRC-4 MF alignment word. Bit 1: CAS MF Sync Active (CASSA). This real-time status bit is set while the synchronizer is searching for the CAS MF alignment word. Bit 0: FAS Sync Active (FASSA). This real-time status bit is set while the synchronizer is searching for alignment at the FAS level.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RNAF Receive Non-Align Frame Register (E1 Mode) base address + 0x194 Bit # 7 6 5 4 3 Name Si 1 A Sa4 Sa5 Default 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See RSLC2. 2 Sa6 0 1 Sa7 0 0 Sa8 0 The non-align frame is the E1 frame that does not contain the frame alignment signal (FAS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 SiF15 0 RSiNAF Receive Si Bits of the Non-Align Frame (E1 Mode Only) base address + 0x19C 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0 The non-align frame is the E1 frame that does not contain the frame alignment signal (FAS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F15 0 RSa4 Receive Sa4 Bits (E1 Mode Only) base address + 0x1A4 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0 The Sa4 bits received in each multiframe are saved in internal registers and latched into this register at the start of the next CRC-4 multiframe.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F15 0 RSa6 Receive Sa6 Bits (E1 Mode Only) base address + 0x1AC 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0 The Sa6 bits received in each multiframe are saved in internal registers and latched into this register at the start of the next CRC-4 multiframe.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F15 0 RSa8 Receive Sa8 Bits (E1 Mode Only) base address + 0x1B4 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0 The Sa8 bits received in each multiframe are saved in internal registers and latched into this register at the start of the next CRC-4 multiframe.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default Sa6CODE Receive Sa6 Codeword (E1 Mode Only) base address + 0x1BC 7 0 6 0 5 0 4 0 3 2 1 0 Sa6CODE3 Sa6CODE2 Sa6C0DE1 Sa6CODE0 0 0 0 0 Bits 3 to 0: Sa6 Codeword Bits (Sa6CODE[3:0]). This field reports the received Sa6 codeword per ETS 300 233.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RCR1-T1 Receive Control Register 1 (T1 Mode) base address + 0x204 Bit # 7 6 5 4 3 Name SYNCT RB8ZS RFM ARC SYNCC Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RCR1-E1. 2 RJC 0 1 SYNCE 0 0 RESYNC 0 Bit 7: Sync Time (SYNCT). 0 = Qualify 10 bits 1 = Qualify 24 bits Bit 6: Rx B8ZS Enable (RB8ZS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RCR1-E1 Receive Control Register 1 (E1 Mode) base address + 0x204 Bit # 7 6 5 4 3 Name RHDB3 RSIGM RCRC4 Default 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See RCR1-T1. 2 FRC 0 1 SYNCE 0 0 RESYNC 0 Bit 6: Rx HDB3 Enable (RHDB3). 0 = HDB3 decoding disabled 1 = HDB3 decoding enabled (decoded per O.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RIBCC Receive In-Band Code Control Register (T1 Mode) base address + 0x208 Bit # 7 6 5 4 3 Name --RUP2 RUP1 RUP0 Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RCR2-E1. 2 RDN2 0 1 RDN1 0 0 RDN0 0 2 0 1 0 0 RLOSA 0 Bits 5 to 3: Rx Up-Code Length Bits (RUP[2:0]). See Section 10.11.14.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 IDF 0 RCR3 Receive Control Register 3 base address + 0x20C 6 uALAW 0 5 RSERC 0 4 BINV1 0 3 BINV0 0 2 0 1 PLB 0 0 FLB 0 Bit 7: Input Data Format (IDF). See the pos/dat and neg signals in the Rx path in Figure 6-1. 0 = Bipolar data (AMI, HDB3 or B8ZS format) is expected from the LIU on the pos and neg signals.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default RIOCR Receive I/O Configuration Register base address + 0x210 7 6 5 4 RCLKINV RSYNCINV Reserved RSCLKM 0 0 0 0 3 RSMS 0 2 RSIO 1 1 RSMS2 0 0 RSMS1 0 Bit 7: RCLK Invert (RCLKINV). See the RCLK signal going into the Rx framer in Figure 6-1. 0 = No inversion 1 = Invert RCLK signal Bit 6: RSYNC Invert (RSYNCINV).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default RESCR Receive Elastic Store Control Register base address + 0x214 7 6 RDATFMT Reserved 0 0 5 0 4 RSZS 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 7: Receive Channel Data Format (RDATFMT).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 0 = MECU bit is used to manually update error counter registers 1 = GCR1.GFCLE is used to manually update error counter registers Bit 5: Manual Error Counter Update (MECU). When enabled by EAMS=1, changing this bit from zero to one allows the next clock cycle to load the error counter registers with the latest counts and reset the counters.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default RSCC In-Band Receive Spare Control Register (T1 Only) base address + 0x224 7 0 6 0 5 0 4 0 3 0 2 RSC2 0 1 RSC1 0 0 RSC0 0 2 RBPDIR 0 1 RBPFUS 0 0 RBPEN 0 Bits7 to 3: Reserved, must be set to zero for proper operation Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RBPBS8 0 RBPBS Receive BERT Port Bit Suppress Register base address + 0x22C 6 RBPBS7 0 5 RBPBS6 0 4 RBPBS5 0 3 RBPBS4 0 2 RBPBS3 0 1 RBPBS2 0 0 RBPBS1 0 Bit 7: Receive BERT Port Bit Suppress (RBPBS[8:1]).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RLS2-T1 Receive Latched Status Register 2 (T1 Mode) base address + 0x244 Bit # 7 6 5 4 3 Name RPDV COFA 8ZD 16ZD Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RLS2-E1. None of the bits in the register can cause an interrupt request. 2 SEFE 0 1 B8ZS 0 0 FBE 0 Bit 7: Receive Pulse Density Violation Event (RPDV).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 It is cleared when written with a 1. When RSA1 is set it can cause an interrupt request if the RSA1 interrupt enable bit is set in the RIM2 register. Bit 2: Receive Signaling All Zeros Event (RSA0). This latched status bit is set to 1 when, over a full MF, timeslot 16 contains all zeros. It is cleared when written with a 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RLS3-E1 Receive Latched Status Register 3 (E1 Mode) base address + 0x248 Bit # 7 6 5 4 3 Name LORCC V52LNKC RDMAC LORCD Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RLS3-T1. 2 0 1 V52LNKD 0 0 RDMAD 0 Bit 7: Loss of Receive Clock Clear (LORCC). This latched status bit is set to 1 when RRTS3-E1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 changes signaling state. RSCOS is cleared when written with a 1. When RSCOS is set it can cause an interrupt request if the corresponding interrupt enable bit is set in the RIM4 register. See Section 10.11.3.2. Bit 2: One Second Timer (1SEC). This latched status bit is set to 1 on every 1 second interval as timed by RCLK cycles. 1SEC is cleared when written with a 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RLS7-T1 Receive Latched Status Register 7 (T1 Mode) base address + 0x258 Bit # 7 6 5 4 3 Name RRAI-CI RAIS-CI RSLC96 Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RLS3-E1. 2 RFDLF 0 1 BC 0 0 BD 0 Bit 5: Receive RAI-CI Detect (RRAI-CI).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # RSS1 RSS2 RSS3 RSS4 7 CH8 CH16 CH24 CH32 RSS1, RSS2, RSS3, RSS4 Receive Signaling Status Registers base address + 0x260, 0x264, 0x268, 0x26C 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1* CH9 CH17* CH25 Bits 7 to 0 (x4): Receive Signaling Change Latched Status fo
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 RIIR Receive Interrupt Information Register base address + 0x27C 6 RLS7 0 5 RLS6* 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2** 0 0 RLS1 0 The bits in this register indicate which of the framer latched status registers, RLS1 through RLS7, are currently generating interrupt requests (1=interrupt request pending).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 RIM2 Receive Interrupt Mask Register 2 (E1 Mode Only) base address + 0x284 6 0 5 0 4 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS2-E1. Bit 3: Receive Signaling All Ones Event (RSA1).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 2: Spare Code Detected Condition Detect (LSPD). 0 = interrupt masked 1 = interrupt enabled Bit 1: Loop Down Code Detected Condition Detect (LDND). 0 = interrupt masked 1 = interrupt enabled Bit 0: Loop Up Code Detected Condition Detect (LUPD).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RESF 0 RIM4 Receive Interrupt Mask Register 4 base address + 0x28C 6 RESEM 0 5 RSLIP 0 4 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS4. Bit 7: Receive Elastic Store Full Event (RESF).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 3: Receive Packet End Event (RPE). 0 = interrupt masked 1 = interrupt enabled Bit 2: Receive Packet Start Event (RPS). 0 = interrupt masked 1 = interrupt enabled Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). 0 = interrupt masked 1 = interrupt enabled Bit 0: Receive FIFO Not Empty Set Event (RNES).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 RIM7-E1 Receive Interrupt Mask Register 7 (E1 Mode) base address + 0x298 6 0 5 0 4 0 3 0 2 0 1 Sa6CD 0 0 SaXCD 0 Note: This register has an alternate definition for E1 mode. See RIM7-T1. The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS7-E1. Bit 1: Sa6 Codeword Detect (Sa6CD).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 3: Receive Up Code Definition Bit 3 (C3). Ignored if a 1 to 4 bit length is selected. Bit 2: Receive Up Code Definition Bit 2 (C2). Ignored if a 1 to 5 bit length is selected. Bit 1: Receive Up Code Definition Bit 1 (C1). Ignored if a 1 to 6 bit length is selected. Bit 0: Receive Up Code Definition Bit 0 (C0). Ignored if a 1 to 7 bit length is selected.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 C15 0 RDNCD2 Receive Down Code Definition Register 2 base address + 0x2BC 6 C14 0 5 C13 0 4 C12 0 3 C11 0 2 C10 0 1 C0 0 0 C8 0 1 RLOS 0 0 RLOF 0 See Section 10.11.14. Bit 7: Receive Down Code Definition Bit 15 (C15). Ignored if a 1 to 7 bit length is selected. Bit 6: Receive Down Code Definition Bit 14 (C14).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RRTS3-T1 Receive Real-Time Status Register 3 (T1 Mode) base address + 0x2C8 Bit # 7 6 5 4 3 Name ----LORC Default 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RRTS3-E1. 2 LSP 0 1 LDN 0 0 LUP 0 These bits provide real-time status information from the receive framer. Bit 3: Loss of Receive Clock Condition (LORC).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 RRTS5 Receive Real-Time Status Register 5 (HDLC) base address + 0x2D0 Register Name: Register Description: Register Address: Bit # Name Default 7 0 6 PS2 0 5 PS1 0 4 PS0 0 3 0 2 0 1 RHWM 0 0 RNE 0 These bits provide real-time status information from the receive framer. Bits 6 to 4: Receive Packet Status (PS[2:0]). This field indicates Rx HDLC status as of the last FIFO read. See section 10.12.1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 RHF Receive HDLC FIFO Register base address + 0x2D8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 7 to 0: Receive HDLC Data (RHD[7:0]). A read of this register returns the next byte in the receive HDLC FIFO. Bit 7 is the MSb. This register is read-only. See section 10.12.1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # RCICE1 RCICE2 RCICE3 RCICE4 7 CH8 CH16 CH24 CH32 RCICE1, RCICE2, RCICE3, RCICE4 Receive Channel Idle Code Enable Registers base address + 0x340, 0x344, 0x348, 0x34C 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25 Bits 7 to 0 (x4): Receive Idle Code In
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 11.5.2 Transmit Formatter Registers Table 11-21 lists the transmit formatter registers. Some of these registers change function depending on whether E1 mode or T1/J1 mode is specified in the TMMR register. These dual-function registers are shown below using two lines of text, one for E1 and one for T1/J1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 4E8 4EC 4F0 4F4 4F8 4FC 500 504 508 50C 510 514 518 51C 520 524 528 52C 530 534 538 53C 540 544 548 54C 588 58C 590 594 598 59C 5A0 5A4 5A8 5AC 5B0 5B4 600 604 608 60C 610 614 618 61C 624 628 62C 638 640 644 648 Register Name TIDR1 TIDR1 TIDR1 TIDR1 TIDR1 TIDR1 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4 TFDL TBOC TSLC1 TAF TSLC2 TNAF TSLC3 TSiAF TSi
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Addr Offset 67C 680 684 688 6B0 6B4 6C4 6CC 6D0 6EC 700 704 708 70C 720 724 728 72C 740 744 748 74C 750 754 758 75C TIIR TIM1 TIM2 TIM3 TCD1 TCD2 TRTS2 TFBA THF TDS0M TBCS1 TBCS2 TBCS3 TBCS4 THSCS1 THSCS2 THSCS3 THSCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4 Register Name : Register Description: Register Address: Bit # TDMWE1 TDMWE2 TDMWE3 TDMWE4 Description Read/Write or Read Only Page Tx Interrupt In
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # TJBE1 TJBE2 TJBE3 TJBE4 7 CH8 CH16 CH24 CH32 TJBE1, TJBE2, TJBE3, TJBE4 Transmit Jammed Bit Eight Registers base address + 0x410, 0x404, 0x410, 0x41C 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25 Bits 7 to 0: Transmit Jammed Bit Eight Stuffing Contr
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 5: Transmit HDLC Reset (THR). A low-to-high transition of this bit resets the Tx HDLC controller and flushes the Tx HDLC FIFO. The Tx HDLC controller transmits an abort followed by intermessage fill (determined by the THC1.TFS bit) until a new packet transmission is initiated by writing new data into the FIFO.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 TABT 0 THC2 Transmit HDLC Control Register 2 base address + 0x44C 6 SBOC 0 5 THCEN 0 4 THCS4 0 3 THCS3 0 2 THCS2 0 1 THCS1 0 0 THCS0 0 Bit 7: Transmit Abort (TABT).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 1: Additional Bit 7 Insertion Control Bit (Sa7). 0 = Do not insert data from the TSa7 register into the transmit data stream 1 = Insert data from the TSa7 register into the transmit data stream Bit 0: Additional Bit 8 Insertion Control Bit (Sa8).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TS1 to TS16 Transmit Signaling Registers base address + 0x500 + 0x04*(n-1), n = 1 to 16 T1 Mode: Bit # TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 7 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # TCICE1 TCICE2 TCICE3 TCICE4 TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers base address + 0x540, 0x544, 0x548, 0x54C 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25 Bits 7 to 0 (x4): Transmit Idle Code
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TAF Transmit Align Frame (E1 Mode) base address + 0x590 Bit # 7 6 5 4 3 Name Si 0 0 1 1 Default 0 0 0 1 1 Note: This register has an alternate definition for T1 mode. See TSLC1. 2 0 0 1 1 1 0 1 1 The align frame is the E1 frame containing the frame alignment signal (FAS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TSiAF Transmit Si Bits of the Align Frames (E1 Mode) base address + 0x598 Bit # Name Default 6 TsiF12 0 7 TsiF14 0 5 TsiF10 0 4 TsiF8 0 3 TsiF6 0 2 TsiF4 0 1 TsiF2 0 0 TsiF0 0 The align frame is the E1 frame containing the frame alignment signal (FAS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TRA Transmit Remote Alarm Bits (E1 Mode Only) base address + 0x5A0 Bit # Name Default 6 TRAF13 0 7 TRAF15 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0 When RA=1 in TSACR, the bits of this register specify the remote alarm bits to be transmitted in outgoing multiframes.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TSa5 Transmitted Sa5 Bits (E1 Mode Only) base address + 0x5A8 Bit # Name Default 6 Tsa5F13 0 7 Tsa5F15 0 5 Tsa5F11 0 4 Tsa5F9 0 3 Tsa5F7 0 2 Tsa5F5 0 1 Tsa5F3 0 0 Tsa5F1 0 When Sa5=1 in TSACR, the bits of this register specify the Sa5 bits to be transmitted in outgoing multiframes.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 Tsa7F15 0 TSa7 Transmit Sa7 Bits (E1 Mode Only) base address + 0x5B0 6 Tsa7F13 0 5 Tsa7F11 0 4 Tsa7F9 0 3 Tsa7F7 0 2 Tsa7F5 0 1 Tsa7F3 0 0 Tsa7F1 0 When Sa7=1 in TSACR, the bits of this register specify the Sa7 bits to be transmitted in outgoing multiframes. The Sa7 bits are sampled from this register at the start of the multiframe.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN 0 TMMR Transmit Master Mode Register base address + 0x600 6 INIT_DONE 0 5 0 4 0 3 0 2 0 1 SFTRST 0 0 E1/T1 0 Bit 7: Formatter Enable (FRM_EN). This bit must be set to the desired state before setting the INIT_DONE bit.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 2: Transmit B8ZS Enable (TB8ZS). 0 = B8ZS encoding disabled 1 = B8ZS encoding enabled Bit 1: Transmit Alarm Indication Signal (TAIS). Configuration bit TCR4.TAISM specifies the type of AIS signal. 0 = Transmit data normally 1 = Transmit an unframed all-ones code at TPOS and TNEG Bit 0: Transmit Remote Alarm Indication (TRAI). Configuration bit TCR4.TRAIM specifies the type of RAI signal.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TCR2-T1 Transmit Control Register 2 (T1 Mode) base address + 0x608 Bit # Name Default 6 TSLC96 0 7 TFDLS 0 5 TDDSEN 0 4 FBCT2 0 3 FBCT1 0 2 TD4RM 0 1 PDE 0 0 TB7ZS 0 Bit 7: TFDL Register Select (TFDLS). 0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (if TCR2-T1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 AEBE 0 TCR2-E1 Transmit Control Register 2 (E1 Mode) base address + 0x608 6 AAIS 0 5 ARA 0 4 Sa4S 0 3 Sa5S 0 2 Sa6S 0 1 Sa7S 0 0 Sa8S 0 Bit 7: Automatic E–Bit Enable (AEBE). 0 = E–bits not automatically set in the transmit direction 1 = E–bits automatically set in the transmit direction Bit 6: Automatic AIS Generation (AAIS).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 TCR3 Transmit Control Register 3 base address + 0x60C Register Name: Register Description: Register Address: Bit # Name 7 ODF 6 -- 5 TCSS1 4 TCSS0 3 MFRS 2 TFM 1 IBPV Default 0 0 0 0 0 0 0 0 TLOOP CRC4R 0 Bit 7: Output Data Format (ODF). See the pos/dat and neg signals in the receive path in Figure 6-1. 0 = Bipolar data (AMI, HDB3 or B8ZS format) is output on the pos and neg signals.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default TIOCR Transmit I/O Configuration Register base address + 0x610 7 6 5 4 3 2 1 0 TCLKINV TSYNCINV TSSYNCINV TSCLKM TSSM TSIO TSDW TSM 0 0 0 0 0 0 0 0 Bit 7: TCLKF Invert (TCLKINV). See the TCLK signal going into the transmit formatter in Figure 6-1. 0 = No inversion 1 = Invert TCLK signal Bit 6: TSYNC Invert (TSYNCINV).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 TDATFMT 0 TESCR Transmit Elastic Store Control Register base address + 0x614 6 0 5 0 4 TSZS 0 3 TESALGN 0 2 TESR 0 1 TESMDM 0 0 TESE 0 Bit 7: Transmit Channel Data Format (TDATFMT). 0 = 64kBps (data contained in all 8 bits) 1 = 56kBps (data contained in 7 out of the 8 bits) Bit 6: Reserved, must be set to zero for proper operation.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 uALAW 0 TCR4 Transmit Control Register 4 (T1 Mode Only) base address + 0x618 6 BINV1 0 5 BINV0 0 4 TJBEN 0 3 TRAIM 0 2 TAISM 0 1 TC1 0 0 TC0 0 Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW). 0 = u-law code is inserted based on TDMWE registers. 1 = A-law code is inserted based on TDMWE registers.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 THFC Transmit HDLC FIFO Control Register base address + 0x61C 6 0 5 0 4 0 3 0 2 0 1 TFLWM1 0 0 TFLWM2 0 Bits 1 to 0: Transmit HDLC FIFO Low Watermark Select (TFLWM[1:0]). See section 10.12.2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 BPBSE8 0 TBPBS Transmit BERT Port Bit Suppress Register base address + 0x62C 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit 7: Transmit BERT Port Bit Suppress (TBPBS[8:1]).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default TLS1 Transmit Latched Status Register 1 base address + 0x640 7 6 5 4 TESF TESEM TSLIP TSLC96 0 0 0 0 3 TPDV TAF 0 2 1 0 TMF LOTCC LOTC 0 0 0 Bit 7: Transmit Elastic Store Full Event (TESF). This latched status bit is set to 1 when the transmit elastic store buffer fills and a frame is deleted.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 TLS2 Transmit Latched Status Register 2 (HDLC) base address + 0x644 6 0 5 0 4 TFDLE 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0 Bit 4: Transmit FDL Register Empty (TFDLE). T1 Mode Only. This latched status bit is set when the TFDL register has shifted out all 8 bits.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 0 TIIR Transmit Interrupt Information Register base address + 0x67C 6 0 5 0 4 0 3 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 The bits in this register indicate which of the framer latched status registers, TLS1 through TLS3, are currently generating interrupt requests (1=interrupt request pending).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 0: Loss of Transmit Clock Condition (LOTC). 0 = interrupt masked 1 = interrupt enabled Register Name: Register Description: Register Address: TIM2 Transmit Interrupt Mask Register 2 base address + 0x684 Bit # 7 6 5 4 3 2 1 Name TFDLE TUDR TMEND TLWMS Default 0 0 0 0 0 0 0 The bits in the register are interrupt mask/enable bits for corresponding latched status bits in TLS2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TCD1 Transmit Code Definition Register 1 (T1 Mode Only) base address + 0x6B0 Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 This register and TCD2 specify the code to be transmitted when TCR3.TLOOP is set to one. The length of the code is specified by TCR4.TC[1:0]. See section 10.11.14. Bit 7: Transmit Code Definition Bit 7 (C7).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Bit 0: Transmit FIFO Not Full Condition (TNF). This real-time status bit is set to 1 when the Tx HDLC FIFO has at least one byte available to accept new data. The TFBA register reports the actual number of bytes available. See section 10.12.2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # TBCS1 TBCS2 TBCS3 TBCS4 7 CH8 CH16 CH24 CH32 TBCS1, TBCS2, TBCS3, TBCS4 Transmit Blank Channel Select Registers base address + 0x700, 0x704, 0x708, 0x70C 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25 Bits 7 to 0 (x4): Transmit Blank Channel Select f
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # TBPCS1 TBPCS2 TBPCS3 TBPCS4 TBPCS1, TBPCS2, TBPCS3, TBPCS4 Transmit BERT Channel Select Registers base address + 0x750, 0x754, 0x758, 0x75C 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 0 CH1 CH9 CH17 CH25 Bits 7 to 0 (x4): Transmit BERT Port Chan
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Addresses: Bit # Name Default 7 RTR 0 LTRCR LIU Transmit Receive Control Register base address + 0x00 6 RHPM 0 5 JADS1 0 4 JADS0 0 3 JAPS1 0 2 JAPS0 0 1 T1J1E1S 0 0 LCS 0 Bit 7: Receiver Turns Ratio (RTR). This bit specifies the turns ratio for the LIU receiver. Internal termination is only available with the 1:1 transformer setting.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 LTISR LIU Transmit Impedance Selection Register base address + 0x04 Register Name : Register Description: Register Address: Bit # Name Default 7 TXG703 0 6 TIMPOFF 0 5 TIMPL1 0 4 TIMPL0 0 3 -0 2 L2 0 1 L1 0 0 L0 0 Bit 7: Transmit 2.048kHz G.703 Synchronous Mode (TXG703). Setting this bit to 1 configures the LIU to transmit the 2048kHz synchronization signal described in G.703 section 13 on TTIP/TRING.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 TAIS 0 LMCR LIU Maintenance Control Register base address + 0x08 6 ATAIS 0 5 LB2 0 4 LB1 0 3 LB0 0 2 TPDE 0 1 RPDE 0 0 TXEN 0 Bit 7: Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent timed by T1CLK or E1CLK. The transmit clock and data coming from the framer are ignored. See section 10.13.2.5.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 JAO 0 LRSR LIU Real-Time Status Register base address + 0x0C 6 JAU 0 5 OEQ 0 4 UEQ 0 3 JALT 0 2 SCS 0 1 OCS 0 0 LOS 0 These bit are read-only real-time status bits. Bit 7: JA Overflow (JAO). The jitter attenuator FIFO is currently in an overflow state. See section 10.13.4. Bit 6: JA Underflow (JAU).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: LSIMR LIU Status Interrupt Mask Register base address + 0x10 Bit # Name Default 6 OCCIM 0 7 JALTCIM 0 5 SCCIM 0 4 LOSCIM 0 3 JALTSIM 0 2 OCDIM 0 1 SCDIM 0 0 LOSDIM 0 This bits in this register mask or enable interrupts caused by the latched status bits in the LLSR register. Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 JALTC 0 LLSR LIU Latched Status Register base address + 0x14 6 OCC 0 5 SCC 0 4 LOSC 0 3 JALTS 0 2 OCD 0 1 SCD 0 0 LOSD 0 The bits in this register are latched status bits. Each bit is set when the associated event occurs and is only cleared when the CPU writes 1 to it.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default LRSL LIU Receive Signal Level base address + 0x18 7 RSL3 0 6 RSL2 0 5 RLS1 0 4 RLS0 0 3 -0 2 -0 1 -0 0 RFAIL 0 Bit 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). This read-only real-time status field indicates the incoming signal level at the LIU receiver.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default 7 RG703 0 LRISMR LIU Receive Impedance and Sensitivity Monitor Register base address + 0x1C 6 RIMPON 0 5 RIMPM2 0 4 RIMPM1 0 3 RIMPM0 0 2 RMONEN 0 1 RSMS1 0 0 RSMS0 0 Bit 7: Receive G.703 Clock (RG703). Setting this bit to 1 configures the LIU to receive the 2048kHz synchronization signal described in G.703 section 13 on RTIP/RRING.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: Bit # Name Default LDET LIU Detect base address + 0x20 7 -0 6 -0 5 -0 4 -0 3 -0 2 -0 1 -0 0 RFAIL 0 Bit 0: Receive Failure (RFAIL). This is a read-only real-time status bit. 0 = No short detected on the RTIP/RRING pins 1 = Short detected on the RTIP/RRING pins 11.5.4 BERT Registers Table 11-23 lists the BERT registers.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: BCR BERT Control Register base address + 0x00 Bit # Name Default 15 -0 14 -0 13 -0 12 -0 11 -0 10 -0 9 -0 8 -0 Bit # Name Default 7 PMUM 0 6 LPMU 0 5 RNPL 0 4 RPIC 0 3 MPR 0 2 APRD 0 1 TNPL 0 0 TPIC 0 Bit 7: Performance Monitoring Update Mode (PMUM). When 0, a local performance monitoring update is initiated by the LPMU register bit.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: BPCR BERT Pattern Configuration Register base address + 0x04 Bit # Name Default 15 -0 14 -0 13 -0 12 PTF4 0 11 PTF3 0 10 PTF2 0 9 PTF1 0 8 PTF0 0 Bit # Name Default 7 -0 6 QRSS 0 5 PTS 0 4 PLF4 0 3 PLF3 0 2 PLF2 0 1 PLF1 0 0 PLF0 0 Bits 12-8: Pattern Tap Feedback (PTF[4:0]).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: BSPR1 BERT Seed/Pattern Register 1 base address + 0x08 Bit # Name Default 15 BSP15 0 14 BSP14 0 13 BSP13 0 12 BSP12 0 11 BSP11 0 10 BSP10 0 9 BSP9 0 8 BSP8 0 Bit # Name Default 7 BSP7 0 6 BSP6 0 5 BSP5 0 4 BSP4 0 3 BSP3 0 2 BSP2 0 1 BSP1 0 0 BSP0 0 Bits 15-0: BERT Seed/Pattern (BSP[15:0]). See the BSP[31:0] description below.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: TEICR Transmit Error Insertion Control Register base address + 0x10 Bit # Name Default 15 -0 14 -0 13 -0 12 -0 11 -0 10 -0 9 -0 8 -0 Bit # Name Default 7 -0 6 -0 5 TEIR2 0 4 TEIR1 0 3 TEIR0 0 2 BEI 0 1 TSEI 0 0 -0 Bits 5-3: Transmit Error Insertion Rate (TEIR[2:0]).
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: BSRL BERT Status Register Latched base address + 0x1C Bit # Name Default 15 -0 14 -0 13 -0 12 -0 11 -0 10 -0 9 -0 8 -0 Bit # Name Default 7 -0 6 -0 5 -0 4 -0 3 PMSL 0 2 BEL 0 1 BECL 0 0 OOSL 0 The bits in this register are latched status bits. Each bit is set when the associated event occurs and is only cleared when the CPU writes 1 to it.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RBECR1 Receive Bit Error Count Register 1 base address + 0x28 Bit # Name Default 15 BEC15 0 14 BEC14 0 13 BEC13 0 12 BEC12 0 11 BEC11 0 10 BEC10 0 9 BEC9 0 8 BEC8 0 Bit # Name Default 7 BEC7 0 6 BEC6 0 5 BEC5 0 4 BEC4 0 3 BEC3 0 2 BEC2 0 1 BEC1 0 0 BEC0 0 Bit 15-0: Bit Error Count (BEC[15:0]). See the BEC[23:0] description below.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Register Name: Register Description: Register Address: RBCR1 Receive Bit Count Register 1 base address + 0x30 Bit # Name Default 15 BC15 0 14 BC14 0 13 BC13 0 12 BC12 0 11 BC11 0 10 BC10 0 9 BC9 0 8 BC8 0 Bit # Name Default 7 BC7 0 6 BC6 0 5 BC5 0 4 BC4 0 3 BC3 0 2 BC2 0 1 BC1 0 0 BC0 0 Bit 15-0: Bit Count (BC[15:0]) . See the BC[31:0] description below.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 12 JTAG Information For the latest JTAG model, search under http://www.maxim-ic.com/tools/bsdl/. JTAG Description The device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP and IDCODE. See Figure 12-1 for a block diagram. The device contains the following items which meet the requirements set by the IEEE 1149.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 12-2. JTAG TAP Controller State Machine Test-Logic-Reset 1 0 Run-Test/Idle 1 Select DR-Scan 1 0 1 Select IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 0 1 1 1 Exit1-DR 0 0 Pause-DR Pause-IR 0 1 0 0 1 0 Exit2-DR Exit2-IR 1 1 Update-IR Update-DR 1 1 Exit1-IR 0 1 0 Test-Logic-Reset.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the PauseDR state. Pause-DR. Shifting of the Test registers is halted while in this state. All Test registers selected by the current instruction retain their previous state.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 12-1. JTAG Instruction Codes Instructions SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Selected Register Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification Instruction Codes 010 111 000 011 100 001 SAMPLE/PRELOAD. A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Identification Register. The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state. Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is 32 bits in length.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 13 DC Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input, Bi-directional or Open Drain Output Lead with Respect to DVSS .................................................................................................-0.5V to +5.5V Supply Voltage (DVDDIO, DVDDLIU, ATVDDn, ARVDDn) with Respect to DVSS...............................-0.5V to +3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 14 AC Timing Characteristics Table 14-1. Input Pin Transition Time Requirements PARAMETER SYMBOL CONDITIONS Rise Time tr Fall Time tf MIN TYP MAX UNITS 10 to 90% of DVDDIO 6 ns 90 to 10% of DVDDIO 6 ns 14.1 LIU Characteristics Table 14-2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 14.2 LIU and Framer TDM Interface Timing Table 14-3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-2. Receive Framer Timing Using the RCLK Pin RCLK tD5 RSER F Bit tD6 RFSYNC_RMSYNC tD6 RSYNC Figure 14-3. Receive Framer Timing, Elastic Store Enabled tSP tSH tSL RSYSCLK tD3 RSER See note 3 tD4 RMSYNC RSYNC 1 tD4 tHD tSU RSYNC 2 NOTES: 1. RSYNC is in the output mode 2. RSYNC is in the input mode 3. F-bit when RIOCR.RSCLKM=0, MSB of timeslot 0 when RIOCR.RSCLKM=1 Figure 14-4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Table 14-4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-6. Transmit Formatter Timing, Elastic Store Enabled tSP tSL tSH TSYSCLK tHD tSU TSER 1 tHd tSU TSYNC NOTES: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Figure 14-7. Transmit Formatter Timing, Line Side with LIU Not Used tCP tCL tCH TCLKO tD3 TDATF 14.3 CPU Interface Timing Table 14-5.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-9. CPU Interface Write Cycle Timing T43 H_CS_N T35 T36 T33 T34 H_R_W_N H_AD[24:1] T40 H_WR_BEx_N[3:0] T31 T32 H_D[31:0](input) T26 T37 H_READY_N Figure 14-10. CPU Interface Read Cycle Timing T43 H_CS_N T35 T36 T33 T34 H_R_W_N H_AD[24:1] T22 H_D[31:0](output) T26 T44 T37 H_READY_N 14.4 SPI Interface Timing Table 14-6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-11. SPI interface Timing (SPI_CP = 0) T230 SPI_SEL_N T231 SPI_CLK(CI=0) SPI_CLK(CI=1) T236 T233 T233 T232 T232 T237 SPI_MISO(output) T235 T234 SPI_MOSI(input) Figure 14-12. SPI interface Timing (SPI_CP = 1) T230 SPI_SEL_N T231 SPI_CLK(CI=0) SPI_CLK(CI=1) T236 T233 T233 T232 T237 SPI_MISO(output) T235 T234 SPI_MOSI(input) 14.5 SDRAM Interface Timing Table 14-7.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-13.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-14.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 14.6 TDM-over-Packet TDM Interface Timing Table 14-8.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-16. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) T105 T100 TDMn_TCLK T101 T102 T101 T102 TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC TDMn_TX_MF_CD,TDMn_TX_SYNC T104 T103 TDMn_TX,TDMn_TSIG_CTS Figure 14-17.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-19. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1) T107 T106 TDMn_RCLK T109 T110 TDMn_RX,TDMn_RSIG_RTS,TDMn_RX_SYNC T106 TDMn_TCLK T104 T103 TDMn_TX,TDMn_TSIG_CTS T101 T102 TDMn_TX_MF_CD,TDMn_TX_SYNC Figure 14-20.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 14.7 Ethernet MII/RMII/SSMII Interface Timing Table 14-10. MII Management Interface AC Characteristics PARAMETER SYMBOL MDC Period (Note 1) MDC to MDIO Output Hold (Note 1) MDC to MDIO Output Valid (Note 1) MDIO Input Setup Prior to MDC Rising MDIO Input Hold After MDC Rising T150 T151 T152 T153 T154 MIN TYP MAX UNITS 180 ns ns ns ns ns MAX UNITS 320 10 20 0 NOTES: 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-23. MII Interface Input Signal Timing T158 T180 CLK_MII_RX T159 T160 MII_RXD,MII_RX_DV,MII_RX_ERR Table 14-13.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 14-26. SSMII Interface Output Signal Timing T171 T189 CLK_SSMII_TX T172 MII_TXD_0(SSMII_TXD) T172 MII_TXD_1(SSMII_TX_SYNC) Figure 14-27. SSMII Interface Input Signal Timing T171 T189 CLK_MII_RX(CLK_SSMII_RX) T175 T176 T175 T176 MII_RXD_0(SSMII_RXD) MII_RXD_1(SSMII_RX_SYNC) NOTES FOR SECTION 14.7: 1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 14.9 JTAG Interface Timing Table 14-18. JTAG Interface Timing PARAMETER JTCLK Clock Period JTCLK Clock High / Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO Hi-Z Delay JTRST_N Width Low Time SYMBOL t1 t2 / t3 t4 t5 t6 t7 t8 MIN TYP 1000 500 100 5 2 2 2 100 MAX 50 50 UNITS ns ns ns ns ns ns NOTES 1 2 NOTES: 1. Clock can be stopped high or low. 2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 15 Applications 15.1 Connecting a Serial Interface Transceiver Figure 15-1 below shows the connection of one port of a DS34T10x chip to a serial interface transceiver such as V.35 or RS-530. The figure shows one port in a DCE (Data Communications Equipment) application. All other ports can be connected in the same way. Each direction (Tx and Rx) has its own clock.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 15.2 Connecting an Ethernet PHY or MAC The figures below show the connection of the Ethernet port to a PHY or MAC device, in MII, RMII, and SSMII modes. Figure 15-2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode MII_TXD[3:2] MII_RXD[3:2] TXD[1:0] RXD [1:0] MII_TX_EN TX_EN MII_RX_DV RX_DV DS34T10x MII_RX_ERR RX_ERR CLK_MII_TX CLK MAC 50 MHz OSC. Figure 15-6.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 For the applications above, apply the following layout considerations: Provide termination on all high-speed interface signals and clock lines. Provide impedance matching on long traces to prevent reflections. Keep the clock traces away from all other signals to minimize mutual interference. In RMII mode, a very low skew clock buffer/driver is recommended to maximize the timing budget.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 15-9.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Figure 15-10.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 15.4.2 Connecting the H_READY_N Signal The H_READY_N output should be connected to the MPC860 TA input. The CPU bus operates asynchronously. The TA of the MPC860 is a synchronous input (i.e., needs to meet set-up and hold times). The designer should synchronize H_READY_N to the MPC860 clock by means of a CPLD, which uses the MPC860 reference clock.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 15.5 Working in SPI Mode The following table shows the I/O connections for operating in SPI mode. Table 15-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 16 PIN ASSIGNMENT 16.1 Board Design for Multiple DS34T10x Devices All devices in the DS34T10x family require the same footprint on the board. It is recommended that boards be design to support the use of higher port-count devices in a lower port-count socket. If this is done, unused inputs, input/outputs, and outputs must be biased appropriately.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL A8 D2 H1 R1 W2 AB9 AB15 P1 L1 V16 AA18 Y19 J1 J2 L21 L2 T5 V5 Y20 Y10 T18 G18 V18 V20 A12 E18 E20 C20 B11 G5 E5 C4 M9 N9 P10 P13 N14 P12 M14 L14 P11 K14 J12 J13 J11 J10 L9 K9 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket ATVSS2 ATVSS2 ATVSS2 ATVSS2 ATVSS3 ATVSS3 ATVSS3 ATVSS3 ATVSS4 ATVSS4 ATVSS4 ATVSS4 ATVSS5 ATVSS5 ATVSS5 ATVSS5 ATVSS6 ATVSS6 ATVSS6 ATVSS6 ATVSS7 ATV
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL C3 V3 M10 L13 H15 U17 L11 M11 K12 K11 K10 M12 N11 D4 H8 K13 M13 B12 N2 F6 L10 U6 W4 R8 N12 F17 L12 N10 R15 W19 N13 Y12 D19 Y3 E3 L18 N22 L15 P21 N16 N20 P22 N19 R21 M19 N21 M21 M17 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket DVDDLIU DVDDLIU DVDDLIU DVDDLIU DVDDLIU DVDDLIU DVDDLIU DVDDLIU DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVS
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL P20 R22 N17 T21 K16 M22 T20 M18 M16 M20 L16 K19 L17 T22 U21 V22 P18 W22 Y21 P19 Y22 AA21 AA22 AB21 U20 N18 R19 AB22 P17 V21 R17 V19 T19 W21 U16 R18 R20 W20 U19 T17 P16 U18 R16 U22 T16 J17 L22 K17 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket H_AD[21] H_AD[21] H_AD[21] H_AD[21] H_AD[22] H_AD[22] H_AD[22] H_AD[22] H_AD[23] H_AD[23] H_AD[23] H_AD[23] H_AD[24] H_AD[24] H_AD[24]
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL K18 L19 J16 J18 L20 T3 L3 M3 N3 K3 P3 M15 P15 N15 N1 AB17 AA20 AA17 Y18 Y17 V17 AA16 W16 AB16 Y16 W17 AB20 AB18 W18 AA19 AB19 C10 L4 C9 K5 D7 P6 Y6 P5 AB3 A6 L7 C5 F4 P4 Y4 AA5 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket H_READY_N H_READY_N H_READY_N H_READY_N H_WR_BE0_N/SPI_CLK H_WR_BE0_N/SPI_CLK H_WR_BE0_N/SPI_CLK H_WR_BE0_N/SPI_CLK H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI H_W
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL AA3 A11 K8 E7 G4 E4 M6 W8 T4 AB5 M8 A4 H4 D5 U4 U3 N7 V7 B13 B9 A2 E2 V2 AB2 AA10 AA12 J5 D6 H7 D3 N6 W6 T8 AB4 P2 A5 L6 A3 H6 W3 R4 AA6 M5 C6 K7 F8 H5 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket RDATF8 GND GND GND RESREF RESREF RESREF RESREF RF/RMSYNC1 RF/RMSYNC1 RF/RMSYNC1 RF/RMSYNC1 RF/RMSYNC2 RF/RMSYNC2 RF/RMSYNC2 NC RF/RMSYNC3 RF/RMSYNC3 NC NC RF/RMSYNC4 RF/RMSY
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket W5 U5 Y8 N8 A13 A9 A1 E1 V1 AB1 AB10 AB12 R3 J15 A17 F18 B19 D17 F16 B18 E17 A19 H17 F19 F20 D18 G17 C19 E16 H16 B17 C18 F21 B22 H20 C21 H18 C22 D21 G20 D22 J20 G21 G19 J21 E22 J19 RSYSCLK5 GND GND GND RSYSCLK6 GND GND GND RSYSCLK7 GND GND GND RSYSCLK8 GND GND GND RTIP1 RTIP1 RTIP1 RTIP1 RTIP2 RTIP2 RTIP2 NC RTIP3 RTIP
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL H21 F22 K21 G22 K20 H22 G16 A21 K22 J22 C16 A22 A18 B21 E21 H19 A20 E19 B20 D20 D16 C17 K15 B6 K4 D8 J6 T6 T7 U8 M4 L8 B5 J7 E6 N4 U7 P7 AA7 C7 J8 B4 K6 R6 N5 Y7 P8 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket SD_D[23] SD_D[23] SD_D[23] SD_D[23] SD_D[24] SD_D[24] SD_D[24] SD_D[24] SD_D[25] SD_D[25] SD_D[25] SD_D[25] SD_D[26] SD_D[26] SD_D[26] SD_D[26] SD_D[27] SD_D[27] S
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL E10 D12 C11 D10 D11 F12 E11 C12 F13 E13 E9 E12 C14 D13 C13 G10 F11 G11 F10 E14 G14 C15 G13 D15 D14 G9 G12 E15 F9 F14 H12 J14 F15 H9 H14 H11 G15 J9 H13 H10 V11 V9 T9 R11 U14 T13 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket TDM1_ACLK TDM1_ACLK TDM1_ACLK TDM1_ACLK TDM1_RCLK TDM1_RCLK TDM1_RCLK TDM1_RCLK TDM1_RSIG_RTS TDM1_RSIG_RTS TDM1_RSIG_RTS TDM1_RSIG_RTS TDM1_RX TDM1_RX TDM
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket P14 R12 R10 R14 W14 T12 R9 V12 T15 V15 V13 W15 U15 T10 V14 U13 T14 U12 R13 Y11 W9 W12 Y15 U11 Y13 U9 Y9 V10 T11 Y14 W11 W10 W13 U10 J3 B15 B7 C2 G2 T2 Y2 AA8 AA14 D9 J4 B3 TDM5_TSIG_CTS NC NC NC TDM5_TX NC NC NC TDM5_TX_MF_CD NC NC NC TDM5_TX_SYNC NC NC NC TDM6_ACLK NC NC NC TDM6_RCLK NC NC NC TDM6_RSIG_RTS NC NC NC
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 BALL F3 V6 R7 V8 P9 G3 L5 E8 G7 F5 M7 Y5 R5 AB6 C8 G8 F7 G6 V4 AA4 W7 AB7 A15 A7 C1 G1 T1 Y1 AB8 AB14 H3 DS34T108 Socket DS34T104 Socket DS34T102 Socket DS34T101 Socket TSER4 TSER4 GND GND TSER5 GND GND GND TSER6 GND GND GND TSER7 GND GND GND TSER8 GND GND GND TST_CLD TST_CLD TST_CLD TST_CLD TSYNC/TSSYNC1 TSYNC/TSSYNC1 TSYNC/TSSYNC1 TSYNC/TSSYNC1 TSYNC/TSSYNC2 TSYNC/TSSYNC2 TSYNC/TS
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 16.2 DS34T101 Pin Assignment Figure 16-1.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 16.3 DS34T102 Pin Assignment Figure 16-2.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 16.4 DS34T104 Pin Assignment Figure 16-3.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 16.5 DS34T108 Pin Assignment Figure 16-4.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 17 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. DS34T101, DS34T102 and DS34T108 have a 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions are shown in Maxim document 56-G6038-001. DS34T108 has a 484-lead ball grid array with embedded heat sink (HSBGA) package.
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 19 Data Sheet Revision History Date Description 04/20/07 Initial Release 07/11/08 Major revision. Extensive clean-up and corrections throughout. Many clarifications and crossreferences added. Some structural reorganization. Added G.8261 to list of ITU-T References on page 1. Changed number of pointers for ETH to CPU queue and pool from 64 each to 128 each (section 10.6.11.14). Max aggregate rate of 18.
