Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
145 of 366
The BERT function must be enabled and configured for each port (see the TXPC and RXPC regi
sters). The BERT
can be assigned to any combination of 64kbps channels within the E1/T1 signal using the bits in the TBPCS and
RBPCS regi
sters. Individual bit positions within the channels can be suppressed (i.e. not used for patterns) using
the bits in the TBPBS and RBPBS regist
ers.
The following tables show how to configure the BERT to send and Rx common telecom patterns.
Table 10-61. Pseudorandom Pattern Generation
BPCR REGISTER BCR
PATTERN TYPE
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS QRSS
BPCR BSPR2 BSPR1
TPIC,
RPIC
2
9
-1 O.153 (511 type) 04 08 0 0 0x0408 0xFFFF 0xFFFF 0
2
11
-1 O.152 and O.153
(2047 type)
08 0A 0 0 0x080A 0xFFFF 0xFFFF 0
2
15
-1 O.151 0D 0E 0 0 0x0D0E 0xFFFF 0xFFFF 1
2
20
-1 O.153 10 13 0 0 0x1013 0xFFFF 0xFFFF 0
2
20
-1 O.151 QRSS 02 13 0 1 0x0253 0xFFFF 0xFFFF 0
2
23
-1 O.151 11 16 0 0 0x1116 0xFFFF 0xFFFF 1
Table 10-62. Repetitive Pattern Generation
BPCR REGISTER
PATTERN TYPE
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS QRSS
BPCR BSPR2 BSPR1
all 1s NA 00 1 0 0x0020 0xFFFF 0xFFFF
all 0s NA 00 1 0 0x0020 0xFFFF 0xFFFE
alternating 1s and 0s NA 01 1 0 0x0021 0xFFFF 0xFFFE
double alternating and 0s NA 03 1 0 0x0023 0xFFFF 0xFFFC
3 in 24 NA 17 1 0 0x0037 0xFF20 0x0022
1 in 16 NA 0F 1 0 0x002F 0xFFFF 0x0001
1 in 8 NA 07 1 0 0x0027 0xFFFF 0xFF01
1 in 4 NA 03 1 0 0x0023 0xFFFF 0xFFF1
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BCR.T
NPL and BCR.RNPL.
Monitoring the BERT requires reading the BSR Register which contains the Bit Error Count (BEC) bit and the Out
of Synchronization (OOS) bit. The BEC bit is set when the bit error counter is one or more. The OOS is set when
the Rx pattern generator is not synchronized to the incoming pattern, which occurs when it receives a minimum of
6 bit errors within a 64-bit window. The Rx BERT Bit Count Registers (RBCR) and the Rx BERT Bit Error Count
Registers (RBECR)
are updated upon the zero-to-one transition of a performance monitor update signal (either
BCR.LPM
U or GCR2.BRPMU as specified by BCR.PMUM). This signal updates the registers with the values of the
counters since the last update and resets the counters.
10.14.4 BERT Receive Pattern Detection
The Rx BERT synchronizes the Rx pattern generator to the incoming pattern. The Rx pattern generator is a 32-bit
shift register that shifts data from the least significant bit (LSB, bit 1) to the most significant bit (MSB, bit 32). The
input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
n
+ x
y
+ 1), the feedback is an XOR of bit
n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually