Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsLinear IC - Amplifier - Video buffering Rail-to-rail TQFN 48 (7x7)

DS3514

C Gamma and V

COM

Buffer with EEPROM

________________________________________________________________

Maxim Integrated Products

Rev 1; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS3514 is a programmable gamma and V

COM

volt-

age generator that supports both real-time updating as

well as multibyte storage of gamma/V

COM

data in on-

chip EEPROM memory. An independent 10-bit DAC, two

10-bit data registers, and four words of EEPROM memo-

ry are provided for each individually addressable

gamma or V

COM

channel. High-performance buffer

amplifiers are integrated on-chip, providing rail-to-rail,

low-power (400µA/gamma channel) operation. The

COM

channel features a high current drive (> 250mA

peak) and a fast-settling buffer amplifier optimized to

drive the V

COM

node of a wide range of TFT-LCD panels.

Programming occurs through an I

C-compatible serial

interface. Interface performance and flexibility are

enhanced by a pair of independently loaded data latch-

es per channel, as well as support for I

C speeds up to

400kHz. The multitable EEPROM memory enables a

rich variety of display system enhancements, including

support for temperature or light-level dependent

gamma tables, enabling of factory or field automated

display adjustment, and support for backlight dimming

algorithms to reduce system power. Upon power-up

and depending on mode, DAC data is selected from

EEPROM by the S0/S1 pins or from a fixed memory

address.

Applications

TFT-LCD Gamma and V

COM

Buffer

Adaptive Gamma and V

COM

Adjustment (Real

Time by I

C, Select EEPROM Through I

C or

S0/S1 Pins)

Industrial Process Control

Features

♦ 10-Bit Gamma Buffers, 14 Channels

♦ 8-Bit V

COM

Buffer, 1 Channel

♦ Four 10-Bit EEPROM Words per Channel

♦ Low-Power 400µA/ch Gamma Buffers

♦ I

C-Compatible Serial Interface

♦ Flexible Control from I

C or Pins

♦ 9.0V to 15.0V Analog Supply

♦ 2.7V to 5.5V Digital Supply

♦ 48-Pin TQFN Package (7mm x 7mm)

Gamma or V

COM

Channel Functional Diagram

Ordering Information

EEPROM

SDA, SCL

* 10 BITS FOR GAMMA CHANNELS, 8 BITS FOR THE V

COM

CHANNEL.

S1/ S0

IN OUT

ADDRESS

INTERFACE

LATCH A

LATCH B

LOGIC

MUX

8-/

10-BIT*

DAC

OUT

Pin Configuration and Typical Operating Circuit appear at

end of data sheet.

PART TEMP RANGE PIN-PACKAGE

DS3514T+ -45°C to +95°C 48 TQFN-EP*

DS3514T+T&R -45°C to +95°C 48 TQFN-EP*

Denotes a lead-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

Summary of content (21 pages)

PAGE 1
Rev 1; 10/08 I2C Gamma and VCOM Buffer with EEPROM The DS3514 is a programmable gamma and VCOM voltage generator that supports both real-time updating as well as multibyte storage of gamma/VCOM data in onchip EEPROM memory. An independent 10-bit DAC, two 10-bit data registers, and four words of EEPROM memory are provided for each individually addressable gamma or V COM channel. High-performance buffer amplifiers are integrated on-chip, providing rail-to-rail, low-power (400µA/gamma channel) operation.
PAGE 2
DS3514 I2C Gamma and VCOM Buffer with EEPROM ABSOLUTE MAXIMUM RATINGS Junction Temperature ......................................................+125°C Operating Temperature Range ...........................-45°C to +95°C Programming Temperature Range .........................0°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Voltage Range on VDD Relative to GND ................
PAGE 3
I2C Gamma and VCOM Buffer with EEPROM (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Input Resistance (GHH, GHM, GLM, GLL) Power-Up Time MAX 75 Input Resistance Tolerance Power-On Recall Voltage TYP UNITS k TA = +25°C -20 +20 VPOR (Note 7) 1.6 2.6 tD (Note 8) 25 % V ms OUTPUT ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, VRL = +2.0V, GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = +13.0V, GHH = +14.
PAGE 4
DS3514 I2C Gamma and VCOM Buffer with EEPROM I2C ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 4.) PARAMETER SYMBOL CONDITIONS TYP UNITS 400 kHz Bus-Free Time between STOP and START Conditions tBUF 1.3 μs Hold Time (Repeated) START Condition tHD:STA 0.6 μs tLOW 1.3 μs High Period of SCL 0 MAX f SCL Low Period of SCL (Note 14) MIN SCL Clock Frequency tHIGH 0.
PAGE 5
I2C Gamma and VCOM Buffer with EEPROM (VCC = +2.7V to +5.5V.) PARAMETER SYMBOL EEPROM Write Cycles Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: CONDITIONS MIN MAX TA = +85°C (Guaranteed by design) 50,000 TA = +25°C (Guaranteed by design) 200,000 UNITS Writes All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
PAGE 6
DS3514 I2C Gamma and VCOM Buffer with EEPROM VIH S0/S1 VIL tHD tSU tSET-G GM1–GM14 VIH 100pF ILOAD LD VIL 4tAU SETTLED GM1–G14 Figure 2. GM1–GM14 Settling Timing Diagram VIH S0/S1 (LD = VCC) VIL GM1–GM14 tSEL 100pF OUTPUT 10% SETTLED GM1–GM14 Figure 3. Input Pin to Output Change Timing Diagram SDA tBUF tF tHD:STA tLOW tSP SCL tHIGH tHD:STA tHD:DAT STOP tSU:STA tR START tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 4.
PAGE 7
I2C Gamma and VCOM Buffer with EEPROM DIGITAL SUPPLY STANDBY CURRENT vs. VCC 20 15 10 450 DS3514 toc03 25 ICCQ CURRENT (μA) 25 SDA = SCL = VCC 400 350 IDDQ CURRENT (μA) SDA = SCL = VCC DS3514 toc02 30 DS3514 toc01 30 ICCQ CURRENT (μA) ANALOG SUPPLY STANDBY CURRENT vs. VDD DIGITAL SUPPLY STANDBY CURRENT vs. TEMPERATURE 20 VCC = 5.0V 15 10 300 250 200 150 100 5 5 50 VCC = 3.3V 0 3 4 6 5 -45 15 35 55 75 9 95 11 15 13 VDD VOLTAGE (V) ANALOG SUPPLY STANDBY CURRENT vs.
PAGE 8
Typical Operating Characteristics (continued) (VCC = +5.0V, VDD = +15V, TA = +25°C, unless otherwise noted.) VCOM INL VCOM DNL 0.40 0.30 0 0.20 0.10 0 -0.20 -0.30 -0.40 -0.40 -0.50 0 32 64 96 128 160 192 224 256 32 120 90 60 30 1.0E-6 LOAD CAPACITANCE (F) 10.0E-6 500 UNITY GAIN BANDWIDTH (kHz) 150 96 128 160 192 224 256 VCOM UNITY GAIN BANDWIDTH vs. LOAD CAPACITANCE DS3514 toc13 180 64 VCOM SETTING (DEC) VCOM PHASE MARGIN vs.
PAGE 9
I2C Gamma and VCOM Buffer with EEPROM PIN NAME TYPE 1–5, 9, 10, 46, 48 N.C. — FUNCTION No Connection 6, 23, 43 VDD Power 7 VRH Ref Input High-Voltage Reference for VCOM DAC Analog Supply (9.0V to 15.5V) Low-Voltage Reference for VCOM DAC 8 VRL Ref Input 11, 18, 19, 21, 22, 42 GND Power Ground 12 S1 Input 13 S0 Input Select Inputs. When the Control register [1,0] = 00, S0 and S1 are used to select DAC input data from EEPROM.
PAGE 10
I2C Gamma and VCOM Buffer with EEPROM DS3514 Block Diagram GHH BANKS GM14 BANK A GM14 BANK B GM14 BANK C GM14 BANK D DS3514 S0/S1 PINS S0/S1 BITS GHH GHH MUX 0 0 10 BITS LATCH B 10-BIT DAC 1 GM14 LATCH A 1 LD GHM I2C MODE1 BIT MODE0 BIT COMP BANKS GM8 BANK A GM8 BANK B GM8 BANK C GM8 BANK D S0/S1 PINS S0/S1 BITS GHH MUX 0 0 10 BITS LATCH B 10-BIT DAC 1 GM8 LATCH A 1 LD GHM SDA SCL A0 I2C INTERFACE I2C I2C COMP LOGIC AND CONTROL MODE1 BIT GHM MODE0 BIT (CR.
PAGE 11
I2C Gamma and VCOM Buffer with EEPROM The DS3514 operates in one of three modes that determine how the V COM and gamma DACs are controlled/updated. The first two modes allow “banked” control of the 14 gamma channels and one VCOM channel. Depending on the mode, one of four banks (in EEPROM) can be selected using either the S0/S1 pins or using the SOFT S0/S1 bits in the Soft S0/S1 register. Once a bank is selected, the LD pin can then be used to simultaneously update each channel’s DAC output.
PAGE 12
DS3514 I2C Gamma and VCOM Buffer with EEPROM Map , the Latch A registers for each channel are accessed through memory addresses 00–1Ch. Then, like the other modes, the LD pin determines when the DACs are updated. If the LD signal is high, Latch B is flow-through and the DAC is updated immediately. If LD is low, Latch B is loaded from Latch A after a low-tohigh transition on the LD pin. This latter method allows the timing of the DAC update to be controlled by an external signal pulse.
PAGE 13
I2C Gamma and VCOM Buffer with EEPROM Slave Address Byte and Address Pin The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 5). The DS3514’s slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same I2C bus. Connecting A0 to GND results in a 0 in the corresponding bit position in the slave address. Conversely, connecting A0 to VCC results in a 1 in the corresponding bit position.
PAGE 14
I2C Gamma and VCOM Buffer with EEPROM DS3514 Memory Map (continued) ADDRESS NAME 14 DESCRIPTION TYPE MEMORY OR COMMAND I2C ACCESS (HEX) (DEC) Latch A for GM13 Ch 1Ah, 1Bh 26, 27 10-Bit I2C Data for GM13 DAC Volatile R/W Latch A for GM14 Ch 1Ch, 1Dh 28, 29 10-Bit I2C Data for GM14 DAC Volatile R/W Reserved 1Eh–3Fh 30–63 — — — Soft S1/S0 40h 64 Software Bank Select Byte (Bits 1:0) Volatile R/W Standby 41h 65 Shutdown Byte Volatile R/W Reserved 42h–47h 66–71 — — — Co
PAGE 15
I2C Gamma and VCOM Buffer with EEPROM FACTORY DEFAULT 00h MEMORY TYPE Volatile 40h x x x x x x SOFT S1 BIT 7 SOFT S0 BIT 0 Bits 7:2 Reserved Bits 1:0 These bits are used when in SOFT S0/S1 Bit-Controlled Bank-Updating mode (MODE1 = 0, MODE0 = 1) SOFT S1, SOFT S0: 00 = Selects VCOM and GM1–GM14 Bank A 01 = Selects VCOM and GM1–GM14 Bank B 10 = Selects VCOM and GM1–GM14 Bank C 11 = Selects VCOM and GM1–GM14 Bank D Standby Register 41h: Standby Mode Enable FACTORY DEFAULT 00h MEMORY TYPE V
PAGE 16
DS3514 I2C Gamma and VCOM Buffer with EEPROM Control Register 48h: Control Register (CR) FACTORY DEFAULT 20h MEMORY TYPE NV 48h x x BIAS1 BIAS0 x x MODE1 BIT 7 MODE0 BIT 0 Bits 7:6 Reserved Bits 5:4 VCOM and Gamma Bias Current Control Bits (BIAS[1:0]): 00 = 60% 01 = 80% 10 = 100% (default) 11 = 150% Bits 3:2 Reserved Bits 1:0 DS3514 Mode (MODE[1:0]): 00 = S0/S1 pins are used to select the desired bank (A–D) (default). 01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D).
PAGE 17
I2C Gamma and VCOM Buffer with EEPROM I2C Definitions The following terminology is commonly used to describe I2C data transfers. (See Figure 4 and the I2C Electrical Characteristics for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master’s request.
PAGE 18
DS3514 I2C Gamma and VCOM Buffer with EEPROM I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte-write operations.
PAGE 19
I2C Gamma and VCOM Buffer with EEPROM DS3514 TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 1 0 0 SLAVE ADDRESS* 0 0 A0 R/W MSB SLAVE ACK b7 LSB b6 READ/ WRITE b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 b4 REGISTER ADDRESS b3 b2 b1 b0 SLAVE ACK STOP DATA *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0. EXAMPLE I2C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND).
PAGE 20
I2C Gamma and VCOM Buffer with EEPROM DS3514 Typical Operating Circuit 15V 14.8V 8V 7V 0.2V VDD GHH GHM GLM GLL 14 5V VCC SCL SDA I2C MASTER SOURCE DRIVER GM1 GM2 GM3 GM4 GM5 GM6 GM7 DS3514 S0 S1 LD GM8 GM9 GM10 GM11 GM12 GM13 GM14 A0 GND VRH VRL 13V 2V VCOM 36 35 34 33 32 31 30 29 28 27 26 25 GM1 GM14 37 24 GLM 38 23 VDD GLL 39 22 GND GHM 40 21 GND GHH 41 20 VCAP GND 42 19 GND VDD 43 18 GND VCOM 44 17 VCC A0 45 16 SCL N.C.
PAGE 21
I2C Gamma and VCOM Buffer with EEPROM REVISION NUMBER REVISION DATE 0 9/08 1 10/08 DESCRIPTION PAGES CHANGED Initial release. — Changed the maximum VCC supply current (lCC) specification from 0.5mA to 0.6mA. 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.