Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS3923T+

General Description

The DS3923 high-speed current mirror integrates high-

voltage devices necessary for monitoring the burst-mode

receive power signal in avalanche photodiode (APD) bias-

ing and optical line terminal (OLT) applications. It provides

small and large gain current mirror outputs to monitor the

APD current. A sample/hold circuit with automatic gain

selection captures the sampled signal so that an external

ADC can accurately measure the signal. An adjustable

current clamp limits current through the APD. The clamp

also features an external shutdown. An integrated FET is

also provided which can be used with an external DC-DC

controller to create a high-voltage boost DC-DC converter.

The DS3923 is available in a 24-pin TQFN package and

operates over an extended temperature range of -40°C

to +95°C.

Applications

● APD Biasing

● GPON OLT

● 10GPON OLT

Features

● Supports -32dBm to -5dBm Optical Input Range with

±0.5dB Accuracy

● 15V to 76V APD Bias

● Pin Discharge Option

● Sampling Period as Short as 300ns

● External Capacitor Connection for Controlled RC

Time Constant of APD Voltage Filter

● Current Clamp with Adjustable Limit and External

Shutdown with Limit Status

● 3.5mm x 3.5mm, 24-Pin TQFN Package with

Exposed Pad

● Two Current Mirror Outputs and Additional Small-

Signal Current Mirror Output for ADC Measurement

● High-Voltage Switch FET for DC-DC Boost Converter

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer

to www.maximintegrated.com/DS3923.related.

19-6848; Rev 1; 8/14

0.1I

0.2I

0.8I

MIRIN

100Ω

0.1µF

330kΩ

4.99kΩ

1.8V

MIRIN

MIROUT

330pF

500pF

APD

250µw

1µw

3.3V

300ns

min

250µw

APDV VIP1 VIP2

1kΩ

OPT.

1kΩ

OPT.

CURRENT

LIMIT

TEMP

LIMIT

DUAL

GAIN

SAMPLE/

HOLD

DISCHARGE

RLIM

IOUT

DIFFEN

VOP

VON

VIN

ILIMS

GAIN

SENXOR

ISRC/

SHDN

30kΩ

SRC

4.7µH

HVG

PWM

GPIO[2:0]

GPIO

(BY DEFAULT Hi-Z)

[APD SHUTDOWN]

>300ns PULSE

OCCURS ONCE PER

100µS TO ONCE

PER 100ms

HVD

DS3923

DS4830

VCC

GND

SEN

3.3V

AVCC

3.3V

10kΩ

GPIO

(EDGE INTERRUPT)

[DETECT SEN EDGE]

ADC [BM RSSI MONITOR,

AVERAGE RSSI,

MIRROR VOLTAGE DROP

DC-DC FEEDBACK]

200µA

TIA

ADJUSTED FROM 55V AT -40°C TO 65V AT 95°C

Typical Application Circuit

DS3923 High-Speed Current Mirror

with Sample/Hold Output

EVALUATION KIT AVAILABLE

Summary of content (15 pages)

PAGE 1
EVALUATION KIT AVAILABLE DS3923 High-Speed Current Mirror with Sample/Hold Output General Description Features ●● Supports -32dBm to -5dBm Optical Input Range with ±0.5dB Accuracy ●● 15V to 76V APD Bias ●● Pin Discharge Option ●● Sampling Period as Short as 300ns ●● External Capacitor Connection for Controlled RC Time Constant of APD Voltage Filter ●● Current Clamp with Adjustable Limit and External Shutdown with Limit Status ●● 3.5mm x 3.
PAGE 2
DS3923 High-Speed Current Mirror with Sample/Hold Output Absolute Maximum Ratings Voltage on HVD, MIRIN, MIRCAP, and MIROUT Relative to HVGND ...........................................-0.3V to +79V Voltage on VCC and AVCC to GND.....................-0.3V to + 4.3V Voltage on All Other Pins Relative to GND....................-0.3V to (VCC + 0.3V) Not to Exceed +4V Continuous Power Dissipation (TA = +70°C) TQFN (derate 15.4mW/°C above +70°C)...............1228.9mW Storage Temperature Range................
PAGE 3
DS3923 High-Speed Current Mirror with Sample/Hold Output Electrical Characteristics (continued) (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL VOL CONDITIONS MIN TYP IGAIN = -30µA MAX UNITS 0.4 Logic Output Levels (GAIN Has 3.5kΩ Internal Nominal Impedance) VOH IGAIN = +30µA ILIMS Output Time tILIMS (Note 4) IOUT to MIROUT Ratio KIOUT IMIROUT = 1mA 0.090 0.100 0.110 A/A VIP1 to MIROUT Ratio KVIP1 IMIROUT = 1mA 0.
PAGE 4
DS3923 High-Speed Current Mirror with Sample/Hold Output Sample and Hold Parameters (VMIRIN = 15V to 76V, VCC = 2.85V to 3.63V, TA = -40°C to +95°C, RISRC = 30kΩ, DISCHARGE = high, unless otherwise noted.
PAGE 5
DS3923 High-Speed Current Mirror with Sample/Hold Output VIP1/VIP2 tS tDEL SENINT tO_VAL tO_VAL MAX OUTPUT VALID MIN VOP - VON GAIN VOLTAGE INVALID GAIN VALID GAIN VALID tADC EXTERNAL ADC DATA tS = SAMPLE TIME DATA VALID tDEL = DELAY TIME tADC = ADC CONVERSION TIME tO_VAL = OUTPUT VALID TIME UL VOP - VON LL LOWER LIMIT (LL) UPPER LIMIT (UL) VIP1 < 0.4 (0.91 x 4 x IM x RVIP1)/1.25 (1.09 x 4 x IM x RVIP1)/1.25 VIP1 > = 0.4 (0.91 x 4 x IM x RVIP2)/5 (1.
PAGE 6
DS3923 High-Speed Current Mirror with Sample/Hold Output Block Diagram IOUT VIP1 VIN VIP2 MIRIN I1 4V 0.8I1 0.2I1 0.1I1 AVCC AVCC MIRCAP RMIRCAP CS ILIMS DIFFEN VOP VON 4X CURRENT LIMIT RLIM TEMP LIMIT 0.4 CS ISRC/ SHDN MIROUT VCC DS3923 AVCC DISCHARGE 1.8V HVD D Q RG GAIN SAMPLE DISCHARGE SEN SENINT SENXOR GND HVGND VCC HVG AVCC MIRIN 0.5V/V APDV MIROUT www.maximintegrated.
PAGE 7
DS3923 High-Speed Current Mirror with Sample/Hold Output Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ICC vs. TEMPERATURE 7.4 VVOP vs. TEMPERATURE toc01 2.00 VCC = 3.3V 1.80 1.60 IMIROUT = 1.0mA 7 6.8 VVOP (V) ICC (mA) 7.2 IMIROUT = 0.4mA IMIROUT = 0.4mA 1.20 1.00 IMIROUT = 1.0mA 0.60 0.40 6.4 6.2 IMIROUT = 2.0mA 1.40 0.80 6.6 0.20 -40 -15 10 35 60 85 0.00 110 -40 -15 VVOP vs. VCC 1.8 VVOP (V) 35 60 1.
PAGE 8
DS3923 High-Speed Current Mirror with Sample/Hold Output DISCHARGE RLIM APDV ILIMS ISRC/SHDN GAIN Pin Configuration 18 17 16 15 14 13 MIROUT 19 12 VOP HVG 20 11 VON 10 GND 9 SEN 8 SENXOR 7 IOUT MIRCAP 21 DS3923 MIRIN 22 EP + 1 2 3 4 5 VCC AVCC DIFFEN VIP2 VIP1 HVD 24 6 VIN HVGND 23 24-LEAD TQFN (3.5mm x 3.5mm x 0.8mm) Pin Description PIN NAME FUNCTION 1 VCC Digital 3.3V (Nominal) Supply 2 AVCC Analog 3.
PAGE 9
DS3923 High-Speed Current Mirror with Sample/Hold Output Pin Description (continued) PIN NAME 10 GND Ground 11 VON Negative Sample/Hold Voltage Output. Do not connect for single-ended mode. 12 VOP Sample/Hold Voltage Output. Positive output in differential mode. Also used for single-ended output. GAIN Hold Amplifier Gain Indicator. Both as output and logic input. Indicates which current mirror’s output is active. 3.5kΩ input/output impedance.
PAGE 10
DS3923 High-Speed Current Mirror with Sample/Hold Output Detailed Description hold circuit. On pin VIP1 and VIP2, resistors to ground should be selected such that the maximum voltage is 0.625V (2.5V after the 4x gain of the built-in amplifier). For example, if the maximum monitored current through the APD is 1mA, the mirror is 1.25:1 ratio, and then the correct resistor is approximately 780Ω. The DS3923 contains circuits to create an APD bias voltage and to monitor the APD bias current.
PAGE 11
DS3923 High-Speed Current Mirror with Sample/Hold Output Current Mirror Voltage Drop Monitor The DS3923 includes a voltage monitor that indicates the voltage drop across the current mirror. This signal is output on APDV. This signal should be used to accurately maintain the correct APD bias voltage in conjunction with the feedback resistors for the APD bias boost converter.
PAGE 12
DS3923 High-Speed Current Mirror with Sample/Hold Output Table 1. Sample/Hold Output Voltage vs. Input INPUT SELECTED (AUTO OR FORCED) SAMPLE/HOLD OUTPUT VOLTAGE VIP1 4 × VIP1 = 4 × 0.8 × I1 × R4 = 3.2 × I1 × R4 VIP2 4 × VIP2 = 4 × 0.2 × I1 × R5 = 0.8 × I1 × R5 resistance of the voltage source connected to the sample/ hold’s input and the DS3923’s sampling capacitors. An external capacitor may be used on the sample/hold’s inputs.
PAGE 13
DS3923 High-Speed Current Mirror with Sample/Hold Output tS SEN PULSE VIP1 VIP2 DISCHARGE DISABLE tS SEN PULSE VIP1 VIP2 DISCHARGE ENABLE Figure 5. Discharge, Current Mirror, and SEN Pulse Timing Diagram Table 2. Sample/Hold Input Selection VIP1 INPUT SELECTED OUTPUT VOLTAGE GAIN OUTPUT < 0.4V VIP1 4 × VIP1 0 ≥ 0.4V VIP2 4 × VIP2 VCC Alternatively, forcing GAIN = 0 always chooses VIP1 and forcing GAIN = VCC chooses VIP2. By default, GAIN pin is pulled high.
PAGE 14
DS3923 High-Speed Current Mirror with Sample/Hold Output VIP2 NOT DS3923 AMPLIFIER X4 400mV SAMPLE/HOLD COMPARATOR D Q VIP1 VOP VON NOT RG SENINT GAIN Figure 6. GAIN Selection Logic Diagram Applications Information Layout Considerations Proper PCB layout helps to reduce switching noise in the system. HVGND is the connection of the switching FET and thus carries high current pulses. HVGND should also be connected to the boost converter’s input capacitor and output bulk capacitor.
PAGE 15
DS3923 High-Speed Current Mirror with Sample/Hold Output Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 12/13 Initial release 1 8/14 Notes added to Pin Description and Discharge section stating SENXOR should not be a logic-high if the discharge feature is being used. DESCRIPTION — 8, 9, 12 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.