Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS4100H+

General Description

The DS4100H is a low-jitter 100MHz clock oscillator

with a high-speed current steering logic (HCSL) output.

It combines an AT-cut crystal, an oscillator, and a low-

noise phase-locked loop (PLL) in a 5mm by 3.2mm

ceramic package. Typical phase jitter is 0.9ps

RMS

from

12kHz to 20MHz. The device operates from a single

+3.3V supply.

Applications

PCI Express

Features

♦ 100MHz Output Frequency

♦ 3.3V ±5% Operating Voltage

♦ HCSL Output

♦ Phase Jitter (RMS): 0.9ps Typical

♦ ±39ppm Frequency Stability Over Voltage,

Temperature, 10 Years of Aging

♦ Output-Enable (OE) Control Input

♦ 5mm x 3.2mm x 1.49mm Ceramic Package (LCCC)

♦ Pb Free/RoHS Compliant

DS4100H

100MHz HCSL Clock Oscillator

________________________________________________________________

Maxim Integrated Products

TOP VIEW

RREF

N.C.

*EP

*EXPOSED PAD

N.C.

N.C. N.C.

GND

OUTN

OUTP

(5.00mm

3.20mm

1.49mm)

DS4100H

Pin Configuration

Ordering Information

3.3V

GND

OUTP

OUTN

RREF

DS4100H

475Ω

±1%

PCI Express

LOAD OR

CONNECTOR

Typical Operating Circuit

Rev 1; 4/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free package. The lead finish is JESD97

category e4 (Au over Ni) and is compatible with both lead-based

and lead-free soldering processes.

PCI Express is a registered trademark of PCI-SIG Corp.

PART TEMP RANGE PIN-PACKAGE

TOP

MARK

DS4100H+ -40°C to +85°C 10 LCCC 10H

Summary of content (7 pages)

PAGE 1
Rev 1; 4/08 100MHz HCSL Clock Oscillator The DS4100H is a low-jitter 100MHz clock oscillator with a high-speed current steering logic (HCSL) output. It combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5mm by 3.2mm ceramic package. Typical phase jitter is 0.9psRMS from 12kHz to 20MHz. The device operates from a single +3.3V supply. Applications PCI Express® Features ♦ 100MHz Output Frequency ♦ 3.3V ±5% Operating Voltage ♦ HCSL Output ♦ Phase Jitter (RMS): 0.
PAGE 2
DS4100H 100MHz HCSL Clock Oscillator ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (VCC) .......................................-0.3V, +4V Continuous Power Dissipation (TA = +70°C) ...................280mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ...............................-40°C to +85°C Soldering Temperature Profile (3 passes max) ...................................
PAGE 3
100MHz HCSL Clock Oscillator (VCC = 3.135V to 3.465V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Output Disable Time t PZ CONDITIONS MIN TYP Figure 3 (Note 6) CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN Clock Output f OUT Frequency Stability Total f / f O Over temperature range, aging, load, and supply (Note 7) Initial Frequency Tolerance f_TOL VCC = 3.
PAGE 4
Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 0 -5 -10 -20 0 20 40 60 80 0.5 0.3 0.0 -0.3 -0.5 -0.8 3.190 3.245 3.300 3.355 3.410 3.465 DS4100H toc03 DS4100H toc02 0.8 -1.0 3.135 -15 75.0 fOUT DEVIATION FROM VCC = 3.3V (ppm) 5 1.0 fOUT DEVIATION FROM VCC = 3.3V (ppm) DS4100H toc01 10 -40 SUPPLY CURRENT vs. SUPPLY VOLTAGE CLOCK OUTPUT vs. SUPPLY VOLTAGE FREQUENCY vs.
PAGE 5
100MHz HCSL Clock Oscillator Z0 RS DS4100H OUTP OUTP CL OUTPUT BUFFER Z0 = 50Ω, 35in LENGTH RECEIVER RS OUTN Z0 RT RT OUTN CL CL = 2pF RT = 50Ω RS = 0Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION. CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY. Figure 2. Typical Termination for HCSL Driver and Test Conditions 0.7 x VCC OE 0.3 x VCC tPZH tPZ OUTP GND tPZL OUTN GND Figure 3.
PAGE 6
DS4100H 100MHz HCSL Clock Oscillator Detailed Description The DS4100H is a low-jitter HCSL 100MHz clock oscillator. It combines an AT-cut crystal, an oscillator, and a low-noise PLL in a 5mm by 3.2mm ceramic package. The typical phase jitter is 0.9ps RMS from 12kHz to 20MHz. The device operates from a single +3.3V supply. Chip Information TRANSISTOR COUNT: 2850 SUBSTRATE CONNECTED TO GROUND PROCESS: Bipolar SiGe Thermal Information PLL The PLL generates a 1.
PAGE 7
100MHz HCSL Clock Oscillator REVISION NUMBER REVISION DATE 0 11/07 DESCRIPTION Initial release. — In the Electrical Characteristics table, added the typical supply current value of 71mA; corrected the units for the clock phase noise parameter from ps to dBc/Hz. 1 4/08 PAGES CHANGED In the Pin Description, changed the exposed pad description to indicate that it should not be connected and to avoid placing exposed metal under the pad location.