Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - I/O extensions EEPROM, POR I²C, JTAG 400 kHz TSSOP 20

General Description

The DS4550 is a 9-bit, nonvolatile (NV) I/O expander

with 64 bytes of NV user memory controlled by either

an I

C-compatible serial interface or an IEEE 1149.1

JTAG port. The DS4550 offers a digitally programmable

alternative to hardware jumpers and mechanical

switches that are being used to control digital logic

nodes. Each I/O pin is independently configurable. The

outputs are open drain with selectable pullups. Each

output has the ability to sink up to 16mA, and since the

device is NV, it powers up in the desired state allowing

it to control digital logic inputs immediately on power-

up without having to wait for the host CPU to initiate

control.

Applications

RAM-Based FPGA Bank Switching for Multiple

Profiles

Selecting Between Boot Flash

Setting ASIC Configurations/Profiles

Servers

Network Storage

Routers

Telecom Equipment

PC Peripherals

Features

♦ Programmable Replacement for Mechanical

Jumpers and Switches

♦ Nine NV Inputs/Outputs

♦ 64-Byte NV User Memory (EEPROM)

♦ I

C-Compatible Serial Interface and JTAG

♦ Up to 8 Devices can be Multidropped on the Same

C Bus

♦ IEEE 1149.1 Boundary Scan Compliant

♦ Open-Drain Outputs with Configurable Pullups

♦ Outputs Capable of Sinking 16mA

♦ Low Power Consumption

♦ Wide Operating Voltage Range: 2.7V to 5.5V

♦ Operating Temperature Range: -40°C to +85°C

DS4550

C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

______________________________________________ Maxim Integrated Products 1

GND

I/O_8

I/O_7

I/O_6I/O_3

I/O_2

I/O_1

I/O_0

TOP VIEW

I/O_5

TDO

TDITCK

I/O_4

SCL

SDAV

TMS

TSSOP

DS4550

FPGA

CLOCK

GENERATOR

CPU SPEED

SELECT

GND

0.1μF

4.7k

INTERFACE

JTAG

INTERFACE

DS4550

SCL

SDA

TCK

TMS

TDI

TDO

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

I/O_8

Pin Configuration

Typical Operating Circuit

Rev 0; 9/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

DS4550E -40°C to +85°C 20 TSSOP

Add “/T&R” for tape and reel orders.

Summary of content (18 pages)

PAGE 1
Rev 0; 9/04 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory The DS4550 is a 9-bit, nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by either an I2C-compatible serial interface or an IEEE 1149.1 JTAG port. The DS4550 offers a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes. Each I/O pin is independently configurable. The outputs are open drain with selectable pullups.
PAGE 2
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory ABSOLUTE MAXIMUM RATINGS Voltage on VCC, SDA, and SCL Pins Relative to Ground.............................................-0.5V to +6.0V Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8] Relative to Ground ...................................-0.5V to VCC + 0.5V, not to exceed +6.0V. Operating Temperature Range ...........................-40°C to +85°C EEPROM Programming Temperature Range .........
PAGE 3
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory DS4550 AC ELECTRICAL CHARACTERISTICS-–I2C Interface (See Figure 5) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between Stop and Start Conditions tBUF Hold Time (Repeated) Start Condition tHD:STA CONDITIONS (Note 4) MIN TYP 0 (Note 5) MAX UNITS 400 kHz 1.3 µs 0.6 µs µs Low Period of SCL tLOW 1.
PAGE 4
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.7V to +5.5V, unless otherwise noted.) PARAMETER SYMBOL EEPROM Writes CONDITIONS MIN +70°C (Note 3) TYP MAX UNITS 50,000 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: All voltages referenced to ground. ISTBY is specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCC or GND. Guaranteed by design. Timing shown is for fast-mode (400kHz) operation.
PAGE 5
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory SUPPLY CURRENT vs. SUPPLY VOLTAGE I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED SUPPLY CURRENT (µA) 1 0.5 1.5 VCC = SDA = SCL = 5.5V = TCK 1 0.5 18 16 SUPPLY CURRENT (µA) 2 1.5 20 DS4550 toc03 I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED VCC = SDA = SCL = TCK DS4550 toc02 2.5 DS4550 toc01 2 14 12 VCC = SDA = TCK = 5.0V 10 8 6 4 VCC = SDA = SCL = 2.7V = TCK 2 0 4 4.5 5 5.
PAGE 6
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory DS4550 Pin Description 6 PIN NAME FUNCTION 1 I/O_0 Input/Output 0. Bidirectional I/O pin. 2 I/O_1 Input/Output 1. Bidirectional I/O pin. 3 I/O_2 Input/Output 2. Bidirectional I/O pin. 4 I/O_3 Input/Output 3. Bidirectional I/O pin. 5 I/O_4 Input/Output 4. Bidirectional I/O pin. 6 A0 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 7 A1 I2C Address Input.
PAGE 7
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory VCC VCC DS4550 SDA SCL A0 A1 A2 BSC BSC BSC BSC BSC I2C INTERFACE PULLUP ENABLE (F0h-F1h) VCC RJPU TMS TDI TDO TCK GND I/O CONTROL REGISTERS BSC RPU EEPROM 64 BYTES USER MEMORY RJPU JTAG CONTROL PORT (x9) VCC I/O CELL I/O_n [n = 0 TO 8] I/O CONTROL (F2h-F3h) BSC I/O STATUS (F8h-F9h) BSC BOUNDARY SCAN CELL (BSC) Detailed Description The DS4550 contains nine bidirectional, NV, input/output (I/O) pins, and a 64-byte EEPROM user memory
PAGE 8
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Memory Map and Memory Types The DS4550 memory map is shown in Table 1. Three different types of memory are present in the DS4550: EEPROM, SRAM-shadowed EEPROM, and SRAM. Memory locations specified as EEPROM are NV. Writing to these locations results in an EEPROM write cycle for a time specified by tWR in the AC Electrical Characteristics table.
PAGE 9
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory MSB 1 LSB 0 1 0 A2 A1 A0 R/W READ/WRITE BIT SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. IEEE 1149.1 JTAG Operation The DS4550 contains an IEEE 1149.1 compliant JTAG port in addition to the I2C serial bus. Either can be used to access the internal memory. However, the device contains no bus arbitration and hence both busses cannot be used at the same time. All of the I/O pins on the DS4550 are IEEE 1149.
PAGE 10
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Test Access Port (TAP) Controller State Machine rising edge of TCK, the controller goes to the Shift-DR state if TMS is LOW or it goes to the Exit1-DR state if TMS is HIGH. The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK (see Figure 4). Test-Logic-Reset. Upon power-up, the TAP controller is in the Test-Logic-Reset state. The Instruction Register contains the IDCODE instruction.
PAGE 11
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Exit2-IR. A rising edge on TCK with TMS HIGH puts the controller in the Update-IR state. The controller loops back to Shift-IR if TMS is LOW during a rising edge of TCK in this state. Update-IR. The instruction code that has been shifted into the Instruction shift register is latched to the parallel outputs of the Instruction Register on the falling edge of TCK as the controller enters this state.
PAGE 12
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory CLAMP. All digital outputs of the device output data from the Boundary Scan parallel output while connecting the Bypass test data register between TDI and TDO. The outputs do not change during the CLAMP instruction. HIGHZ. All digital outputs of the device are placed in a high-impedance state. The Bypass test data register is connected between TDI and TDO. IDCODE.
PAGE 13
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory CELL NUMBER NAME TYPE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A2 input A1 input A0 input SCL input SDA input SDA output IO8 pubout IO8 pdbout IO8 input IO7 pubout IO7 pdbout IO7 input IO6 pubout IO6 pdbout IO6 input IO5 pubout IO5 pdbout Input Observe Only Input Observe Only Input Observe Only Input Observe Only Input Observe Only Output Output Output Input Observe Only Output Output Input Observe Only Output Output Input Observe Only O
PAGE 14
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Table 5. EEPROM Write Cycle STEP Select Address Register Load EEPROM Address Select Write Register Write EEPROM Data TAP STATE COMMENTS Select-IR-Scan  Capture-IR  Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Exit1-IR  Update-IR  Select-DR-Scan  Capture-DR No-op. Shift-DR (8 x TCK) The 8-bit address is shifted in through TDI.
PAGE 15
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8-bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition.
PAGE 16
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory The DS4550’s slave address of the DS4550 is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave.
PAGE 17
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Applications Information Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it must NACK to indicate the end of the transfer and generate a stop condition.
PAGE 18
DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Package Information Chip Topology TRANSISTOR COUNT: 21,161 SUBSTRATE CONNECTED TO GROUND For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.