DS4830 Optical Microcontroller User’s Guide Rev 0.3 8/2012 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
DS4830 User’s Guide Contents SECTION 1 – OVERVIEW ...................................................................................................................................................... 9 SECTION 2 – ARCHITECTURE ........................................................................................................................................... 11 2.1 – Instruction Decoding .................................................................................................................
DS4830 User’s Guide 7.1.3 – Temperature Conversion ................................................................................................................................... 48 7.1.4 – Sample and Hold Conversion ............................................................................................................................ 48 7.1.5 – ADC Frame Sequence .......................................................................................................................................
DS4830 User’s Guide 11.1 – Detailed Description .............................................................................................................................................. 90 11.1.1 – Default Operation ............................................................................................................................................. 90 11.1.2 – Slave Address ...........................................................................................................................
DS4830 User’s Guide 14.2.3 – Pulse Spreading............................................................................................................................................. 116 14.2.4 – Alternate PWM Output ................................................................................................................................... 119 14.2.5 – PWM DELAY Register (PWMDLYn).............................................................................................................. 119 14.
DS4830 User’s Guide SECTION 18 – HARDWARE MULTIPLIER MODULE ....................................................................................................... 140 18.1 – Hardware Multiplier Organization ......................................................................................................................... 140 18.2 – Hardware Multiplier Controls ................................................................................................................................ 140 18.
DS4830 User’s Guide 22.2.1 – JTAG Bootloader Protocol ............................................................................................................................. 172 22.2.2 – I2C Bootloader Protocol ................................................................................................................................. 172 22.3 – Bootloader Commands ......................................................................................................................................
DS4830 User’s Guide 23.6.2 - Zero Flag ........................................................................................................................................................ 185 23.6.3 - Equals Flag ..................................................................................................................................................... 185 23.6.4 - Carry Flag .........................................................................................................................
DS4830 User’s Guide SECTION 1 – OVERVIEW The DS4830 System Management Microcontroller provides a complete optical control, calibration, and monitor solution. The IC is based on the high-performance 16-bit family of MAXQ® reduced instruction set computing (RISC) microcontrollers, and provides generous amounts of flash program memory and SRAM data memory.
DS4830 User’s Guide Figure 1-1 DS4830 Block Diagram This document is provided as a supplement to the DS4830 IC data sheet. This user’s guide provides the information necessary to develop applications using the DS4830. All electrical and timing specifications, pin descriptions, package information, and ordering information can be found in the DS4830 IC data sheet.
DS4830 User’s Guide SECTION 2 – ARCHITECTURE The DS4830 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with flash memory. It is structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data.
DS4830 User’s Guide prefix register is cleared to zero after one cycle so it will not affect any other instructions. The write to the prefix register is done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute in a single cycle, two cycles are needed for instructions that require the prefix register. The architecture of the DS4830 is transport-triggered.
DS4830 User’s Guide Table 2-1. Register-to-Register Transfer Operations SOURCE REGISTER DESTINATION REGISTER PREFIX SIZE (BITS) SIZE (BITS) SET? 8 8 X 8 16 No 8 16 Yes 16 8 X 16 16 X DESTINATION SET TO VALUE HIGH 8 BITS LOW 8 BITS — Source [7:0] 00h Source [7:0] PFX [7:0] Source [7:0] — Source [7:0] Source [15:8] Source [7:0] 2.
DS4830 User’s Guide The width of the stack is 16 bits to accommodate the instruction pointer size. On reset, the stack pointer SP initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt vectoring operations first increment SP and then store a value at @SP. The RET, RETI, POP, and POPI operations first retrieve the value at @SP and then decrement SP. The stack memory is initialized to indeterminate values upon reset or power-up.
DS4830 User’s Guide 2.4.2 – Program Memory Mapping The DS4830’s mapping of the three memory segments (flash, SRAM, and utility ROM) as program memory is shown in Figure 2-2. The mapping of memory segments into program space is always the same. When referring to memory as program memory, all addresses are given as word addresses. The 32KWord flash memory segment is located at memory location 0000h through 7FFFh and is logically divided into two pages, each containing 16KWords.
DS4830 User’s Guide pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memory location addressed by the data pointer. Following are some examples of setting and using a data pointer. move DP[0], #0100h move Acc, @DP[0] move @DP[0], Acc ; set pointer DP[0] to address 100h ; read data from location 100h ; write to location 100h The address pointed to by the data pointers can be automatically incremented or decremented.
DS4830 User’s Guide 2.4.4.1 – Memory Map When Executing from Flash Memory When executing from the flash memory: Read and write operations of SRAM memory are executed normally. The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. Figure 2-3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is executing from the flash memory segment.
DS4830 User’s Guide 2.4.4.2 – Memory Map When Executing from Utility ROM When executing from the utility ROM: Read and write operations of SRAM memory are executed normally. Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 8000h as determined by the CDA0 bit.
DS4830 User’s Guide 2.4.4.3 – Memory Map When Executing from SRAM When executing from the SRAM: The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 0000h.
DS4830 User’s Guide 2.5 – Data Alignment To support merged program and data memory operation while maintaining efficient memory space usage, the data memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while maintaining data accessibility at the byte level.
DS4830 User’s Guide POR BROWNOUT STATE CPU DISABLED ANALOG ACTIVE VDD > VBO VDD < VBO SYSTEM CLOCK STARTUP DELAY CPU MODE VDD < VBO DIGITAL CORE ON ANALOG ON CODE EXECUTION Figure 2-6: DS4830 State Diagram 2.6.2 – Watchdog Timer Reset The watchdog timer is a programmable hardware timer that can be used to reset the processor in case a software lockup or other unrecoverable error occurs. Once the watchdog is enabled, software must reset the watchdog timer periodically.
DS4830 User’s Guide 2.6.4 – Internal System Resets There are two possible sources of internal system resets. An internal reset will hold the DS4830 in reset mode for 12 clock cycles. 2 1. When data BBh is written to the special I C slave address 34h. 2. When in-system programming is complete and the ROD bit is set to 1. 2.7 – Clock Generation The DS4830 generates its 20MHz peripheral clock using an internal oscillator and generates 10MHz instruction clock by divide 2.
DS4830 User’s Guide SECTION 3 – SYSTEM REGISTER DESCRIPTIONS Most functions of the DS4830 are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers.
DS4830 User’s Guide Table 3-2.
DS4830 User’s Guide 3.1 Accumulator Pointer Register (AP, 8h[0h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. Bit 7:4 Name Reserved 3:0 AP[3:0] Function Reserved. All reads return 0. Active Accumulator Select. These bits select which of the 16 accumulator registers are used for arithmetic and logical operations.
DS4830 User’s Guide 3.5 Interrupt Mask Register (IMR, 8h[6h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted read/write access. Bit 7 6 5 4 3 2 1 0 Name IMS Reserved IM5 IM4 IM3 IM2 IM1 IM0 Function Interrupt Mask for System Modules Reserved. All reads return 0.
DS4830 User’s Guide 3.8 Watchdog Control Register (WDCN, 8h[Fh]) Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. Access: Unrestricted direct read/write access. BIT NAME 7 POR 6 EWDI 5:4 WD[1:0] 3 WDIF 2 WTRF 1 EWT 0 RWT DESCRIPTION Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset.
DS4830 User’s Guide 3.10 Prefix Register (PFX[n], Bh[n]) Initialization: This register is cleared to 0000h on all forms of reset. Access: Unrestricted direct read/write access. BIT NAME 15:0 PFX[n][15:0] DESCRIPTION The Prefix register provides a means of supplying an additional 8 bits of high-order data for use by the succeeding instruction as well as providing additional indexing capabilities.
DS4830 User’s Guide 3.16 Frame Pointer Offset Register (OFFS, Eh[3h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. BIT 7:0 DESCRIPTION This 8-bit register provides the Frame Pointer (FP) offset from the base pointer (BP). The Frame Pointer is formed by unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs).
DS4830 User’s Guide 3.22 General Register High Byte (GRH, Eh[9h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. BIT 7:0 DESCRIPTION This register reflects the high byte of the GR register and is intended primarily for supporting byte operations on 16-bit data. Any data written to the GRH register will also be stored in the high byte of the GR register. 3.
DS4830 User’s Guide SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS Reg M0 M1 M2 M3 M4 M5 0 PO2 I2CBUF-M I2CBUF-S MCNT DACD0 QTDATA 1 PO1 I2CST-M I2CST-S MA DACD1 QTCN 2 PO0 I2CIE-M I2CIE-S MB DACD2 LTIF 3 EIF2 PO6 ADCN MC2 DACD3 HTIF 4 EIF1 SPIB_S DADDR MC1 DACD4 SPIB_M 5 EIF0 MIIR1 SENR MC0 DACD5 PWMDATA 6 GTV1 EIF6 ADST GTV2 DACD6 PWMCN 7 GTCN1 EIE6 ADADDR GTCN2 DACD7 PWMSYNC 8 PI2 PI6 MIIR2 MC1R DACCFG LTIE 9 PI1 SVM ADDATA MC0R HT
DS4830 User’s Guide MODULE 0 Register index 15 14 13 12 11 10 PO2 00h 9 8 7 6 5 4 PO2[7:0] 3 2 1 0 PO1 01h PO1[7:0] PO0 02h EIF2 03h IE7 IE6 IE5 IE4 EIF1 04h IE7 IE6 IE3 IE2 IE1 IE0 IE5 IE4 IE3 IE2 IE1 EIF0 05h IE7 IE0 IE6 IE5 IE4 IE3 IE2 IE1 GTV1 06h IE0 GTCN1 07h PI2 08h - - GTIF PI2[7:0] PI1 09h PI1[7:0] PI0 0Ah GTC1 0Bh EIE2 0Dh EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0 EIE1 0Eh EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0 EIE0 0Fh EX
DS4830 User’s Guide MODULE 1 Register index 15 14 13 12 11 10 9 I2CBUF_M 00h 8 7 6 5 4 I2CST_M 01h I2CBUS I2CBUSY - - I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI - I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI I2CIE_M PO6 02h 03h - - - - I2CSPIE - I2CROIE I2CGCIE I2CNACKIE - - I2CAMIE I2CTOIE I2CSTRIE PO6[6:0] I2CRXIE I2CTXIE I2CSRIE SPIB_S 04h MIIR1 05h - - - - - SPI_S - I2CM SVM P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 EIF6 06h - IE6 IE5 IE4 I
DS4830 User’s Guide MODULE 2 Register index 15 14 13 I2CBUF_S 00h I2CST_S 01h I2CBUS I2CBUSY - - I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI - I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI I2CIE_S 02h - - - - I2CSPIE - I2CROIE I2CGCIE I2CNACKIE - I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE ADDAINV ADCONT ADDAIE LOC_OVR ADCN 03h 04h SENR 05h ADST 06h - - - ADADDR 07h - - - MIIR2 08h ADDATA 09h TWR 0Ah 0Bh I2CCN_S 0Ch I2CCK_S 0Dh 11 10 9 8
DS4830 User’s Guide MODULE 3 Register index 15 14 13 12 11 10 MCNT 00h 9 8 7 6 5 4 3 2 1 0 OF MCW CLD SQU OPCS MSUB MMAC SUS MA 01h MB 02h MB[15:0] MC2 03h MC2[15:0] MC1 04h MC1[15:0] MC0 05h MC0[15:0] GTV2 06h GTV2[15:0] GTCN2 07h MC1R 08h MC1R[15:0] - - GTIF - MC0R 09h MC0R[15:0] GTC2 0Ah GTC2[15:0] Register index 15 14 13 12 DACD0 00h - - - - DACD0[11:0] 5 4 3 DACD1 01h - - - - DACD1[11:0] DACD2 02h - - - - DACD2[11
DS4830 User’s Guide SECTION 5 – INTERRUPTS The DS4830 provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority.
DS4830 User’s Guide Note: Some of the DS4830 module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hierarchy diagram. Please refer the corresponding sections of this user’s guide for more detailed information about all of the possible interrupts. 5.1 – Servicing Interrupts For the DS4830 to service an interrupt, interrupts must be enabled globally, modularly, and locally.
DS4830 User’s Guide I2C Slave Transmit Complete Interrupt I2C Slave Receive Ready Interrupt I2C Slave Clock Stretch Interrupt I2C Slave Timeout Interrupt I2C Slave Address Match Interrupt I2C Slave NACK Interrupt I2C Slave General Call Interrupt I2C Slave Receiver Overrun Interrupt I2C Slave Stop Interrupt ADC Data Available Interrupt Internal Temperature Interrupt External Temperature 0 Interrupt External Temperature 1 Interrupt Sample and Hold 0 Interrupt Sample and Hold 1 Interrupt 3 Wire Interrupt Timer
DS4830 User’s Guide pending interrupt. The peripheral register bits inside the module also provide a way to differentiate among interrupt sources. Section 5.2 has more detail on the Module Interrupt Identification Registers. The Interrupt Vector (IV) register provides the location of the interrupt service routine. It may be set to any location within program memory.
DS4830 User’s Guide 5.3 – Interrupt System Operation The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an interrupt flag is set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor one clock cycle later, assuming the request does not hit the interrupt exception window.
DS4830 User’s Guide When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the prefix value to be used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses it must always be executed back to back. Therefore, writing to the PFX register causes an interrupt exception window on the next cycle.
DS4830 User’s Guide SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) The DS4830 contains eight 12-bit digital-to-analog converters (DACs). Each DAC has a voltage output buffer. Each DAC can independently select between a 2.5V internal reference and external reference at REFINA pin for DAC0 to DAC3 and at REFINB pin for DAC4 to DAC7.
DS4830 User’s Guide The DAC Data register programs the DAC for a particular voltage output depending on the value of this register and the reference setting. The DAC outputs are voltage buffered and have the capability to sink or source current. Each DAC output has an output impedance which limits the DAC operating range if configured to sink current (refer to the DS4830 IC data sheet). The DAC output voltage is maintained during any type of reset except POR.
DS4830 User’s Guide 6.2.
DS4830 User’s Guide 6.3 – DAC Code Examples 6.3.1 – DAC0 enabled with internal reference and output voltage is configured for 50% (1.25V) of internal reference. DACCFG = 0x0002; DACD0 = 0x0800; //Only DAC0 enabled and internal reference is selected //DACD0 is set for 50% 6.3.2 – DAC2 enabled with external reference and output voltage is configured for 25% of external reference at REFINA pin. DACCFG = 0x0010; DACD2 = 0x0400; //Only DAC2 enabled and external reference is selected //DACD2 is set for 25% 6.
DS4830 User’s Guide SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) NUM_SMP ADCONT ADCONV ADEND ADSTART The DS4830 provides a 13-bit analog-to-digital converter (ADC) with 26-input MUX. As shown in Figure 7-1, the MUX selects the ADC input from 16 external channels, DAC external references at REFINA and REFINB, VDD, DAC Internal Reference, Internal Die Temperature, External Remote Diode temperatures at GP8-GP9 and GP10-GP11, Sample and Hold at GP2-GP3 and GP12-GP13 and ADC Internal Offset.
DS4830 User’s Guide By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL). The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick Trip use. Each bit location in this register corresponds to the ADC/Quick Trip input pin. The ADC controller uses a set of Special Function Registers (SFRs) to configure the ADC for the desired mode of operation.
DS4830 User’s Guide case for sequence conversion, where the starting and ending configuration address is the same. The configuration registers can be viewed as a circular register array where ADSTART does not have to be less than ADEND. For example, if ADSTART = 1 and ADEND = 5, then the sequence of conversions would be configurations 1, 2, 3, 4, 5. If ADSTART = 5 and ADEND = 1, then the sequence of conversions would be configurations 5, 6, 7,…… 23 , 0, 1.
DS4830 User’s Guide 3. S/H0 has priority over S/H1 if both S/Hs are ready for conversion. However, in next slot for S/H, the S/H1 will get slot even if S/H0 is also ready. For example, if the ADC sequence mode conversion is enabled for channel 0, 4, 5, 6 and all secondary channels are enabled and ready for conversion then the sequence of conversion is performed as shown in figure 7-3 SH0 or 1 if triggered by internal or SHEN0/1l Both S/H0 & S/H1 are ready.
DS4830 User’s Guide ADACQ[3:0]. Table 7-2 shows the extended acquisition time in terms of core clocks at different ADACQ[3:0] The total acquisition time, ACQ, is two ADC clocks plus the Extended Acquisition Time (ADACQ, as listed in Table 7-2). Figure 7-4 shows the clocking required for one conversion. Table 7-2. Extended Acquisition Time in Terms of Core Clock and Time (s) # of Core Clocks 2 6 14 30 62 126 254 520 ADACQ[3:0] 0 1 2 3 4 5 6 7 ADC STARTUP SAMPLE 1 Time (in s) ADACQ[3:0] 0.2 0.6 1.4 3.
DS4830 User’s Guide location configured in the ALT_LOC[4:0] bits in the ADDATA during ADC configuration (ADST.ADCFG = 1). This buffer is accessed by reading the ADDATA register when ADCFG is set to 0. The data buffer pointed to by ADST.ADIDX [4:0] will be the buffer returned when ADDATA is read. The ADIDX is automatically incremented following a read of ADDATA. This allows repeated reads of ADDATA to return the results from multiple conversions.
DS4830 User’s Guide 7.2 – ADC Register Descriptions The ADC is controlled by ADC SFR registers. The PINSEL register is used to configure pins as analog pin for ADC use. Four of the registers, ADST, ADADDR, ADCN, and ADDATA are used for setup, control, and reading from the ADC. There are few other registers, ETS, ADCG1-4, ADVOFF, and TOEX, which are used to adjust the gains and offsets applied to ADC results. To avoid undesired operations, the user should not write to bits labeled as “Reserved”. 7.2.
DS4830 User’s Guide 7.2.2 – ADC Status Register (ADST) Register Address: M2[06h] Bit 15 14 Name 0 0 Reset r r Access BIT 15:13 12 NAME SH1DAI 11 SH0DAI 10 EX1DAI 9 EX0DAI 8 INTDAI 7 ADDAI 6 ADCONV 5 ADCFG 4:0 ADIDX[4:0] 13 12 11 10 9 8 7 6 5 - SH1DAI SH0DAI EX1DAI EX0DAI INTDAI ADDAI ADCONV ADCFG 4 3 2 1 0 ADIDX[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw rw rw rw rw rw rw DESCRIPTION Reserved.
DS4830 User’s Guide 7.2.3 – PIN Select Register (PINSEL) Register Address: M2 [12h] Bit 15 14 13 12 11 PINSEL.15 PINSEL.14 PINSEL.13 PINSEL.12 PINSEL.11 Name Reset 0 0 0 0 0 Access rw rw rw rw rw s = special, initial value is dependent on trim settings 10 9 8 7 6 5 4 3 2 1 0 PINSEL.10 PINSEL.9 PINSEL.8 PINSEL.7 PINSEL.6 PINSEL.5 PINSEL.4 PINSEL.3 PINSEL.2 PINSEL.1 PINSEL.
DS4830 User’s Guide 6 ADALIGN 5 ADDIFF 4:0 ADCH[4:0] ADC Data Alignment Select. This bit selects the ADC data alignment mode. Setting this bit to ‘1’ returns ADC data left aligned in ADDATA [15:2] with ADDATA[1:0] zero padded. Clearing this bit to ‘0’ returns ADC data in right aligned format in ADDATA[13:0] with ADDATA[15:14] sign-extended by ADDATA[13]. ADC Differential Mode Select. This bit selects the ADC conversion mode. When this bit is set to ‘1’, the ADC conversion is in differential mode.
DS4830 User’s Guide 7.2.6 – Temperature Control Register (TEMPCN) Register Address: M2 [0Bh] The Temperature Control register TEMPCN configures and enables internal die temperature and two external remote diodes temperatures. Internal Temperature, external diode 0 and external diode 1 temperatures have dedicated data buffers 22, 21 and 20 respectively. The DS4830 ADC Controller forces current in the diode and integrates voltage across diode.
DS4830 User’s Guide 7.2.8 – ADC External Temperature Offset Register (TOEX) Register Address: M1 [1Ah] Bit 15 14 13 12 11 Name S S S S 28 Reset s s s s s Access rw rw rw rw rw s = special, initial value is dependent on trim settings 10 27 s rw 9 26 s rw 8 25 s rw 7 24 s rw 6 23 s rw 5 22 s rw 4 21 S rw 3 20 s rw 2 2-1 s rw 1 2-2 s rw 0 2-3 s rw This register contains the temperature offset for the external temperature measurements.
DS4830 User’s Guide 7.3 – ADC Code Examples 7.3.1 – One Sequence of 4 Voltage Conversions for Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15 (Single) PINSEL = 0xC00F; //Configure Pin as ADC Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15(Single) ADCN_bit.ADCONT = 0; //run a single conversion sequence ADST_bit.ADCFG = 1; ADST_bit.
DS4830 User’s Guide while (1) { while (!ADST_bit.ADDAI); //wait for conversions to complete ADST_bit.ADDAI = 0; ADST_bit.
DS4830 User’s Guide SECTION 8 – SAMPLE AND HOLD The DS4830 has two independent, but identical, Sample and Hold differential channels. Sample and Hold 0 (S/H0) is on GP2-GP3 and Sample and Hold 1 (S/H1) is on GP12-GP13. The sample and hold function can be configured for internal or external triggering. Each sample and hold has a dedicated pin for external trigger.
DS4830 User’s Guide Sample Time (min 300nSec) Conversion Time Depends upon ADC Sequencing Pin Discharge, if Enabled SH Sample & Conversion Timings Sample Pulse Internal or External Min 125uSec in Fast Mode or 250uSec in Normal Mode Sample and Hold Sample and Conversion Timings Figure 8-2 – Sample and Hold Conversion Timings 8.1.1.
DS4830 User’s Guide circuit. When the clock select bit CLK_SEL is set to ‘1’, the external clock (CLKIN on the DACPW2 pin) is used for the sample and hold circuit. External Trigger 0 0 Sample Pulse SHEN OUT NonZero Internal Trigger { SHEN OUT when SSC=0 Sampling Pulse depends upon SSC Value 1 Mux INTTRIG_EN Mux SSC Figure 8-3: Sample Pulse The end of the sample and hold sample time is controlled by the Sampling Stop Control bits SSC[3:0] in the SHCN register.
DS4830 User’s Guide Sample Pulse Width with external clock SHEN0/1 or INT_REIG0/1 CLKIN …. …. …. Falling edge (Sample stop) depends upon SSC[3:0] Sample Pulse 300ns min SSC[3:0] = 0 Figure 8-5: Sample Pulse Width with the External Clock As shown in Figure 8-5, the sample pulse width time depends upon the SSC bits value when the external clock is selected (CLK_SEL = 1). 8.1.
DS4830 User’s Guide 8.1.5 – Sample and Hold Data Reading Each sample and hold has defined data buffer locations where the ADC controller writes sample and hold results after the ADC conversion. The data buffer location 23 and 24 are reserved for Sample and Hold 0 and 1 respectively. The ADC controller uses ADCG1 (1.2V full scale) for ADC conversion of the sampled signal of both sample and holds. 8.1.
DS4830 User’s Guide 8.2 – Sample and Hold Register Descriptions The sample and hold has two SFRs. These are Sample and Hold Control Register (SHCN) and Sample and Hold Internal Trigger Enable register (SENR). The SHCN register controls both sample and holds. The SENR controls the internal sample pulse for both sample and holds. The sample and hold SFRs are located in module 2. 8.2.
DS4830 User’s Guide 10 PIN_DIS1 9 PIN_DIS0 8 SH_DUAL 7 6 SH1_ALGN 5 SHDAI1_EN 4 SMP_HLD1 3 CLK_SEL 2 SH0_ALGN 1 SHDAI0_EN 0 SMP_HLD0 125s. During fast mode, the sample and hold conversion priority is increased over voltage channels in the sequence and the voltage conversions will be delayed. When this bit is ‘0’, Sample and Hold 0 acts in the normal mode in which Sample and Hold 0 will get a conversion slot in the ADC sequence every 250s. Pin Discharge Enable 1.
DS4830 User’s Guide 8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR) SENR Register Address: M2[05h] Bit 15 14 13 Name 0 0 0 Reset r r r Access BIT 15:6 5 NAME INT_TRIG_EN1 4 INT_TRIG1 3:2 1 INT_TRIG_EN0 0 INT_TRIG0 12 11 10 9 8 7 6 5 4 3 2 1 0 INT_TRIG_EN1 INT_TRIG1 - - INT_TRIG_EN0 INT_TRIG0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r rw rw r r rw rw DESCRIPTION Reserved. The user should write 0 to these bits.
DS4830 User’s Guide SECTION 9 – QUICK TRIP (FAST COMPARATOR) The DS4830 has 16 8-bit quick trips with 16-input Analog MUX (Figure 9-1). The MUX selects the quick trip analog input from 16 external channels. The quick trip external channels can be configured to operate as eight fully differential inputs or sixteen single-ended inputs. The quick trip monitors all configured quick trip channels in a round robin sequence.
DS4830 User’s Guide By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL). The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick Trip use. Each bit location in this register corresponds to the ADC/Quick Trip input pin. Table 9-1.
DS4830 User’s Guide (channel 7 + differential mode) and 06h (channel 6 + single-ended). See below Table 9-2 for the quick trip list configurations. To scan (See Figure 9-2) these list registers, the QTSTART bits are set to 0 (0000b) and the QTSTOP bits is set to 3 (0011b). Each channel is scanned twice (See Figure 9-2). First the low trip threshold (LT) is scanned and then the high trip threshold (HT). Table 9-2.
DS4830 User’s Guide Channel 5 Channel 6 Channel 7 Channel 6* Channel 5 Channel 6 Channel 7 LT LT LT Channel 6* ………. LT HT LT HT LT HT LT HT ………. HT HT HT LT HT * Note: Channels can be defined multiple times in the list. Figure 9-2: Quick Trip Operation 9.1.3 – Quick Trip Interrupts The DS4830 quick trip has two interrupt flag registers the Low Trip Interrupt Flag Register (LTI) and High Trip interrupt Flag Register (HTI).
DS4830 User’s Guide 9.2 – Quick Trip Register Descriptions The quick trip has 7 SFRs. These are the Quick Trip Control Register (QTCN), Quick Trip List Register (QTLST), Quick Trip Data Register (QTDATA), Low Trip Interrupt Flag Register (LTI), High Trip Interrupt Flag Register (HTI), Low Trip Interrupt Enable Register (LTIE) and High Trip Interrupt Enable Register (HTIE). The QTCN register controls the quick trip operation. The QTLIST register defines the list for the quick trip controller.
DS4830 User’s Guide QTDATA Register map when RW_LST = 0 (in the QTCN Register) Bit 15 14 13 12 11 10 9 Name 0 0 0 0 0 0 0 Reset r r r r r r rw Access BIT 15:10 9:2 NAME QTDATA[9:2] 8 7 6 5 4 3 2 1 LOW or HIGH THRESHOLD 0 - 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw DESCRIPTION Reserved. The user should write these bits to ‘0’. a.
DS4830 User’s Guide 9.2.3 – Low Trip Interrupt Register (LTI) LTI Register Address: M5 [02h] Bit 15 14 13 Name 0 0 0 Reset rw rw rw Access BIT 15:0 NAME IF[15:0] 12 11 10 9 8 7 6 5 4 3 2 1 0 IF[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw DESCRIPTION Low Trip Interrupt Flag. The corresponding bit of the Low Trip Interrupt register is set when a low threshold trip is occurred on a channel list register.
DS4830 User’s Guide 9.2.7 – Quick Trip List Register (QTLST) QTLIST Register Address: M5 [0Ah] Bit Name Reset Access 15 14 13 12 11 10 9 - - - - - - - 8 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r rw rw rw rw rw rw rw rw BIT 15:8 7:4 NAME QTSTART[3:0] 3:0 QTEND[3:0] 7 6 5 4 3 QTSTART3:0] 2 1 0 QTEND[3:0] DESCRIPTION Reserved. The user should write these bits to ‘0’. Quick Trip Configuration Start Address Bits [3:0].
DS4830 User’s Guide SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE 2 The DS4830 provides an I C-compatible master controller that allows the DS4830 to communicate with a slave device. 2 2 The I C master interface can be setup to provide system interrupts after each I C event. 10.1 – Detailed Description 10.1.1 – Description of Master I2C Interface 2 2 The master I C interface uses the MSDA and MSCL pins. These pins are the master I C controller’s connection to the 2 2 SDA and SCL pins of an I C bus.
DS4830 User’s Guide 2 Figure 10-1: I C Clock Generation 2 The master I C controller’s ability to monitor the state of SCL allows the master to operate with slave devices that clock 2 stretch. A slave device may clock stretch, or hold SCL low, while it is busy or processing data. The master I C controller 2 will always release SCL after holding it low for the SCL Low Time duration.
DS4830 User’s Guide Whenever SCL goes low. If the SCL line is low for a period longer than specified in the timeout register, the I2C controller concludes that there is a bus error and will set the I2CTOI flag. 2 For all of these cases, when the I C timeout period is reached, the I2CTOI flag will be set. The setting of I2CTOI can 2 generate an interrupt if enabled.
DS4830 User’s Guide 2 Figure 10-3: Master I C Generated START and STOP 10.1.6 – Generating a STOP 2 To end an I C transfer, a STOP must be transmitted. A STOP is generated by setting the I2CSTOP bit. The master 2 I C controller’s flow when attempting to issue a STOP command is shown in Figure 10-3.
DS4830 User’s Guide 10.1.7 – Transmitting a Slave Address 2 The first byte after an I C start or restart condition is the slave address byte. This byte, which is transmitted by the master, contains seven bits of slave address followed by the R/W bit. The transmission of the slave address begins with writing 7bit slave address + the R/W bit to I2CBUF_M. Figure 10-4 shows the format for slave address 36h in write mode.
DS4830 User’s Guide Transmitting Slave Address Transmitting Byte Receiving Byte Write to I2CBUF_M Write to I2CBUF_M First SCL Rising Edge Generated I2CBUSY=1 I2CBUSY=1 I2CBUSY=1 Receive a Bit into Shift Register MSB first Transmit Shift Register Byte, MSB First Transmit I2CBUF_M[7:0] I2CBUF_M[0] I2CMODE 8 Bits Received? N RECEIVE ACKNOWLEDGE 8 Bits Transmit? Y Receiver Full ? Y RECEIVE ACKNOWLEDGE I2CNACKI = ACKNOWLEDGE I2CTXI=1 I2CBUSY=0 N Y I2CROI=1 N I2CNACKI = ACKNOWLEDGE Load
DS4830 User’s Guide 2 1. If I2CBUF_M is empty, the I C master controller will copy the data from the shift register into I2CBUF_M. The I2CRXI flag will be set to indicate a received byte is ready to be read. The setting of I2CRXI can generate an interrupt if enabled. 2. If I2CBUF_M is full, the data in the shift register cannot be copied into I2CBUF_M. This causes a receive overrun condition. The receive overrun flag, I2CROI, will be set which can generate an interrupt if enabled.
DS4830 User’s Guide 10.1.10 – I2C Master Clock Stretching 2 The Master I C Controller is capable of clock stretching at the end of each transfer cycle. Clock stretching is when SCL is 2 2 held low. If the I C Clock Stretch Enable bit (I2CSTREN) is set to a 1, the I C controller will hold SCL low after the clock 2 2 pulse defined by the I C Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I C controller will hold SCL low after the th 2 th falling edge of the 9 clock pulse.
DS4830 User’s Guide 10.1.12 – Operation as a Slave 2 The DS4830 contains two I C interfaces, the master (MSDA and MSCL) and slave (DS4830 SDA and SCL pins). These are two totally separate blocks within the DS4830. However, both of the blocks are identical. Because of this, it is possible to operate the master as a slave and also operate the slave as a master. 2 To operate the master (MSDA and MSCL) as a slave I C interface, the I2CMST bit in I2CCN_M needs to be set to a 0.
DS4830 User’s Guide 10.2 – I2C Master Controller Register Description 2 Following are the registers that are used to control the I C Master Interface, which is the MSDA and MSCL pins. These 2 registers are used to control the I C master interface if it is operating as either a master or slave. The bit descriptions below detail how to use these registers when operating in master mode. When operating in slave mode, some of the bits 2 2 and registers have different functionality.
DS4830 User’s Guide 2 10.2.2 – I C Master Status Register (I2CST_M) Address: M1[01h] Bit Name Reset Access 15 14 I2CBUS I2CBUSY 13 12 11 10 9 - - I2CSPI I2CSCL I2CROI 8 7 I2CGCI I2CNACKI 6 5 - I2CAMI 4 3 I2CTOI I2CSTRI 2 1 0 I2CRXI I2CTXI I2CSRI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r* r* r r rw r* rw rw rw* r rw rw rw* rw* rw rw * Set by hardware only. BIT NAME DESCRIPTION 2 I C Master Bus Busy.
DS4830 User’s Guide 2 10.2.
DS4830 User’s Guide 2 10.2.5 – I C Master Clock Control Register (I2CCK_M) Address: M1[0Dh] Bit Name Reset Access 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw BIT NAME 15:8 I2CCKH[7:0] 7:0 12 I2CCKH7 I2CCKH6 I2CCKH5 I2CCKH4 I2CCKH3 I2CCKH2 I2CCKH1 I2CCKH0 I2CCKL7 I2CCKL6 I2CCKL5 I2CCKL4 I2CCKL3 I2CCKL2 I2CCKL1 I2CCKL0 DESCRIPTION 2 I C Clock High Period.
DS4830 User’s Guide SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE 2 The DS4830 provides an I C-compatible slave controller that allows the DS4830 to communicate with a host device. This 2 controller can also operate as an SMBUS slave. Also designed into the I C slave controller is the ability to bootload the 2 2 DS4830 with new user Flash memory. The I C slave interface can be setup to provide system interrupts after each I C 2 event. Figure 11-1 shows the basic operation flow of the I C slave controller.
DS4830 User’s Guide 11.1 – Detailed Description 11.1.1 – Default Operation 2 2 The I C slave controller is enabled (I2CCN_S.I2CEN=1) by default. As long as the I C slave controller is enabled, the 2 2 DS4830 I C bootloader can operate. This allows bootloading of blank devices without any setup of the I C slave 2 controller. Prior to the I C slave controller being used for normal data communication, some software setup will be 2 2 required.
DS4830 User’s Guide Receiving Slave Address Transmitting Byte Receiving Byte Detect START I2CSRI=1 I2CBUS=1 I2CBUSY=1 Write to I2CBUF_S Detect 1 st SCL Rising Edge I2CBUSY=1 I2CBUSY=1 Receive Addr[6:0] + R/W N Transmit Shift Register Byte, MSB First 8 Bits Received ? Match I2CSLA_S[7:1] ? N Y 8 Bits Transmit ? Transmit Y I2CACK RECEIVE ACKNOWLEDGE Set I2CMODE According to R/W Receive a Bit, into Shift Register MSB first N Y Receiver Full ? Y I2CROI=1 N I2CNACKI = ACKNOWLEDGE Load
DS4830 User’s Guide th Following the 8 data (least significant bit) being shifted to SDA, the SDA line will be released by the DS4830 slave th 2 controller. This allows the host to signal an ACK or NACK during the 9 clock cycle. The DS4830 I C slave controller th samples the acknowledge bit following the rising 9 SCL rising edge. After the acknowledge bit is sampled, the DS4830 2 I C slave controller will perform the following tasks: 2 Set the I2CST_S.
DS4830 User’s Guide 11.1.8 – Clock Stretching If a slave device cannot receive or transmit another complete byte of data, it may hold SCL low, forcing the master to wait. Data transfer will continue when the slave is ready for another byte of data and releases SCL. 2 The I C slave controller is capable of holding SCL low at the completion of each byte being transferred.
DS4830 User’s Guide 2 2 1. The I C slave controller is in the idle state and there is no communications on the I C bus. The timer should not 2 generate interrupts if the I C slave controller is in the idle state regardless of how long SCL is low. 2 2. The SMBUS mode bit is not set. This ensures the SMBUS timeout functionality does not interfere with normal I C functionality. 3. SCL is high. The timer is inactive whenever SCL is high. The timer resets when it is inactive. 2 2 4.
DS4830 User’s Guide 11.2 – I2C Slave Controller Register Description 2 Following are the registers that are used to control the I C Slave Interface, which is the SDA and SCL pins. These 2 registers are used to control the I C slave interface if it is operating as either a slave or master. The bit descriptions below detail how to use these registers when operating in slave mode. When operating in master mode, some of the bits and 2 2 registers have different functionality.
DS4830 User’s Guide 2 11.2.2 – I C Slave Status Register (I2CST_S) Address: M2[01h] Bit 15 14 I2CBUS I2CBUSY Name 0 0 Reset r* r* Access * Set by hardware only. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI - I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r rw r* rw rw rw* r rw rw rw* rw* rw rw BIT NAME DESCRIPTION 15 I2CBUS 14 I2CBUSY I C Slave Bus Busy.
DS4830 User’s Guide 2 11.2.
DS4830 User’s Guide 2 11.2.5 – I C Slave Data Buffer Register (I2CBUF_S) Address: M2[00h] Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Reset r r r r r r r r Access * Unrestricted read access. This register can be written to only when I2CBUSY = 0. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 rw* rw* rw* rw* rw* rw* rw* rw* BIT NAME DESCRIPTION 15:8 7:0 Reserved D[7:0] Reserved. The user should write 0 to these bits.
DS4830 User’s Guide SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) The DS4830 provides two independent Serial Peripheral Interfaces (SPI) – one defined as SPI Master and SPI Slave. Each SPI module of the DS4830 microcontroller provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system.
DS4830 User’s Guide edge is used to sample the serial shift data. The Clock Phase Select (CKPHA; SPICF.1) bit controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled on the inactive clock edge (clock returning to the idle state). When CKPHA is set to 0, data is sampled on the active clock edge (clock transition to the active state).
DS4830 User’s Guide 12.1.2 – SPI Character Lengths To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable via the Character Length Bit (CHR) in the SPI Configuration Register. These are independently configurable for the master and slave SPI. The CHR bit allows selection of either 8-bit or 16-bit transfers. When CHR is 0, the character length is 8bits; when CHR is set to 1, the character length is 16-bits.
DS4830 User’s Guide 12.2.3 – Write Collision While Busy A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY=1). Since the shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data.
DS4830 User’s Guide 12.4 – SPI Master The DS4830 has the following SPI interface signals. Functional name External pin name MSPIDI: Input to serial shift register (MISO) MDI MSPIDO: Output from serial shift register (MOSI) MDIO MSPICK: Serial shift clock sourced to slave device(s) (SPICK) MCL MSPICS: (Optional) Mode fault detection input if enabled (MODFE=1) (SSEL) MCS 12.4.
DS4830 User’s Guide SPI Master MSPICK MSPICK MSPIDO MSPIDO MSPIDI SPI Master MSPIDI MSPICS CS (Any GPIO) CS (Any GPIO) Mode Fault Enable Mode Fault Disable CS: External Slave Chip Select Note: MSPICS can be used as CS for External Slave Device Figure 12-4: SPI Master Pin Configurations with mode fault enable and disable In master mode, the MSPICS pin of the master defaults to general-purpose I/O pin.
DS4830 User’s Guide 12.4.3 – SPI Master Register Descriptions SPI Master Module has four SFR registers. These are SPICN_M, SPICF_M, SPICK_M and SPIB_M. The SPI control register SPICN_M and SPI configuration register SPICF_M controls and configures the Serial Peripheral Interface respectively. The SPI Clock Register SPICK_M configures SPI Baud rate in Master mode. The SPI Buffer SPIB_M is used in SPI data transfer. SPI Master SFRs are located in Module 5. 12.4.3.
DS4830 User’s Guide 12.4.3.2 – SPI Configuration Register (SPICF_M) SPICF_M Register Address: M5 [13h] Bit 7 6 5 ESPII SAS Name 0 0 0 Reset rw rw r Access 4 3 2 1 0 - - CHR CKPHA CKPOL 0 0 0 0 0 r r rw rw rw BIT 7 NAME ESPII DESCRIPTION SPI Interrupt Enable. Setting this bit to ‘1’ enables the SPI interrupt when MODF, WCOL, ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt. 6 SAS 5:3 2 Reserved CHR 1 CKPHA 0 CKPOL Slave Active Select.
DS4830 User’s Guide 12.5 – SPI Slave Functional name External pin name SSPIDO: Output from serial shift register (MISO) GP6 SSPIDI: Input to serial shift register (MOSI) SDA SSPICK: Serial shift clock from SPI master (SPICK) SCL SSPICS: Slave select input (CS) GP7 12.5.1 – SPI Slave Select The SPI Slave Select SSPICS can be configured to accept either an active low or active high signal via the Slave Active Select Bit (SAS) in the SPI Configuration Register.
DS4830 User’s Guide 12.5.4 – SPI Slave Register Descriptions SPI Slave Module has four SFR registers. These are SPICN_S, SPICF_S, SPICK_S and SPIB_S. The SPI control register SPICN_S and SPI configuration register SPICF_S controls and configures the Serial Peripheral Interface respectively. The SPI Clock Register SPICK_S is not used in SPI Slave mode as SPI clock is driven by SPI Master. The SPI Buffer SPIB_S is used in SPI data transfer. SPI Slave SFRs are located in Module 1. 12.5.4.
DS4830 User’s Guide 12.5.4.2 – SPI Configuration Register (SPICF_S) SPICF_S Register Address: M1 [13h] Bit 7 6 5 ESPII SAS Name 0 0 0 Reset rw rw r Access 4 3 2 1 0 - - CHR CKPHA CKPOL 0 0 0 0 0 r r rw rw rw BIT 7 NAME ESPII DESCRIPTION SPI Interrupt Enable. Setting this bit to ‘1’ enables the SPI interrupt when MODF, WCOL, ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt. 6 SAS 5:3 2 Reserved CHR 1 CKPHA 0 CKPOL Slave Active Select.
DS4830 User’s Guide SECTION 13 – 3-WIRE The DS4830 has proprietary 3-Wire master interface for communication with MAXIM 3-wire laser drivers (which supports MSB first 3-wire protocol). The 3-wire communication mode operates similar to SPI mode. However, in the 3-wire mode, there is one bi-directional I/O instead of separate data in and data out signals. The 3-wire interface consists of the MCS, MDIO and MCL. The 3-Wire Master interface reads data on the falling edge of MCL.
DS4830 User’s Guide 13.1.1.1 – Write Mode (RWN=0) The 3-Wire master generates 16 clock cycles on MCL pin. It outputs 16-bits (MSB first DADDR data) to the MDIO line at the falling edge of the MCL. After completion of 16 clocks, the 3-Wire BUSY flag is cleared and the data transfer complete flag TWI is set to ‘1’ which generates interrupt if enabled. The master closes the transmission by setting the MCS to ‘0’. 13.1.1.2 – Read Mode (RWN=1) The 3-Wire master generates 16 clock cycles at MCL.
DS4830 User’s Guide 13.2 – 3-Wire Register Descriptions The 3-Wire interface is controlled by two SFR registers. These are the 3-Wire Control Register TWR and Data and Address Register DADDR. The TWR register configures and controls 3-Wire interface. The DADDR is used in 3-Wire read and write operation. These registers are located at Module 2. 13.2.
DS4830 User’s Guide SECTION 14 – PWM The DS4830 provides ten independent PWM output pins that can be used to create DC-DC power supply controllers or a Thermoelectric Cooler Controller (TECC). 14.1 – Detailed Description The DS4830 provides 10 independently configurable PWM outputs. The DS4830 PWM controller has 3 SFRs PWMCN, PWMDATA and PWMSYNC for configuration and control of the 10 PWM outputs.
DS4830 User’s Guide READ OR WRITE TO PWMDATA DCYC0 (Ch0) PWMCN.REG_SEL = 00b DUTY CYCLE REGISTER PWMCN.PWM_SEL =n DCYC9 (Ch9) PWMCFG0 (Ch0) PWMCN.REG_SEL = 01b PWM CONFIGURATION PWMCN.PWM_SEL =n PWMCFG9 (Ch9) PWMDLY0 (Ch0) PWMCN.REG_SEL = 1xb DELAY REGISTER PWMCN.PWM_SEL =n PWMDLY9 (Ch9) Note: n = 0 to 9 PWMDATA REGISTER Figure 14-1: Illustration of PWMDATA and PWMCFG SFRs 14.1.2 – PWMSYNC SFR Different channels can be synchronized using the PWMSYNC register.
DS4830 User’s Guide 14.2 – Individual PWM Channel Operation Figure 14-3: Block diagram of one PWM channel. The DS4830 has 10 PWMs which can provide up to 12 bits of resolution on each channel. Each channel can be independently enabled or disabled. Each PWMs is configured using 3 Local Registers (for a total of 30 Local Registers for programming the 10 PWMs) As explained above the PWMCN SFR points to a particular PWM channel. The local registers are then programmed by writing data to the PWMDATA SFR.
DS4830 User’s Guide DCYCn = 128 PWM Output High Time PWM Output Low Time 128 Cycles 384 Cycles PWM Frame = 512 Cycles 9-bit PWM Operation in Normal Mode Figure 14-4: PWM Duty Cycle set to 128 with 9-bits resolution 14.2.2 – PWM Configuration Register (PWMCFGn) This register allows independent configuration of a PWM Channel. Each PWM Channel can be independently disabled or enabled. Each output can have from 7 to 12 bits of resolution and can be inverted.
DS4830 User’s Guide DCYCn = 127 Slot 1 Slot 2 PWM Output High Time PWM Output High Time PWM Output Low Time PWM Output Low Time Slot 3 Slot 4 PWM Output High Time PWM Output High Time PWM Output Low Time Slot 1 PWM Output Low Time 32 Cycles 32 Cycles 31 Cycles 32 Cycles 96 Cycles 96 Cycles 96 Cycles 97 Cycles Next Cycle PWM Frame = 512 Cycles 9 bit PWM Operation in 4 Slot pulse spreading mode Figure 14-5: 9-bit PWM operation in 4-Slot pulse spreading mode 14.2.3.
DS4830 User’s Guide Table 14-2. Slot frequencies for various resolution with different PWM Clocks Resolution No of Slots Clock (MHz) Frame freq (kHz) Slot freq (kHz) Resolution No of Slots Clock (MHz) Frame freq (kHz) Slot freq (kHz) 7 1 10 78.13 78.13 10 1 10 9.77 9.77 10 78.13 10 9.77 39.06 156.25 10 1 20 19.53 19.53 7 4 312.5 10 4 7 1 20 156.25 7 4 20 156.25 625 10 4 20 19.53 78.13 7 1 133 1039.06 1039.06 10 1 133 129.88 129.88 7 4 133 1039.
DS4830 User’s Guide 14.2.4 – Alternate PWM Output Table 14-3 shows the mapping of each PWM Output. The PWM outputs PW0 to PW7 are also multiplexed with the DAC output pins. The DS4830 provides the option to select these alternate locations for PW0 to PW7 outputs if PWM functionality is required along with DAC outputs. When the ALT_LOC is set to ‘1’ during PWM configuration for a PWM output, the PWM output will be available on this alternate pin. See Table 14-3 for details. Table 14-3.
DS4830 User’s Guide 14.2.3.1 – PWM DELAY with PWMSYNC SFR The PWM channels to be synchronized must have the same configurations (Resolution, Pulse Spreading option, Clock source etc.). The Delays on the two channels can be different. After the synchronization, the programmed delay is maintained as shown in Figure 14-7. PWMSYNC = 00h PWMSYNC = 03h PWMSYNC = 00h PWM1 PWM0 Core Clock Figure 14-7: PWM output synchronization with 4 clock delay 14.
DS4830 User’s Guide 3:2 1:0 Reserved REG_SEL[1:0] PWM_SEL REG_SEL Local Register Selected 0 0 Duty Cycle Register PWM Channel 0 (DCYC0) 0 1 PWM Configuration Register PWM Channel 0 (PWMCFG0) 0 2 Delay Setting Register for PWM Channel 0 (PWMDLY0) 1 0 Duty Cycle Register PWM Channel 1 (DCYC1) 1 1 PWM Configuration Register PWM Channel 1 (PWMCFG1) 1 2 Delay Setting Register for PWM Channel 1 (PWMDLY1) 2 0 Duty Cycle Register PWM Channel 2 (DCYC2) 2 1 PWM Configuration Register PWM Channel 2 (PWMCFG2) 2 2 De
DS4830 User’s Guide 14.3.2.1 – Local Register DCYCn BIT 15:12 NAME Reserved 11:0 DCYCn[11:0] PWMCN REG_SEL = 00b PWMDATA[15:0] DCYCn[15:0] DESCRIPTION Reserved. The user should write 0 to these bits. These bits are ignored by the PWM controller. Duty Cycle Register. When REG_SEL[1:0] in the PWMCN SFR is set to 00b, the PWMDATA register points to the Duty Cycle Register of the PWM channel selected by PWM_SEL[3:0] bits in the PWMCN register.
DS4830 User’s Guide 14.3.2.
DS4830 User’s Guide 14.3.2.3 – Local Register PWMDLYn BIT 15:12 NAME Reserved 11:0 PWMDLYn[11:0] PWMCN REG_SEL = 1xb PWMDATA[15:0] PWMDLY[15:0] DESCRIPTION Reserved. The user should not write to these bits. These bits are ignored by the PWM controller. Delay Setting Register. When REG_SEL[1:0] is set to 1xb, the PWMDATA register points to the Delay Setting Register of PWM channel selected by PWM_SEL[3:0] bits in the PWMCN register.
DS4830 User’s Guide 14.4 – PWM Output Code Examples 14.4.
DS4830 User’s Guide SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS 15.1 – Overview The DS4830 provides general-purpose input/output (GPIO) functionality on 31 pins. In addition to the GPIO functionality, each of these pins is multiplexed with at least one other function, which is classified as “Special Function”. Special functions override the GPIO register settings of the port pin when they are enabled.
DS4830 User’s Guide Table 15-1. GPIO Pins and Multiplexed Functions Port Pin Name Index Pin No. Default Special Function Function-1 P0.0 GP12 19 GPIO ADC-S12 P0.1 GP13 20 GPIO ADC-S13 P0.2 GP14 21 GPIO ADC-S14 P0.3 GP15 22 GPIO ADC-S15 P0.4 DACPW0 32 GPIO DAC0 P0.5 DACPW1 33 GPIO DAC1 P0.6 PW8 30 GPIO PW8 P0.7 PW9 29 GPIO PW9 Special function-1 enable PINSEL.12 = 1 & ADDATA.DIFF = 0 PINSEL.13 = 1 & ADDATA.DIFF = 0 PINSEL.14 = 1 & ADDATA.DIFF = 0 PINSEL.
DS4830 User’s Guide Table 15-2.
DS4830 User’s Guide 15.2 – GPIO Port 0 Register Descriptions Port 0 provides eight GPIO pins that are multiplexed with ADC, DAC, Sample and Hold1 and PWM functionality. ADC function is enabled when PINSEL.n is set to ‘1’ (where n = 12 to 15). Single or Differential ADC mode is selected by ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled when DACCFG.n is set to either “10b” or “01b” (where n = 0 or 1). Sample and Hold-1 is enabled when SHCN.
DS4830 User’s Guide 15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0) Bit # 7 6 5 4 Name IE7 IE6 IE5 IE4 Reset 0 0 0 0 Access rw rw rw rw 3 IE3 0 rw 2 IE2 0 rw 1 IE1 0 rw 0 IE0 0 rw These bits are set when a negative edge (IESP0.n = 1) or a positive edge (IESP0.n = 0) is detected on the P0.n pin. Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will remain set until cleared by software or a reset.
DS4830 User’s Guide 15.3.3 – GPIO Input Register for Port 1 (PI1) Bit # 7 6 5 Name PI1_7 PI1_6 PI1_5 Reset s s s Access r r r 4 PI1_4 s r 3 PI1_3 s r 2 PI1_2 s r 1 PI1_1 s r 0 PI1_0 s r PI1 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI1 input register contains valid input data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states applied to the pins.
DS4830 User’s Guide PD2 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is independently controlled by its direction bit. When PD2.n (n = 0 to 7) is set to 1, the pin is an output; data in the PO2.n bit will be driven on the pin. When PD2.n is cleared to 0, the pin is an input, and allows an external signal to drive the pin. Note that each port pin has a weak pull-up circuit when functioning as an input.
DS4830 User’s Guide 15.5 – GPIO Port 6 Register Descriptions Port 6 provides seven GPIO pins that are multiplexed with the test access port (TAP), DAC, Sample trigger input, PWM and ADC. ADC function is enabled when PINSEL.n is set to ‘1’ (where n = 4, 5, 10 or 11). Single or Differential ADC mode is selected by ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled when DACCFG.n is set to either “10b” or “01b” (where n = 2 or 6).
DS4830 User’s Guide 15.5.5 – GPIO Port 6 External Interrupt Flag Register (EIF6) Bit # 7 6 5 4 Name Reserved IE6 IE5 IE4 Reset 0 0 0 0 Access r rw rw rw 3 IE3 0 rw 2 IE2 0 rw 1 IE1 0 rw 0 IE0 0 rw These bits are set when a negative edge (IESP6.n = 1) or a positive edge (IESP6.n = 0) is detected on the P6.n pin. Setting any of the bits to ‘1’ will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will remain set until cleared by software or a reset.
DS4830 User’s Guide SECTION 16 – GENERAL-PURPOSE TIMERS The DS4830 has two identical 16-bit general-purpose timers. Each timer has the following, Two modes - Free synchronous and Compare Three Clock source selection options - Core clock, Peripheral clock and External clock 6 prescalers Interrupt feature in both modes.
DS4830 User’s Guide In compare mode, the timer module begins counting from 0x0000 and when the value in the GTV register matches the value in the General Timer Compare Register (GTC), the GTIF interrupt flag is set to ‘1 ‘ which generates an interrupt if enabled. When the match occurs, the timer reloads the GTV register with 0x0000 at the next timer clock. 16.1.2 – Clock Selection There are three timer clock sources available in each timer module, core clock, peripheral clock and external clock.
DS4830 User’s Guide 16.2 – Timer Register Descriptions Each General Timer module has three independent SFR registers. These are GTCN, GTV and GTC. The General Timer Control Register GTCN controls the timer operation. The General Timer Value Register GTV is the Timer Value register and is incremented every timer clock when enabled. The General Timer Compare Register GTCx is used in the timer compare mode only. Timer 1 and 2 SFRs are located in module 0 and 3 respectively. 16.2.
DS4830 User’s Guide 16.2.2 – General Timer Value Register (GTV) GTV1 Register Address: M0 [06h] GTV2 Register Address: M3 [06h] Bit 15 14 13 Name 0 0 0 Reset r r r Access 12 11 10 9 8 7 6 5 4 3 2 1 0 GTV(1/2) 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r 9 8 7 6 5 4 3 2 1 0 16.2.
DS4830 User’s Guide SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) The DS4830 provides features to allow monitoring its power supply. The Supply Voltage Monitor (SVM) monitors the VDD power supply and can alert the processor through an interrupt if VDD falls below a programmable threshold. The DS4830 provides the following power monitoring features: SVM compares VDD against a programmable threshold from approximately 3.0V to 3.6V.
DS4830 User’s Guide SECTION 18 – HARDWARE MULTIPLIER MODULE The hardware multiplier module can be used by the DS4830 to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
DS4830 User’s Guide 18.3 – Register Output Selection The Hardware Multiplier implements the MC Register Write Select (MCW) control bit so that writing of the result to the MC2:MC0 registers can be blocked to preserve the MC registers (accumulator). When the MCW bit is configured to logic 1, the result for the given operation is not written to the MC registers. When the MCW bit is configured to logic 0, the MC registers are updated with the result of the operation.
DS4830 User’s Guide The specified hardware multiplier operation begins when the final operand(s) is loaded and will complete in a single cycle. The read-only MC1R, MC0R result registers can be accessed in the very next cycle unless accumulation/subtraction with MC2:0 is requested (MCW = 0 and MMAC = 1), in which case, one cycle is required so that stable data can be read. When MCW = 0, the MC2:0 registers always require one wait cycle before the operation result is accessible.
DS4830 User’s Guide 18.5.1 – Multiplier Control Register (MCNT) Bit Name Reset Access 7 6 5 4 3 2 1 0 OF MCW CLD SQU OPCS MSUB MMAC SUS 0 r 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw BIT 7 NAME 6 MCW 5 CLD 4 SQU 3 OPCS 2 MSUB 1 MMAC 0 SUS OF DESCRIPTION Overflow Flag. This bit is set to logic 1 when an overflow occurred for the last operation. This bit can be set for accumulation/subtraction operations or unsigned multiply-negate attempts.
DS4830 User’s Guide 18.5.2 – Multiplier Operand A Register (MA) Bit Name Reset Access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA.15 MA.14 MA.13 MA.12 MA.11 MA.10 MA.9 MA.8 MA.7 MA.6 MA.5 MA.4 MA.3 MA.2 MA.1 MA.0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw Multiplier Operand A: This operand A register is used by the application code to load 16-bit values for multiplier operations. 18.5.
DS4830 User’s Guide 18.6 – Hardware Multiplier Examples The following are code examples of multiplier operations.
DS4830 User’s Guide SECTION 19 – WATCHDOG TIMER 19.1 - Overview The Watchdog Timer is a user programmable clock counter that can serve as a time-base generator, an event timer, or a system supervisor. As can be seen in Figure 19-1 below, the timer is driven by the main system clock and is supplied to a series of dividers. If the watchdog interrupt and the watchdog reset are disabled (WDCN.EWDI = 0 and WDCN.EWT = 0), the watchdog timer and its input clock are disabled.
DS4830 User’s Guide Table 19-1. Watchdog Operating States EWT x 0 0 1 EWDI X 0 1 0 WDIF 0 x 1 1 1 1 1 Actions No interrupt has occurred. Watchdog disable, clock is gated off. Watchdog interrupt has occurred. No interrupt has been generated. Watchdog reset will occur in 512 system clock cycles if RWT is not set or WDIF not cleared. Watchdog interrupt has occurred. Watchdog reset will occur in 512 system clock cycles if RWT is not set or WDIF not cleared. 19.2.
DS4830 User’s Guide BIT 7 NAME DESCRIPTION POR 6 EWDI 5:4 WD[1:0] Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset. This bit can be checked by software following a reset to determine if a power-on/brownout reset occurred. It should always be cleared by software following a reset to ensure that the sources of following resets can be determined correctly.
DS4830 User’s Guide SECTION 20 – TEST ACCESS PORT (TAP) The DS4830 incorporates a Test Access Port (TAP) and TAP controller for communication with a host device across a 4wire synchronous serial interface. The TAP may be used by the DS4830 to support in-system programming and/or incircuit debug. The TAP is compatible with the JTAG IEEE standard 1149 and is formed by four interface signals described below. For detailed information on the TAP and TAP controller, refer to IEEE STD 1149.
DS4830 User’s Guide 20.1 – TAP Controller The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signals. Based on its state transition, the controller provides the clock and control sequence for TAP operation. The performance of the TAP is dependent on the TCK clock frequency. The maximum TCK clock frequency should be limited to 1/8 the system clock frequency. This section provides a brief description of the state machine and its state transitions.
DS4830 User’s Guide 20.2 – TAP State Control The TAP provides an independent serial channel to communicate synchronously with the host system. The TAP state control is achieved through host manipulation of the Test Mode Select (TMS) and Test Clock (TCK) signals. The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state (i.e. Shift-IR or Shift-DR). 20.2.
DS4830 User’s Guide Table 20-3 - Instruction Register (IR2:0) Encodings IR2:0 Instruction Function Serial Data Shift Register Selection 000 Extest No operation Unchanged. Retain previous selection 001 Sample/Preload No operation Unchanged.
DS4830 User’s Guide For the host to establish a specific data communication link, a private instruction must be loaded into the IR2:0 register. Once the instruction is latched in the instruction parallel buffer at the Update-IR state, it is recognized by the TAP controller and the communication channel is established. In-Circuit Debug or In-System Programming commands and data can be exchanged between the host and the DS4830 by operating in the data register portion of the state sequence (i.e. DR-Scan).
DS4830 User’s Guide TCK TMS Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Run-Test/Idle Control State TDI Shift Register Don’t care or undefined Parallel Output Instruction Register Don’t care or undefined New Data Old Data Data Register Don’t care or undefined TDO Enable TDO Figure 20-4: TAP Controller Debug Mode DR-Scan Example 154
DS4830 User’s Guide SECTION 21 – IN-CIRCUIT DEBUG MODE The DS4830 is equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAG-compatible Test Access Port (TAP) as its means of communication between the host and the DS4830. Figure 21-1 shows a block diagram of the in-circuit debugger.
DS4830 User’s Guide DS4830 9 9 0 X X Host Command / Data Input TDI 0 TDO s1 DS4830 Data Output s0 Status Figure 21-2: 10-Bit Word Format Table 21-1: Status Bits s1:s0 Status / Condition Non-Debug. Default condition, Background mode, or debug engine inactive. 00 Debug Idle. Debug engine is ready to receive data from the host (command, data). 01 Debug Busy. Debug engine is busy without valid data (i.e. ROM code execution, trace operations). 10 Debug Valid.
DS4830 User’s Guide Table 21-2. Background Mode Commands Opcode Command Operation 0000-0000 No Operation No operation. (Default state for Debug Shift register). 0000-0001 Read ICDC Read control data from the ICDC. The contents of the ICDC register will be loaded into the Debug Shift Register via the ICDB register for host read. This command requires one follow-on transfer cycle. 0000-0010 Read ICDF Read flags from the ICDF.
DS4830 User’s Guide 21.1.1.1 – Breakpoint 0 Register (BP0) Bit Name Reset Access s = special 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BP0.15 BP0.14 BP0.13 BP0.12 BP0.11 BP0.10 BP0.9 BP0.8 BP0.7 BP0.6 BP0.5 BP0.4 BP0.3 BP0.2 BP0.1 BP0.0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 s s s s S s s s s s s s s s s s The Breakpoint 0 register is accessible only via background mode read/write commands.
DS4830 User’s Guide When REGE = 1: This register serves as one of the two register breakpoints. A break occurs when the destination register address for the executed instruction matches with the specified module and index. The destination module is indicated by the M[3:0] bits and the register within that module is defined by the r[4:0] bits. Bit Name Reset Access s = special 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - r.4 r.3 r.2 r.1 r.0 M.3 M.2 M.1 M.
DS4830 User’s Guide 21.2 – Debug Mode There are two ways to enter the Debug Mode from Background Mode: 1. Issuance of the Debug command directly by the host via the TAP communication port, or 2. Breakpoint matching mechanism. The host can issue the Debug background command to the debug engine. This direct Debug Mode entry is nondeterministic. The response time varies dependent on system conditions when the command is issued.
DS4830 User’s Guide (e.g., Unlock Password) require additional data from the host. Some commands need only to provide an indication of completion to the host, while others (e.g., Read Register Map) need to supply multiple bytes of output data. To accomplish data flow control between the host and ROM, the status bits should be used by the host to assess when the ROM is ready for additional data and/or when the ROM is providing valid data output.
DS4830 User’s Guide Op Code 0010-0101 Command Write data memory 0010-0110 Trace 0010-0111 Return 0010-1000 Unlock password 0010-1001 Read register Operation Write data to a selected data memory location. This command requires four follow-on transfer cycles, two for the memory address and two for the data, starting with the LSB address and ending with the MSB data. The input address must be based memory map when executing from utility ROM, as shown in Figure 2-4.
DS4830 User’s Guide Table 21-4.
DS4830 User’s Guide debug engine. Also, note that the interrupt handler is an essential part of the CPU and a pending interrupt could be granted during single step operation since the IGE bit state present on debug mode entry is restored for the single step. 21.2.4 – Return To terminate the debug mode and return the debug engine to background mode, the host must issue a Return command to the debug engine.
DS4830 User’s Guide 21.3 – In-Circuit Debug Peripheral Registers The following peripheral registers are used to control the in-circuit debug mode of the DS4830. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: ● Name: Symbolic names of bits or bit fields in this register.
DS4830 User’s Guide 21.3.3 – In-Circuit Debug Control Register (ICDC, M2[1Ah]) Bit Name Reset Access r = read, s = special BIT 7 NAME DME 6 5 Reserved REGE 4 3:0 Reserved CMD3:0 7 6 5 4 3 2 1 0 DME - REGE - CMD3 CMD2 CMD1 CMD0 0 0 0 0 0 0 0 0 rs r Rs r rs rs rs rs DESCRIPTION Debug Mode Enable (DME). When this bit is cleared to 0, background mode commands may be executed, but breakpoints are disabled.
DS4830 User’s Guide 21.3.4 – In-Circuit Debug Flag Register (ICDF, M2[1Bh]) Bit Name Reset Access r = read, s = special BIT 7:4 3:2 NAME Reserved PSS[1:0] 1 JTAG_SPE 0 TXC 7 6 5 4 3 2 1 0 - - - - PSS1 PSS0 JTAG_SPE TXC 0 0 0 0 0 0 0 0 r r r r rw rw rw rw DESCRIPTION Reserved. Do not write to these bits. Programming Source Select Bits [1:0].
DS4830 User’s Guide 21.3.7 – In-Circuit Debug Data Register (ICDD, M2[1Eh]) Bit Name Reset Access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICDD.15 ICDD.14 ICDD.13 ICDD.12 ICDD.11 ICDD.10 ICDD.9 ICDD.8 ICDD.7 ICDD.6 ICDD.5 ICDD.4 ICDD.3 ICDD.2 ICDD.1 ICDD.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r This register is used by the debug engine to store data or read count so that ROM code can view that information.
DS4830 User’s Guide SECTION 22 – IN-SYSTEM PROGRAMMING 2 The DS4830 contains an internal bootstrap loader utilizing the JTAG or I C interfaces. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. After each device reset, DS4830 ROM code is executed which determines if bootloader operation is desired. Figure 22-1 provides information on how the DS4830 enters into bootloader operation.
DS4830 User’s Guide If none of the preceding conditions have been met, the DS4830 ROM code will be complete. The DS4830 will then jump to program memory location 0000h and begin normal program execution. 22.1.1 - Password Protection The DS4830 uses a password to protect the contents of the program memory from simple access and viewing. The password resides in the 32 bytes of program memory at byte address 0020h through 003Fh. A valid password is defined as any value that does not contain all 0000h or FFFFh.
DS4830 User’s Guide Table 22-2 JTAG Bootloader Status Bits Bits 1:0 Status Condition 00 Reserved Invalid condition. 01 Reserved Invalid condition 10 Loader-Busy ROM Loader is busy executing code or processing the current command. 11 Loader-Valid ROM Loader is supplying valid output data to the host in current shift operation. 22.1.3 – Entering I2C Bootloader 2 2 The DS4830 also has built-in functionality that allows bootloading over I C.
DS4830 User’s Guide 22.2.1 – JTAG Bootloader Protocol The JTAG port consists of a shift register. As data is clocked into TDI, data will be clocked out of TDO. Each “byte” on the JTAG port is actually 10 bits. The two least significant bits are the status bits described in Table 22-2. The data that is input to the device on the TDI pin should have the two status bits set to 0. The following steps are required for each command. 1) 2) 3) 4) 5) 6) Transmit the Command byte on TDI.
DS4830 User’s Guide 22.3 – Bootloader Commands Commands for the DS4830 loader are grouped into families. All bootloader commands begin with a single command byte. The upper four bits of this command byte define the command family (from 0 to 15), while the lower four bits define the specific command within that family. The loader command families are shown in Table 22-5.
DS4830 User’s Guide 22.3.4 - Command 03h – Password Match Byte 1 Bytes 2 to 33 Byte 34 Byte 35 Command Data In NOP Return Input 03h 32-Byte Password 00h 00h Output X X X 3Eh This command accepts a 32-byte password value, which is matched against the password in program memory from byte address 0020h through 003Fh. If the entered value matches the password in program memory, the password lock bit will be cleared. This command is not password protected. 22.3.
DS4830 User’s Guide 22.3.6 - Command 05h – Get Supported Commands Byte 1 Byte 2 Byte 3 Byte 4 Command NOP Data Out Data Out Input 05h 00h 00h 00h Output X X SupportL SupportH Byte 5 Data Out 00h 00h Byte 6 Data Out 00h 00h Byte 7 Return 00h 3Eh The SupportL (LSB) and SupportH (MSB) bytes form a 16-bit value that indicates which command families the bootloader supports. If bit 0 is set to 1, it indicates that Family 0 is supported. If bit 1 is set to 1, it indicates that Family 1 is supported.
DS4830 User’s Guide 22.3.11 - Command 10h – Load Code Byte 1 Byte 2 Byte 3 Input Output Command 10h X Data In Length X Data In AddressL X Byte 4 Data In AddressH X (Length) Bytes Data In Data to load X Byte Length+5 NOP 00h X Byte Length+6 Return 00h 3Eh This command programs (Length) bytes of data into the program flash starting at byte address (AddressH:AddressL). The bootloader writes one 16-bit word to flash at a time.
DS4830 User’s Guide 22.3.14 - Command 21h – Dump Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 5 Byte 6 Command 21h X Data In 2 X Data In AddrL X Data In AddrH X Data In LengthL X Data In LengthH X NOP 00h X Length Bytes Data Out 00h Memory Byte Length+7 Return 00h 3Eh This command returns the contents of the SRAM memory. The memory dump begins at byte address AddrH:AddrL and will contain LengthH:LengthL bytes. This command is password protected. 22.3.
DS4830 User’s Guide This command operates in the same manner as the Load Data command, except that instead of writing the input data into SRAM, it verifies that the input data matches the data already in data space. If the data does not match, the status code is set to reflect this failure. This command is password protected. 22.3.
DS4830 User’s Guide SECTION 23 – PROGRAMMING The following section provides a programming overview of the DS4830. For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide. 23.1 – Addressing Modes The instruction set for the DS4830 provides three different addressing modes: direct, indirect and immediate.
DS4830 User’s Guide 23.3.1 – Loading an 8-bit register with an immediate value Any writeable 8-bit register with a sub-index from 0h to 7h within its module can be loaded with an immediate value in a single cycle using the MOVE instruction. move AP, #05h ; load accumulator pointer register with 5 hex Writeable 8-bit registers with sub-indexes 8h and higher can be loaded with an immediate value using MOVE as well, but an additional cycle is required to set the prefix value for the destination.
DS4830 User’s Guide 16-bit destination concatenation(8-bit source, 8-bit source) Two 8-bit source registers can be concatenated and stored into a 16-bit destination by using the prefix register to hold the high order byte for the concatenated transfer. An additional cycle may be required if either source byte register index is greater than 0Fh.
DS4830 User’s Guide As with other instructions, prefixing is required to select destination registers beyond index 07h. The MOVE instruction may also be used to transfer any one of the lowest 8 bits from a register source or any bit of the active accumulator (Acc) to the Carry flag. There is no restriction on the source register module for the ‘MOVE C, src.bit’ instruction. move C, IIR.3 move C, Acc.7 ; copy IIR.3 to Carry ; copy Acc.
DS4830 User’s Guide MOVE Acc, Acc XCHN XCH (Recirculation of active accumulator contents) (Exchange nibbles within each byte of active accumulator) (Exchange active accumulator bytes) The active accumulator may not be the source in any instruction where it is also the implicit destination. There is an additional notation that can be used to refer to the active accumulator for the instruction “MOVE dst, Acc”.
DS4830 User’s Guide 23.5.3 – ALU operations using the active accumulator and a source The following arithmetic and logical operations can use any register or immediate value as a source. The active accumulator Acc is always used as the second operand and the implicit destination. Also, Acc may not be used as the source for any of these operations.
DS4830 User’s Guide Since the Sign flag is a dynamic reflection of the high bit of the active accumulator, any instruction that changes the value in the active accumulator can potentially change the value of the Sign flag. Also, any instruction that changes which accumulator is the active one (including AP auto-increment/decrement) can also change the Sign flag. The following operation uses the Sign flag: JUMP S, src ; Jump if Sign flag is set 23.6.2 - Zero Flag The Zero flag (PSF.
DS4830 User’s Guide MOVE Acc., C AND Acc. OR Acc. XOR Acc. JUMP C, src JUMP NC, src (Set selected active accumulator bit to Carry) (Carry = Carry AND selected active accumulator bit) (Carry = Carry OR selected active accumulator bit) (Carry = Carry XOR selected active accumulator bit) (Jump if Carry flag is set) (Jump if Carry flag is cleared) 23.6.5 - Overflow Flag The Overflow flag (PSF.
DS4830 User’s Guide 23.7.3 - Conditional jumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command.
DS4830 User’s Guide move LC[1], #10h ... LoopTop: call LoopSub ... djnz LC[1], LC[0] ; loop 16 times ; loop address not relative to djnz LC[n],src ; decrement LC[1] and jump if nonzero If opting to preload the loop address to an internal 16-bit register, the most time and code efficient means is by performing the load in the instruction just prior to the top of the loop: move LC[1], #10h move LC[0], IP LoopTop: ...
DS4830 User’s Guide To support high priority interrupts while servicing another interrupt source, the IMR register may be used to create a userdefined prioritization. The IMR mask register should not be utilized when the highest priority interrupt is being serviced because the highest priority interrupt should never be interrupted. This is default condition when a hardware branch is made the Interrupt Vector address (INS is set to 1 by hardware and all other interrupt sources are blocked).
DS4830 User’s Guide add @SP-add @SP-add @SP-- ; sum the last three words pushed onto the stack ; with Acc, disregarding overflow The stack pointer SP can be set explicitly. For a DS4830, which has a stack depth of 16 words, only the lowest four bits are used and setting SP to 0Fh will return it to its reset state. Since the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a single location.
DS4830 User’s Guide bit that is utilized only for word mode data pointer access). Switching from byte to word access mode or vice versa does not alter the data pointer contents. Therefore, it is important to maintain the consistency of data pointer address value within the given access mode.
DS4830 User’s Guide SECTION 24 – INSTRUCTION SET Table 24-1. Instruction Set Summary DATA TRANSFER BRANCHING MATH BIT OPERATIONS LOGICAL OPERATIONS Mnemonic AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src.
DS4830 User’s Guide Note 2: Only module 8 and modules 0-5 are supported by these single-cycle bit operations. Potentially affects C or E if PSF register is the destination. Potentially affects S and/or Z if AP or APC is the destination. Note 3: The terms Acc and A[AP] can be used interchangeably to denote the active accumulator. Note 4: Any index represented by or found inside [ ] brackets is considered variable, but required.
DS4830 User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source field is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
DS4830 User’s Guide {L/S}CALL src {Long/Short} Call to subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL. Using the optional ‘L’ prefix (i.e.
DS4830 User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
DS4830 User’s Guide {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) register. The DJNZ LC[n], src instruction decrements the LC[n] loop counter and branches to the address defined by src if the decremented counter has not reached 0000h.
DS4830 User’s Guide {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional ‘L’ prefix (i.e.
DS4830 User’s Guide {L/S} JUMP C / {L/S} JUMP NC, src {L/S} JUMP Z / {L/S} JUMP NZ, src {L/S} JUMP E / {L/S} JUMP NE, src {L/S} JUMP S, src Conditional {Long/Short} Jump on Status Flag Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
DS4830 User’s Guide JUMP NZ Operation: Encoding: Example(s): JUMP E Operation: Encoding: Example(s): Z=0: IP IP + src (relative) –or— src (absolute) Z=1: IP IP + 1 15 f101 0 1100 ssss JUMP NZ, label1 ssss ; Z=1, branch not taken E=1: IP IP + src (relative) –or— src (absolute) E=0: IP IP + 1 15 0011 0 1100 ssss JUMP E, label1 ssss ; E=1, branch taken Special Notes: The src specifier must be immediate data.
DS4830 User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination specifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16bit (word) data, the rules governing data transfer are also explained below in the encoding section.
DS4830 User’s Guide MOVE dst, src Destination Specifier Codes NUL dst Bit Encoding ddd dddd 111 0110 MN[n] AP APC PSF IC IMR A[n] Acc PFX[n] @++SP SP IV LC[n] @BP[Offs] @BP[++Offs] @BP[--Offs] OFFS DPC GR GRL BP @DP[n] @++DP[n] @--DP[n] DP[n] nnn 0NNN 000 1000 001 1000 100 1000 101 1000 110 1000 nnn 1001 000 1010 nnn 1011 000 1101 001 1101 010 1101 11n 1101 000 1110 001 1110 010 1110 011 1110 100 1110 101 1110 110 1110 111 1110 n00 1111 n01 1111 n10 1111 n11 1111 dst (continued) Width 16 or 8 8/16 8/
DS4830 User’s Guide Example(s): ; A[0] A[3] ; DP[0] #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h ; DP[0] #0080h (PFX[0] register not needed) MOVE A[0], A[3] MOVE DP[0], #110h MOVE DP[0], #80h Special Notes: Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing assembly source code
DS4830 User’s Guide MOVE C, Acc. Move Accumulator bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flag: C Operation: C Acc. Encoding: 15 1110 0 1010 bbbb Example(s): 1010 ; Acc = 01C0h, C=0 ; C =1 MOVE C, Acc.8 MOVE C, src. Move bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified source bit src.. Status Flag: C Operation: C src.
DS4830 User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flags: C1 Operation: C1 Encoding: 15 1101 0 1010 0001 Example(s): 1010 ;C=0 ;C1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF) Operation: dst. 0 Encoding: 15 1ddd 0 dddd 0bbb Example(s): MOVE M0[0].1, #0 MOVE M0[0].
DS4830 User’s Guide NEG Negate Accumulator Description: Performs a negation (two’s complement) of the active accumulator and returns the result back to the active accumulator. Status Flags: S, Z Operation: Acc ~Acc + 1 Encoding: 15 1000 0 1010 1001 Example(s): 1010 ; Acc = FEEDh, S=1, Z=0 ; Acc = 0113h, S=0, Z=0 NEG OR src Logical OR Description: Performs a logical-OR between the active accumulator (Acc or A[AP]) and the specified src data.
DS4830 User’s Guide POP dst Pop Word from the Stack Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP).
DS4830 User’s Guide Operation: SP ++SP Encoding: 15 f000 Example(s): 0 1101 ssss ssss PUSH GR PUSH #40h ; GR=0F3Fh Stack Data: xxxxh 0040h 0F3Fh xxxxh xxxxh SP (after PUSH #40h) SP (after PUSH GR) SP (initial) RET Return from subroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). The decremented SP is saved as the new stack pointer (SP).
DS4830 User’s Guide RET C / RET NC RET Z / RET NZ RET S Conditional Return on Status Flag Description: Performs conditional return (RET) based upon the state of a specific processor status flag. RET C returns if the Carry flag is set while RET NC returns if the Carry flag is clear. RET Z returns if the Zero flag is set while RET NZ returns if the Zero flag is clear. RET S returns if the Sign flag is set. See RET for additional information on the return operation.
DS4830 User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
DS4830 User’s Guide RETI Z Operation: Encoding: Example(s): RETI NZ Operation: Encoding: Example(s): RETI S Operation: Encoding: Example(s): Z=1: IP @SP-INS 0 Z=0: IP IP + 1 15 1001 0 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur Z=0: IP @SP-INS 0 Z=1: IP IP + 1 15 1101 0 1100 1000 RETI NZ 1101 ; Z=0, return from interrupt (RETI) is performed S=1: IP @SP-INS 0 S=0: IP IP + 1 15 1100 RETI S 0 1100 1000 1101 ; S=0, return from interrupt (RETI) d
DS4830 User’s Guide RL / RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1] Acc.[14:0]; Acc.0 Acc.
DS4830 User’s Guide RR / RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0] Acc.[15:1]; Acc.15 Acc.
DS4830 User’s Guide SLA / SLA2 / SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a ‘0’ is shifted into the lsb and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
DS4830 User’s Guide SR SRA / SRA2 / SRA4 Shift Accumulator Right Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times respectively for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
DS4830 User’s Guide SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag 0 Carry Flag Acc.[13:0] Acc.[15:2] Acc.[15:14] Acc.15 C Acc.1 Encoding: 15 1000 0 1010 1110 Example(s): ; Acc = 0003h, C=0, Z=0 ; Acc = 0000h, C=1, Z=1 SRA2 SRA4 Operation: 1010 15 Active Accumulator (Acc) Acc.[11:0] Acc.[15:4] Acc.[15:12] Acc.15 C Acc.
DS4830 User’s Guide SUB / SUBB src Subtract / Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator. The SUBB additionally subtracts the borrow (Carry Flag) which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
DS4830 User’s Guide XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] Acc.[7:0] Acc.[7:0] Acc.[15:8] Encoding: 15 1000 0 1010 1000 Example(s): 1010 ; Acc = 2345h ; Acc = 4523h XCH XCHN Exchange Accumulator Nibbles Description: Status Flags: Exchanges the upper and lower nibbles in the active accumulator byte(s). S Operation: Acc.[7:4] Acc.[3:0] Acc.[3:0] Acc.[7:4] Acc.[15:12] Acc.
DS4830 User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
DS4830 User’s Guide SECTION 25 – UTILITY ROM 25.1 – Overview The DS4830 utility ROM includes routines that provide the following functions to application software: In-application programming routines for flash memory (program, erase, mass erase) Single word/byte copy and buffer copy routines for lookup tables in flash To provide backwards compatibility among different versions of the utility ROM, a function address table is included that contains the entry points for all user-callable functions.
DS4830 User’s Guide 25.2 – In-Application Programming Functions 25.2.1 – UROM_flashWrite Function UROM_flashWrite Summary Programs a single word of flash memory Inputs Outputs A[0]: Word address in program flash memory to write. A[1]: Value to write to flash memory. Carry: Set on error and cleared on success Destroys PSF, LC[1] Notes: This function uses two stack levels to save and restore values. If the watchdog reset function is active, it should be disabled before calling this function.
DS4830 User’s Guide 25.3 – Data Transfer Functions The DS4830 cannot access data from the same memory segment that is currently being used for instructions. For example, when instructions are executing from FLASH, data in FLASH cannot be accessed. The following utility ROM functions can be used to transfer data from one memory segment to another. For example, if data in FLASH needs to be copied to SRAM, one of these ROM functions can be called to do this transfer.
DS4830 User’s Guide 25.3.1 – UROM_moveDP0 Function UROM_moveDP0 Summary Reads the byte/word value pointed to by DP[0]. Inputs DP[0]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. Destroys None Notes: Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 25-1.
DS4830 User’s Guide 25.3.4 – UROM_moveDP1 Function UROM_moveDP1 Summary Reads the byte/word value pointed to by DP[1]. Inputs DP[1]: Address to read data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. Destroys None Notes: Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 25-1.
DS4830 User’s Guide 25.3.7 – UROM_moveBP Function UROM_moveBP Summary Reads the byte/word value pointed to by BP[OFFS]. Inputs BP[OFFS]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. Destroys None. Notes: Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode.
DS4830 User’s Guide 25.3.10 – UROM_copyBuffer Function UROM_copyBuffer Summary Inputs Outputs LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS]. DP[0]: Starting address to copy from. BP[OFFS]: Starting address to copy to. LC[0]: Number of bytes/words to copy. OFFS is incremented by LC[0]. DP[0] is incremented by LC[0]. Destroys LC[0] Notes: This function can be used to copy from program flash to data RAM, or from one part of data RAM to another.
DS4830 User’s Guide 25.4 – Utility ROM Examples 25.4.
