Datasheet

Figure 4. SPI Master Communications Timing Diagram
Figure 5. SPI Slave Communications Timing Diagram
MSPICS
(SAS = 0)
MSPICK
CKPOL/CKPHA
MSPICK
CKPOL/CKPHA
1/0
0/1
1/1
0/0
1/0
0/1
1/1
0/0
MSPIDO
MSPIDI
LSB
LSB
SHIFT SAMPLE SHIFT SAMPLE
t
MSPICK
t
MCH
t
MOH
t
MIS
t
MOV
t
SPI_RF
t
MLH
t
MIH
t
MCL
MSB MSB-1
MSB MSB-1
SHIFT SAMPLE SHIFT SAMPLE
SSPICS
(SAS = 1)
SSPIDI
SSPIDO
t
SSE
t
SSPICK
t
SCH
t
SCL
t
SIS
t
SOV
t
SLH
t
SSH
t
SD
t
SPI_RF
t
SIH
MSB MSB-1
MSB MSB-1
LSB
LSB
SSPICK
CKPOL/CKPHA
SSPICK
CKPOL/CKPHA
1/0
0/1
1/1
0/0
1/0
0/1
1/1
0/0
DS4830A Optical Microcontroller
www.maximintegrated.com
Maxim Integrated │ 10
Timing Diagrams (continued)