Datasheet

Note: Bypass V
DD
, REG274, and REG18 each with 1µF X5R and 10nF capacitors to ground. All input-only pins and open-drain out-
puts are high impedance after V
DD
exceeds V
BO
and prior to code execution. Except for pins having DAC functions, pins configured
as GPIO have a weak internal pullup at power-up. See the Selectable Functions table for more information.
PIN NAME
INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
STATE
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION)
PORT
32 DACPW0 Digital Push-Pull
High
Impedance
DAC0, FS
= REFINA
or Internal
Reference
PWM0 — — P0.4
33 DACPW1 Digital Push-Pull
High
Impedance
DAC1, FS
= REFINA
or Internal
Reference
PWM1 — — P0.5
34 DACPW2 Digital Push-Pull
High
Impedance
DAC2, FS
= REFINA
or Internal
Reference
PWM2 CLKIN — P6.5
35 DACPW3 Digital
Push-Pull,
Strong
High
Impedance
DAC3, FS
= REFINA
or Internal
Reference
PWM3 — — P1.5
36 DACPW4 Digital Push-Pull
High
Impedance
DAC4, FS
= REFINB
or Internal
Reference
PWM4
I
2
C
MSDA-
ALT
— P1.6
37 DACPW5 Digital Push-Pull
High
Impedance
DAC5, FS
= REFINB
or Internal
Reference
PWM5
I
2
C
MSCL-
ALT
— P1.7
38 DACPW6 Digital
Push-Pull,
Strong
High
Impedance
DAC6, FS
= REFINB
or Internal
Reference
PWM6 — — P6.6
39 REFINB
Reference, ADC/
Digital Input
Push-Pull 55µA Pullup
ADC-
REFINB
— — — P1.4
40 DACPW7 Digital Push-Pull
High
Impedance
DAC7, FS
= REFINB
or Internal
Reference
PWM7 — — P2.7
— EP
Exposed Pad
(Connect to GND)
— GND — — — — —
DS4830A Optical Microcontroller
www.maximintegrated.com
Maxim Integrated │ 15
Pin Description (continued)