Datasheet

Programming
The microcontroller’s flash memory can be programmed
by one of two methods: in-system programming and in-
application programming. These provide great flexibility in
system design as well as reduce the life-cycle cost of the
embedded system. Programming can be password pro-
tected to prevent unauthorized access to code memory.
In-System Programming
An internal bootstrap loader allows the device to be pro-
grammed over the JTAG or I
2
C compatible interfaces.
As a result, system software can be upgraded in-system,
eliminating the need for a costly hardware retrofit when
software updates are required.
The programming source select (PSS) bits in the ICDF
register determine which interface is used for boot loading
operation. The device supports JTAG and I
2
C as an inter-
face corresponding to 00 and 01 bits of PSS, respectively
as shown in Figure 7.
In-Application Programming
The in-application programming feature allows the micro-
controller to modify its own flash program memory. This
allows on-the-fly software updates in mission-critical
applications that cannot afford downtime. Alternatively, it
allows the application to develop custom loader software
that can operate under the control of the application soft-
ware. The utility ROM contains firmware-accessible flash
programming functions that erase and program flash
memory. These functions are described in detail in the
DS4830A User’s Guide.
Register Set
Sets of registers control most device functions. These
registers provide a working space for memory opera-
tions as well as configuring and addressing periph-
eral registers on the device. Registers are divided
into two major types: system registers (special pur-
pose registers, or SPRs) and peripheral registers (spe-
cial function registers, or SFRs). The system registers
includes the ALU, accumulator registers, data point-
ers, interrupt vectors and control, and stack pointer.
Figure 7. In-System Programming
DS4830A Optical Microcontroller
www.maximintegrated.com
Maxim Integrated │ 20
ANY DEVICE
RESET OCCURS
RESET DEVICE.
BEGIN BOOT ROM CODE
EXECUTION AT 8000h.
WAIT FOR 320 SYSTEM
CYCLES (32µs). RESET I
2
C.
SET PWL BIT.
SET ROD BIT.
BOOTLOADER
SET PSS[1:0] = 01
ROM CODE ENABLES
SLAVE I
2
C INTERFACE:
ADDRESS IS 36h.
IS JTAG_SPE BIT SET?
NO
YES
SET USING JTAG PROGRAMMER,
FOLLOWED BY RESET OF DEVICE.
WAITS FOR EXIT LOADER
COMMAND FROM HOST
SET BY WRITING F0h TO
I
2
C SLAVE 34h.
JUMP TO USER CODE
(FLASH) AT 0000h.
IS I2C_SPE BIT SET?
NO
YES