Datasheet

The peripheral registers define additional functionality
and the functionality is broken up into discrete modules.
Both the system registers and the peripheral registers are
described in detail in the DS4830A User’s Guide.
System Timing
The device generates its 10MHz instruction clock (MOSC)
and 20MHz peripheral clock internally. On power-up,
oscillator’s output (which cannot be accessed externally)
is disabled until V
DD
rises above V
BO
. Once this threshold
is reached, the output is enabled after approximately 1ms
(t
SU:MOSC
), clocking the device as shown in Figure 8.
System Reset
The device features several sources that can be used
to reset the DS4830A. The DAC and PWM outputs are
maintained during execution of all resets except POR.
Power-On Reset
An internal power-on reset (POR) circuit is used to enhance
system reliability. This circuit forces the device to perform a
POR whenever a rising voltage on V
DD
climbs above V
BO
.
When this happens the following events occur:
● All registers and circuits enter their reset state.
● The POR flag (WDCN.7) is set to indicate the source
of the reset.
● Code execution begins at location 8000h when the
reset condition is released.
Brownout Detect/Reset
The device features a brownout detect/reset function.
Whenever the power monitor detects a brown-out condi-
tion (when V
DD
< V
BO
), it immediately issues a reset and
stays in that state as long as V
DD
remains below V
BO
.
Once V
DD
voltage rises above V
BO
, the device waits
for t
SU:MOSC
before returning to normal operation, also
referred to as CPU state. If a brownout occurs during this
t
SU:MOSC,
the device again goes back to the brownout
state. Otherwise, it enters into CPU state. In CPU state,
the brownout detector is also enabled.
On power-up, the device always enters brownout state
first and then follows the above sequence. The reset
issued by brownout is same as POR. Any action per-
formed after POR also happens on brownout reset. All
the registers that are cleared on POR are also cleared on
brownout reset.
External Reset
Asserting the RST pin low causes the device to enter the
reset state. Execution resumes at location 8000h after
RST is released.
Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution. The
watchdog timer is a hardware timer designed to be peri-
odically reset by the application software. If the software
operates correctly, the timer is reset before it reaches its
maximum count. However, if undesirable code execution
prevents a reset of the watchdog timer, the timer reaches
its maximum count and resets the processor.
The watchdog timer is controlled through 2 bits in the
WDCN register (WDCN[5:4] : WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
ranging from 2
12
to 2
21
system clock (MOSC) periods
(0.410ms to 0.210s). The watchdog interrupt occurs at
the end of this timeout period, which is 512 MOSC clock
periods, or approximately 50µs, before the reset. The
reset generated by the watchdog timer lasts for 4 system
clock cycles, which is 0.4µs. Software can determine if a
reset is caused by a watchdog timeout by checking the
watchdog timer reset flag (WTRF) in the WDCN register.
Figure 8. System Timing
t
SU:MOSC
= ~1ms
CORE
CLOCK
V
DD
V
BO
DS4830A Optical Microcontroller
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