Datasheet

Execution resumes at location 8000h following a watch-
dog timer reset. The watchdog reset has the same effect
as the external reset as far as the reset values of all reg-
isters are concerned.
Internal System Reset
The host can issue an I
2
C command (BBh) to reset the
communicating device. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1). This
reset has the same effect as the external reset as far as
the reset values of all registers are concerned.
Software Reset
The device UROM provides option to soft reset through
the application program. The application program can
jump to UROM code, which generates the internal sys-
tem reset. This reset has the same effect as the internal
system reset.
Further information regarding various resets can be found
in the DS4830A User’s Guide.
Programmable Timer
The device features two general-purpose programmable
timers. Various timing loops can be implemented using
the timers. The timer can be used in two modes: free-
running mode and compare mode. The functionality of the
timers can be accessed through three SFRs for each of
the general purpose timers. GTCN is the general control
register, GTV is the timer value register and GTC is the
timer compare register.
The timer SFRs are accessed in Module 0 and 3. Detailed
information regarding the timer block can be found in the
DS4830A User’s Guide.
Hardware Multiplier
The hardware multiplier (a multiply-accumulate, or MAC
module) is a very powerful tool, especially for applications
that require heavy calculations. This multiplier is capable
of executing the multiply, multiply-negate, multiply-accu-
mulate, multiply-subtract operation for signed or unsigned
operands in a single machine cycle. The MAC module
uses 10 SFRs, mapped as register 0h–05h, 07h–09h and
0Eh in Module M3.
System Interrupts
Multiple interrupt sources are available to respond to
internal and external events. The microcontroller archi-
tecture uses a single interrupt vector (IV) and single inter-
rupt-service routine (ISR) design. For maximum flexibility,
interrupts can be enabled globally, individually, or by mod-
ule. When an interrupt condition occurs, its individual flag
is set, even if the interrupt source is disabled at the local,
module, or global level. Interrupt flags must be cleared
within the firmware-interrupt routine to avoid repeated
interrupts from the same source. Application software
must ensure a delay between the write to the flag and the
RETI instruction to allow time for the interrupt hardware
to remove the internal interrupt condition. Asynchronous
interrupt flags require a one-instruction delay and syn-
chronous interrupt flags require a two-instruction delay.
When an enabled interrupt is detected, execution jumps
to a user-programmable interrupt vector location. The IV
register defaults to 0000h on reset or power-up, so if it is
not changed to a different address, application firmware
must determine whether a jump to 0000h came from a
RST or interrupt source.
Once control has been transferred to the ISR, the inter-
rupt identification register (IIR) can be used to determine
which module was the source of the interrupt. In addition
to IIR, MIIR registers are implemented to indicate which
particular function under a peripheral module has caused
the interrupt. The device contains six peripheral modules,
M0 to M5. An MIIR register is implemented in modules
M1, M4, and M5. The MIIRs are 16-bit read only registers
and all of them default to all zero on system reset. Once
the module that causes the interrupt is singled out, it
can then be interrogated for the specific interrupt source
and software can take appropriate action. Interrupts are
evaluated by application code allowing the definition of
a unique interrupt priority scheme for each application.
Interrupt sources are available from the watchdog timer,
the ADC (including sample/holds and internal tempera-
ture), fast comparators, the programmable timers, SVM,
the I
2
C-compatible master and slave interface, 3-wire,
master and slave SPI, software interrupts, as well as all
GPIO pins.
I/O Port
The device allows for most inputs and outputs to func-
tion as general purpose input and/or output pins. There
are four ports: P0, P1, P2, and P6. Note that there is no
port pin corresponding to P6.7. The 7th bit of port 6 is
nonfunctional in all SFRs. Each pin is multiplexed with at
least one special function, such as interrupts, ADC, DAC,
PWM, or JTAG pins etc.
The GPIO pins have Schmitt trigger receivers and full
CMOS output drivers, and can support alternate functions.
The ports can be accessed through SFRs (PO[0,1,2,6],
DS4830A Optical Microcontroller
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