Datasheet

PI[0,1,2,6], PD[0,1,2,6], EIE[0,1,2,6], EIF[0,1,2,6], and
EIES[0,1,2,6]) in Modules 0 and 1 and each pin can be
individually configured. The pin is either high impedance
or a weak pullup when defined as an input, dependent on
the state of the corresponding bit in the output register.
In addition, each pin can function as an external interrupt
with individual enable, flag and active edge selection,
when programmed as input.
The GPIO pins also having DAC function are by default
high impedance. The I/O port SFRs are accessed in
Module 0 and 1. Detailed information regarding the GPIO
block can be found in the DS4830A User’s Guide.
DAC Outputs
The device provides eight 12-bit DAC outputs with mul-
tiple reference options. An internal 2.5V reference is pro-
vided. There are also two selectable external references.
REFINA pin can be selected as the full-scale reference
for DAC0 to DAC3. REFINB pin can be selected as the
full-scale reference for DAC4 to DAC7. The external
reference can be between 1.0V to 2.5V. The DAC out-
puts are voltage buffered. Each DAC can be individually
disabled and put into a low power power-down mode
using DACCFG.
The DAC SFRs are accessed in Module 4. Detailed
information regarding the DAC block can be found in the
DS4830A User’s Guide.
Analog-to-Digital Converter, Sample/Hold
The analog-to-digital converter (ADC) controller is the
digital interface block between the CPU and the ADC. It
provides all the necessary controls to the ADC and the
CPU interface. The ADC uses a set of SFRs for configur-
ing the ADC in desired mode of operation.
The device contains a 13-bit ADC with an input mux, as
shown in Figure 9. The mux selects the ADC input from
16 single-ended or eight differential inputs. Additionally,
the channels can be configured to convert internal
temperature, V
DD
, internal reference or REFINA/B. Two
channels can be programmed to be sample/hold inputs.
The internal channel is used exclusively to measure the
die temperature. The SFR registers control the ADC.
ADC
When used in voltage input mode, the voltage applied on
the corresponding channel (differential or single-ended)
is converted to a digital readout. The ADC can be set up
to continuously poll selected input channels (continuous-
sequence mode) or run a short burst of conversions
and enter a shut down mode to conserve power (single-
sequence mode).
In voltage mode there are four full-scale values that
can be programmed. These values can be trimmed by
modifying the associated gain registers (ADCG1, ADCG2,
ADCG3, and ADCG4). By default these are set to 1.2V,
0.6V, 2.4V, and 6.55V full scale.
The ADC clock (ADCCLK) is derived from the system
clock with division ratio defined by the ADC control reg-
ister. The ADC sampling rate is approximately 40ksps for
the fastest ADC clock (Core Clk/8). The device provides
eight different ADC clock configurations to set differ-
ent ADC clock setting. Refer to the ADC section of the
DS4830A User’s Guide for different ADC clock settings.
In applications where extending the acquisition time is
desired, the sample can be acquired over a prolonged
period determined by the ADC control register.
Each ADC channel can have its own configuration, such
as differential mode select, data alignment select, acquisi-
tion extension enable and ADC gain select, etc. The ADC
also has 24 (0 to 23) 16-bit data buffers for conversion
result storage. The ADC data available interrupt flag
(ADDAI) can be configured to trigger an interrupt following
a predetermined number of samples. Once set, ADDAI
can be cleared by software or at the start of a conversion
process.
The ADC controller provides options to average the ADC
results of individual channel. The device provides 1, 4, 8,
and 16 samples averaging configurations for each chan-
nel independently. The ADC’s internal reference can be
output at pin GP1.
Figure 9. ADC Block Diagram
DS4830A Optical Microcontroller
www.maximintegrated.com
Maxim Integrated │ 23
ADC-S[15:0]
ADC-D[7:0]
ADC-SHP[1:0]
ADC-SHN[1:0]
ADC-REFIN[A/B]
ADC-VDD
ADC-VREF_2.5V
ADC-TINT
MUX
ADCONV
(START CONVERSATION)
ADCCFG
PGA
ADGAIN
13-BIT ADC