Datasheet

Fast Comparator/Quick Trips
The device supports 10-bit quick trip comparison function-
ality. The quick trips may be used to continuously monitor
user defined channels in a round robin sequence. The
quick trip controller allows the user to control the list of
channels to monitor in the round-robin sequence.
The quick trip (analog) performs two comparisons on any
selected channel.
1) Comparison with a high threshold value.
2) Comparison with a low threshold value.
Any comparison above the high threshold value or below
the low threshold value causes a bit to set in the cor-
responding register. This bit can be used to trigger an
interrupt. The threshold values are stored in 32 internal
register (16 for low threshold settings and 16 for high
threshold settings). The quick trip controller provides user
defined threshold values for the quick trips. Because the
quick trips and the ADC use the same input pins, the con-
troller ensures that no collision takes place.
The quick-trip-related SFRs are accessed in Module 5.
Refer to the quick trip section of the DS4830A User’s
Guide for more information.
I
2
C-Compatible Interface Modules
The device provides two independent I
2
C-compatible
interfaces, one is a master and another is a slave.
I
2
C-Compatible Master Interface
The device features an internal I
2
C-compatible master
interface for communication with a wide variety of external
I
2
C devices. The I
2
C-compatible master bus is a bidirec-
tional bus using two bus lines, the serial data line (MSDA)
and the serial clock line (MSCL). For the I
2
C-compatible
master, the device has ownership of the I
2
C bus and
drives the clock and generates the START and STOP
signals. This allows the device to send data to a slave or
receive data from a slave.
The device has a configuration bit in the I2CCN_M regis-
ter that allows the user to configure I
2
C master MSDA and
MSCL pins to two different set of pins.
PIN I2CCN_M.I2CM_ALT = 0 I2CCN_M.I2CM_ALT = 1
MSDA P1.0 P1.6
MSCL P1.1 P1.7
Details can be found in the I
2
C master section of the
DS4830A User’s Guide.
I
2
C-Compatible Slave Interface
The device also features an internal I
2
C-compatible slave
interface for communication with a host. Furthermore,
the device can be in system programmed (bootloaded)
through the I
2
C-compatible slave interface. The two inter-
face signals used by the I
2
C slave interface are SCL and
SDA. For the I
2
C-compatible slave interface, the device
relies on an externally generated clock to drive SCL and
responds to data and commands only when requested by
the I
2
C master device. The I
2
C-compatible slave inter-
face is open-drain and requires external pull up resistors.
The device supports four slave addresses. Each slave
address has dedicated 8-byte transmit page and all slave
addresses share common 8-byte receive FIFO.
SMBus Timeout
Both the I
2
C-compatible slave interfaces can work in
SMBus-compatible mode for communication with other
SMBus devices. To achieve this, a 30ms timer has been
implemented on the I
2
C-compatible slave interface to
make the interface SMBus-compatible. The purpose of
this timer is to issue a timeout interrupt and thus the firm-
ware can reset the I
2
C-compatible slave interface when
the SCL is held low for longer than 30ms. The timer only
starts when none of the following conditions is true:
1) The I
2
C-compatible slave interface is in the idle state
and there is no communication on the bus.
2) The I
2
C-compatible slave interface is not working in
SMBus-compatible mode.
3) The SCL logic level is high.
4) The I
2
C-compatible slave interface is disabled.
When a timeout occurs, the timeout bit is set and an
interrupt is generated, if enabled. The I
2
C master related
SFRs are accessed in Module 1. The I
2
C slave related
SFRs are accessed in Module 2. Details can be found in
the I
2
C master and slave section of the DS4830A User’s
Guide.
DS4830A Optical Microcontroller
www.maximintegrated.com
Maxim Integrated │ 26