Datasheet

Serial Peripheral Interface Module
The device supports master and slave SPI interfaces.
The SPI provides an independent serial communication
channel to communicate synchronously with peripheral
devices in a multiple master or multiple slave system. The
interface allows access to a four-wire, full-duplex serial
bus, and can be operated in either master mode or slave
mode. Collision detection is provided when two or more
masters attempt a data transfer at the same time. The
maximum data rate of the SPI is 1/4 the system reference
clock frequency for slave mode and 1/2 the system clock
frequency for master mode.
The SPI uses the following four interface signals:
● Master In-Slave Out. This signal is an output from
a slave device, SSPIDO, and an input to the master
device, MSPIDI. It is used to serially transfer data
from the slave to the master. Data is transferred most
significant bit (MSB) first. The slave device places this
pin in an input state with a weak pullup when it is not
selected.
● Master Out-Slave In. This signal is an output from
a master device, MSPIDO, and an input to the slave
devices, SSPIDI. It is used to serially transfer data from
the master to the slave. Data is transferred MSB first.
● SPI Clock. This serial clock is an output from the mas-
ter device, MSPICK, and an input to the slave devices,
SSPICK. It is used to synchronize the transfer of data
between the master and the slave on the data bus.
● Slave Select. The slave-select signal is an input to
enable the SPI module in slave mode, SSPICS, by a
master device. The SPI module supports configuration
of an active SSPICS state through the slave-active
select. Normally, this signal has no function in master
mode and its port pin can be used as a general-pur-
pose I/O. However, the SSEL can optionally be used
as mode fault detection in master mode.
SPI Master Interface
The master mode is used when the device’s SPI controls
the data transmission rates and data format. The SPI is
placed in master mode by setting the master mode bit
(MSTM). Only an SPI master device can initiate a data
transfer. Writing a data character to the SPI data buffer
(SPIB), when in master mode, starts a data transfer. The
SPI master immediately shifts out the data serially on
MSPIDO, MSB first, while providing the serial clock on the
MSPICK output. New data is simultaneously gated in on
MSPIDI into the least significant bit (LSB) of the shift reg-
ister. At the end of a transfer, the received data is loaded
into the data buffer for reading, and the SPI transfer com-
plete flag (SPIC) is set. If SPIC is set, an interrupt request
is generated to the interrupt handler, if enabled.
SPI Slave Interface
Slave mode is used when the SPI is controlled by another
peripheral device. The SPI is in slave mode when an inter-
nal bit (MSTM) is cleared to logic 0. In slave mode, the
SPI is dependent on the SPICK sourced from the master
to control the data transfer. The SPICK input frequency
should not be greater than the system clock frequency of
the slave device divided by 4. The SPI master transfers
data to a slave on the SSPIDI, MSB first, the selected
slave device simultaneously transfers the contents of its
shift register to the master on the SSPIDO, also MSB
first. Data received from the master replaces data in the
slave’s shift register at the completion of a transfer. Just
like in the master mode, received data is loaded into the
read buffer and the SPIC is set at the end of the transfer.
Setting the SPIC flag may cause an interrupt if enabled.
The SPI master-related SFRs are accessed in Module 5.
The SPI slave-related SFRs are accessed in Module 4.
Details can be found in the SPI section of the DS4830A
User’s Guide.
3-Wire Interface Module
The device controls 3-wire slave devices like the MAX3798
and MAX3799 over a proprietary 3-wire interface. The
device acts as the 3-wire master, initiating communica-
tion with and generating the clock for the 3-wire slave. It
is a 3-pin interface consisting of MSDIO (a bidirectional
data line), an MSCL clock signal, and an MCS chip-select
output (active high).
The 3-wire master-related SFRs are accessed in Module 4.
Detailed information regarding the 3-wire interface block
can be found in the DS4830A User’s Guide.
DS4830A Optical Microcontroller
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