Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x20) 8-Bit 16 MHz I/O number 32

1 of 25

REV: 072806

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS5002FP secure microprocessor chip is a

secure version of the DS5001FP 128k soft

microprocessor chip. In addition to the memory and

I/O enhancements of the DS5001FP, the secure

microprocessor chip incorporates the most

sophisticated security features available in any

processor. The security features of the DS5002FP

include an array of mechanisms that are designed to

resist all levels of threat, including observation,

analysis, and physical attack. As a result, a massive

effort is required to obtain any information about

memory contents. Furthermore, the “soft” nature of

the DS5002FP allows frequent modification of the

secure information, thereby minimizing the value of

any secure information obtained by such a massive

effort.

PIN CONFIGURATION

FEATURES

 8051-Compatible Microprocessor for

Secure/Sensitive Applications

Access 32kB, 64kB, or 128kB of NV SRAM for

Program and/or Data Storage

In-System Programming Through On-Chip Serial

Port

Can Modify Its Own Program or Data Memory in

the End System

 Firmware Security Features

Memory Stored in Encrypted Form

Encryption Using On-Chip 64-Bit Key

Automatic True Random Key Generator

Self Destruct Input (SDI)

Optional Top Coating Prevents Microprobe

(DS5002FPM)

Improved Security Over Previous Generations

Protects Memory Contents from Piracy

 Crash-Proof Operation

Maintains All Nonvolatile Resources for Over 10

Years in the Absence of Power

Power-Fail Reset

Early Warning Power-Fail Interrupt

Watchdog Timer

ORDERING INFORMATION

PART TEMP RANGE

INTERNAL

MICRO

PROBE

SHIELD

PIN-

PACKAGE

DS5002FPM-16 0°C to +70°C Yes 80 QFP

DS5002FPM-16+ 0°C to +70°C Yes 80 QFP

DS5002FMN-16 -40°C to +85°C Yes 80 QFP

DS5002FMN-16+ -40°C to +85°C Yes 80 QFP

+ Denotes a Pb-free/RoHS-compliant device.

Selector Guide appears at end of data sheet.

DS5002FP

Secure Microprocessor Chip

www.maxim-ic.com

P0.4AD4

BA9

P0.3/AD3

BA8

P0.2/AD2

BA13

P0.1/AD1

P0.0/AD0

CC0

MSEL

P1.0

BA14

P1.1

BA12

P1.2

BA7

P1.3

BA6

P2.6/A14

BD3

P2.5/A13

BD2

P2.4/A12

BD1

P2.3/A11

BD0

VLI

SDI

GND

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

XTAL2

P3.7/RD

P3.6/WR

P3.5/TI

RST

P3.4/T0

Dallas

Semiconductor

DS5002FP

P1.4

BA5

P1.5

BA4

P1.6

BA3

P1.7

PRO

BA2

RST

BA1

P3.0/RXD

BA0

P3.1/TXD

P3.2/INT0

P3.3/INT1

BA11

P0.5/AD5

P0.6/AD6

BA10

P0.7/AD7

N.C.

E1N

BD7

ALE

BD6

N.C.

BD5

P2.7/A15

BD4

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

QFP

TOP VIEW

Summary of content (25 pages)

PAGE 1
DS5002FP Secure Microprocessor Chip www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS5002FP secure microprocessor chip is a secure version of the DS5001FP 128k soft microprocessor chip. In addition to the memory and I/O enhancements of the DS5001FP, the secure microprocessor chip incorporates the most sophisticated security features available in any processor.
PAGE 2
DS5002FP Secure Microprocessor Chip ELECTRICAL SPECIFICATIONS The DS5002FP adheres to all AC and DC electrical specifications published for the DS5001FP. ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………….-0.3V to (VCC + 0.5V) Voltage Range on VCC Relative to Ground……………………………………………………………………-0.3V to +6.0V Operating Temperature Range………………………………………………………………………………..-40°C to +85°C Storage Temperature* ...……………………………………………………………………………………..
PAGE 3
DS5002FP Secure Microprocessor Chip DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.
PAGE 4
DS5002FP Secure Microprocessor Chip AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.
PAGE 5
DS5002FP Secure Microprocessor Chip Figure 2. Expanded Data Memory Write Cycle AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE (VCC = 5V ± 10%, TA = 0°C to +70°C.) (Figure 3) # PARAMETER SYMBOL 28 External Clock High Time tCLKHPW 29 External Clock Low Time tCLKLPW 30 External Clock Rise Time tCLKR 31 External Clock Fall Time tCLKF Figure 3.
PAGE 6
DS5002FP Secure Microprocessor Chip AC CHARACTERISTICS—POWER CYCLE TIME (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 4) # PARAMETER 32 Slew Rate from VCCMIN to VLI 33 Crystal Startup Time 34 Power-on Reset Delay SYMBOL tF tCSU tPOR Figure 4.
PAGE 7
DS5002FP Secure Microprocessor Chip AC CHARACTERISTICS—SERIAL PORT TIMING, MODE 0 (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 5) # PARAMETER 35 Serial Port Clock Cycle Time 36 Output Data Setup to Rising Clock Edge 37 Output Data Hold after Rising Clock Edge 38 Clock Rising Edge to Input Data Valid 39 Input Data Hold after Rising Clock Edge SYMBOL tSPCLK tDOCH tCHDO tCHDV tCHDIV Figure 5.
PAGE 8
DS5002FP Secure Microprocessor Chip AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING (VCC = 5V ±10%, TA = 0°C to +70°C.
PAGE 9
DS5002FP Secure Microprocessor Chip RPC AC CHARACTERISTICS, DBB READ (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) # PARAMETER 54 CS, A0 Setup to RD SYMBOL tAR MIN 0 MAX UNITS ns 55 CS, A0 Hold After RD tRA 0 ns 56 RD Pulse Width tRR 160 ns 57 CS, A0 to Data Out Delay tAD 58 RD to Data Out Delay tRD 59 RD to Data Float Delay tRDZ 0 130 ns 130 ns 85 ns MAX UNITS ns RPC AC CHARACTERISTICS, DBB WRITE (VCC = 5V ±10%, TA = 0°C to +70°C.
PAGE 10
DS5002FP Secure Microprocessor Chip Figure 7.
PAGE 11
DS5002FP Secure Microprocessor Chip PIN DESCRIPTION PIN 11, 9, 7, 5, 1, 79, 77, 75 15, 17, 19, 21, 25, 27, 29, 31 49, 50, 51, 56, 58, 60, 64, 66 NAME FUNCTION P0.0–P0.7 General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this mode, it does not require pullups. P1.0–P1.7 General-Purpose I/O Port 1 P2.0–P2.7 General-Purpose I/O Port 2.
PAGE 12
DS5002FP Secure Microprocessor Chip PIN NAME 62 CE4 78 PE1 3 PE2 22 PE3 23 PE4 32 PROG 42 VRST 43 PF 14 MSEL 53 SDI 72 CE1N 73 N.C. FUNCTION Active-Low Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused. CE4 is lithium-backed and remains at a logic high when VCC falls below VLI. Active-Low Peripheral Enable 1.
PAGE 13
DS5002FP Secure Microprocessor Chip DETAILED DESCRIPTION The DS5002FP implements a security system that is an improved version of its predecessor, the DS5000FP. Like the DS5000FP, the DS5002FP loads and executes application software in encrypted form. Up to 128kB of standard SRAM can be accessed by its byte-wide bus. This RAM is converted by the DS5002FP into lithiumbacked nonvolatile storage for program and data. Data is maintained for over 10 years at room temperature with a very small lithium cell.
PAGE 14
DS5002FP Secure Microprocessor Chip Figure 8.
PAGE 15
DS5002FP Secure Microprocessor Chip SECURE OPERATION OVERVIEW The DS5002FP incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the NV RAM. Loading an application program in this manner is performed by the bootstrap loader using the general sequence described below: 1) 2) 3) 4) 5) Clear security lock.
PAGE 16
DS5002FP Secure Microprocessor Chip Figure 9. Security Circuitry The address encryptor translates each “logical” address, i.e., the normal sequence of addresses that are generated in the logical flow of program execution, into an encrypted address (or “physical” address) at which the byte is actually stored.
PAGE 17
DS5002FP Secure Microprocessor Chip protection measure, the address encryptor also generates “dummy” read access cycles whenever time is available during program execution. DUMMY READ CYCLES Like the DS5000FP, the DS5002FP generates a “dummy” read access cycle to non-sequential addresses in external RAM memory whenever time is available during program execution. This action has the affect of further complicating the task of determining the normal flow of program execution.
PAGE 18
DS5002FP Secure Microprocessor Chip observe such relationships. Although it is very unlikely that an application program could be deciphered by observing vector address relationships, the vector RAM eliminates this possibility. Note that the dummy accesses mentioned above are conducted while fetching from vector RAM. The vector RAM is automatically loaded with the user’s reset and interrupt vectors during bootstrap loading.
PAGE 19
DS5002FP Secure Microprocessor Chip Table 1.
PAGE 20
DS5002FP Secure Microprocessor Chip selections are made using special function registers. The memory map and its controls are covered in detail in the Secure Microcontroller User’s Guide. Figure 10.
PAGE 21
DS5002FP Secure Microprocessor Chip Figure 11. Memory Map In Partitionable Mode (PM = 0) Figure 12.
PAGE 22
DS5002FP Secure Microprocessor Chip Figure 13 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common RAM chip. Figure 14 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM. Figure 13.
PAGE 23
DS5002FP Secure Microprocessor Chip Figure 14. Connection to 64k x 8 SRAM POWER MANAGEMENT The DS5002FP monitors VCC to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. It uses an internal bandgap reference in determining the switch points. These are called VPFW , VCCMIN, and VLI respectively. When VCC drops below VPFW, the DS5002FP will perform an interrupt vector to location 2Bh if the power-fail warning was enabled.
PAGE 24
DS5002FP Secure Microprocessor Chip SELECTOR GUIDE STANDARD PART DS5002FP-16 DS5002FPM-16 DS5002FP-16N DS5002FMN-16 Pb-FREE/RoHS COMPLIANT DS5002FP-16+ DS5002FPM-16+ DS5002FP-16N+ DS5002FMN-16+ TEMP RANGE MAX CLOCK SPEED (MHz) 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 16 16 16 16 INTERNAL MICROPROBE SHIELD No Yes No Yes PIN-PACKAGE 80 QFP 80 QFP 80 QFP 80 QFP PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications.
PAGE 25
DS5002FP Secure Microprocessor Chip REVISION HISTORY REVISION DESCRIPTION 112795 Original release. Change VCC02 specification from VLI - 0.5 to VLI - 0.65 (PCN F62501). Update mechanical specifications. Change VCC01 from VCC - 0.3 to VCC - 0.35. PF signal moved from VOL2 test specification to VOL1. PCN No. (D72502). AC characteristics for battery-backed SDI pulse specification added. Reduced absolute maximum voltage to VCC + 0.5V.