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DS8007

Multiprotocol Dual Smart Card Interface

________________________________________________________________

Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS8007 multiprotocol dual smart card interface is a

low-cost, dual smart card reader interface supporting

all ISO 7816, EMV

, and GSM11-11 requirements.

Through its 8-bit parallel bus and dedicated address

selects (AD3–AD0), the DS8007 can easily and directly

connect to the nonmultiplexed byte-wide bus of a

Maxim secure microcontroller. Optionally, the parallel

bus can be multiplexed to allow direct access to the

multiplexed bus of an 80C51-compatible microcon-

troller through MOVX memory addressing.

One integrated ISO 7816 UART is multiplexed among

the interfaces to allow high-speed automatic smart card

processing with each card-possessing, independent,

variable, baud-rate capability. The card interface is con-

trolled by internal sequencers that support automatic

activation and deactivation sequencing, handling all

actions required for T = 0, T = 1, and synchronous pro-

tocols. Emergency deactivation is also supported in

case of supply dropout. A third card is supported

through the auxiliary I/O. The same set of I/O can option-

ally be used as additional serial interface for the UART.

The DS8007 provides all electrical signals necessary to

interface with two smart cards. The integrated voltage

converter ensures full cross-compatibility between 1.8V/

3V/5V cards and a 1.8V/3V/5V environment, and allows

operation within a 2.7V to 6V supply voltage range.

Applications

Banking Applications (Point-of-Sale Terminals,

Debit/Credit Payment Terminals, PIN Pads,

Automated Teller Machines)

Telecommunications

Pay Television

Access Control

Features

♦ Integrated ISO 7816 UART Provides Complete

Interface/Control for Two Separate Smart Card

Devices

♦ 8kV (min) ESD Protection on Card Interfaces

♦ Internal IC Card Supply Voltage Generation

5.0V ±5%, 65mA (max)

3.0V ±8%, 50mA (max)

1.8V ±10%, 30mA (max)

♦ Automatic Card Activation, Deactivation, and Data

Communication Controlled by Dedicated Internal

Sequencer

♦ Host Interface Through an 8-Bit Parallel Bus (User-

Selectable Multiplexed or Nonmultiplexed Modes)

♦ Chip Select and Three-State Bus Allow Multiple

Devices (Card Readers and Memories) on Bus

♦ 8-Character Receive FIFO with Optional

Programmable Depth/Threshold

♦ I/O Interface Pin to External ISO 7816 UART for

Auxiliary Interface

♦ Separate Card Clock Generation (Up to 10MHz)

with 2x Frequency Doubling

♦ Selectable Card Clock Stop High, Stop Low, or

Internally Generated 1.25MHz (for Card Power-

Down)

♦ EMV-Certified Reference Design and Evaluation

Kit Available (DS8007-KIT)

19-5972; Rev 3; 7/11

EVALUATION KIT

AVAILABLE

Ordering Information

Typical Operating Circuit appears at end of data sheet.

PART TEMP RANGE

SMART

CARDS

SUPPORTED

PIN-

PACKAGE

DS8007-ENG -40°C to +85°C

2 + auxiliary

48 LQFP

DS8007-ENG+ -40°C to +85°C

2 + auxiliary

48 LQFP

Denotes a lead(Pb)-free/RoHS-compliant package.

EMV is a registered trademark of EMVCo LLC.

MAXQ is a registered trademark of Maxim Integrated Products, Inc.

Note: Some revisions of this device may incorporate devia-

tions from published specifications known as errata. Multiple

revisions of any device may be simultaneously available

through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata

CPA2

AGND

RSTOUT

I/OAUX

I/OA

C8A

PRESA

C4A

GNDA

CLKA

CCA

RSTA

I/OB

C8B

PRESB

C4B

GNDB

CLKB

CCB

RSTB

GND

CPA1

CPB1

DDA

CPB2

DELAY

XTAL1

XTAL2

AD0

AD1

AD2

AD3

INTAUX

INT

ALE

LQFP

DS8007

Pin Configuration

Summary of content (41 pages)

PAGE 1
9-5972; Rev 3; 7/11 KIT ATION EVALU E L B A IL AVA Multiprotocol Dual Smart Card Interface Features The DS8007 multiprotocol dual smart card interface is a low-cost, dual smart card reader interface supporting all ISO 7816, EMV ® , and GSM11-11 requirements. Through its 8-bit parallel bus and dedicated address selects (AD3–AD0), the DS8007 can easily and directly connect to the nonmultiplexed byte-wide bus of a Maxim secure microcontroller.
PAGE 2
DS8007 Multiprotocol Dual Smart Card Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD Relative to Ground ...........-0.5V to +6.5V Voltage Range on VDDA Relative to Ground .........-0.5V to +6.5V Voltage Range on Any Pin Relative to Ground Pins CPA1, CPA2, CPB1, CPB2, and VUP .........-0.5V to +7.5V All Other Pins...........................................-0.5V to (VDD + 0.5V) Maximum Junction Temperature .....................................
PAGE 3
Multiprotocol Dual Smart Card Interface (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Alarm Pulse Width SYMBOL tW External Clock Frequency Internal Oscillator f XTAL VUP Voltage Detection of VDDA for 2x, 3x Step-Up VDET Shutdown Temperature T SD RSTx Pins Card Active Mode MIN TYP MAX 10 4 20 External oscillator 0 20 1.6 2.5 3x step-up 5.7 2x step-up 4.1 3.35 3.
PAGE 4
DS8007 Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.
PAGE 5
Multiprotocol Dual Smart Card Interface (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Card Inactive Mode Card Active Mode CONDITIONS MAX UNITS 0 0.
PAGE 6
DS8007 Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage VILAUX -0.3 0.3 x VDD V Input High Voltage VIHAUX 0.7 x VDD VDD V Input Low Current I ILAUX VILAUX = 0V 700 μA Input High Current I IHAUX VIHAUX = VDD +20 μA t IT CL = 30pF 1.2 μs Output Low Voltage VOLINT I OH = 2mA 0.
PAGE 7
Multiprotocol Dual Smart Card Interface (VDD = 3.3V, VDDA = 3.3V, TA = +25°C, unless otherwise noted.
PAGE 8
DS8007 Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR NONMULTIPLEXED PARALLEL BUS (READ AND WRITE) (VDD = 3.3V, VDDA = 3.3V, TA = +25°C, unless otherwise noted.) (See Figure 2.
PAGE 9
Multiprotocol Dual Smart Card Interface (VDD = 3.3V, VDDA = 3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SEE FIGURE 3 RD Pulse Width RD Low to Bit CRED = 1 Set Time Bit FE Set Time Bit RBF tW(RD) 10 ns tRD(URR) tW(RD) + 2tCY(CLK) t SB(FE) 10.5 ETU t SB(RBF) 10.
PAGE 10
DS8007 Multiprotocol Dual Smart Card Interface I/Ox TBE BIT INT WR/CS tW(WR) CRED BIT tWR(UTR) Figure 4. Timing Between Two Write Operations in Register UTR WR/CS CRED BIT tW(WR) tWR(TOC) Figure 5.
PAGE 11
Multiprotocol Dual Smart Card Interface PIN NAME FUNCTION 1 RSTOUT Reset Output. This active-high output is provided for resetting external devices. The RSTOUT pin is driven high until the DELAY pin reaches VDRST. Once the DELAY pin reaches VDRST, the RSTOUT pin is threestated so it can externally be pulled down. The SUPL bit is set for each RSTOUT pulse. 2 I/OAUX 3 I/OA Smart Card A I/O Data Line. This is the I/O data line associated with smart card A.
PAGE 12
DS8007 Multiprotocol Dual Smart Card Interface Pin Description (continued) PIN NAME 24 CPB2 Step-Up Converter Contact 4. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2. FUNCTION 25 AGND Analog Ground 26 CPA2 27 VDD 28–35 D0–D7 8-Bit Digital I/O. This port functions as the data or address/data communication lines between the host controller and the DS8007 for the nonmultiplexed and multiplexed operating modes, respectively. 36 RD Active-Low Parallel Bus Read Strobe Input.
PAGE 13
Multiprotocol Dual Smart Card Interface The following describes the major functional features of the device. Use of this document requires the reader have a basic understanding of ISO 7816 terminology. Parallel Bus Interface The device interfaces to a host computer/processor through a multiplexed or demultiplexed, parallel, 8-bit data bus (D0–D7). The parallel bus interface monitors the ALE signal and automatically detects whether a multiplexed or nonmultiplexed external bus interface is intended.
PAGE 14
DS8007 Multiprotocol Dual Smart Card Interface CS RD WR REGISTERS 0 AD3–AD0 D7–D0 LATCH 1 D3–D0 ALE VDD CS RST LOGIC OR RST CONTROL Figure 7. Parallel Bus Interface Multiplexed Mode Nomultiplexed Mode In the multiplexed mode of operation, the D7–D0 signals are multiplexed between address and data.
PAGE 15
Multiprotocol Dual Smart Card Interface If the SC3–SC1 bits are configured so that card A is selected, then all reads and writes to address 06h only affect card A. If SC3–SC1 are changed to select card B, then all reads and writes to address 06h only affect card B, etc. In addition, some registers have different functions based on whether the register is being read from or written to. An example of this are the UART Receive (URR)/UART Transmit (UTR) registers located at address 0Dh.
PAGE 16
DS8007 Multiprotocol Dual Smart Card Interface Card Select Register (CSR) Address 00h 7 6 5 4 3 2 1 0 CSR7 CSR6 CSR5 CSR4 RIU SC3 SC2 SC1 R-0 R-0 R-1 R-1 RW-0 RW-0 RW-0 RW-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00110uuub on RIU = 0. Bits 7 to 4: Identification Bits (CSR7 to CSR4). These bits provide a method for software to identify the device as follows: 0011 = DS8007 revision Ax Bit 3: Reset ISO UART (RIU).
PAGE 17
Multiprotocol Dual Smart Card Interface Address 02h 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0. • ETU = Prescaler output / (PD7–PD0), when PD7–PD0 = 02h–FFh • ETU = Prescaler output / 1, when PD7–PD0 = 00h–01h Bits 7 to 0: Programmable ETU Divider Register Bits 7 to 0 (PD7 to PD0).
PAGE 18
DS8007 Multiprotocol Dual Smart Card Interface Bit 4: Power-Down Mode Enable (PDWN). This bit controls entry into the power-down mode. Power-down mode can only be entered if the SUPL bit has been cleared. When PDWN is set to 1, the XTAL1 and XTAL2 crystal oscillator is stopped, and basic functions such as the sequencers are supported by the internal ring oscillator. The UART is put in a suspended state, and the clocks to the UART, the ETU unit, and the timeout counter are gated off.
PAGE 19
Multiprotocol Dual Smart Card Interface Address 06h 7 6 5 4 3 2 1 0 FTE0 FIP — PROT T/R LCT SS CONV R-0 RW-0 R-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu00uub on RIU = 0. Bit 7: FIFO Threshold Enable 0 (FTE0). When this bit and the FTE1 (FCR.3) bit are set, the programmable FIFO threshold feature is enabled. This bit always reads 0 for compatibility. Bit 6: Force Inverse Parity (FIP).
PAGE 20
DS8007 Multiprotocol Dual Smart Card Interface Power Control Register (PCR) Address 07h 7 6 5 4 3 2 1 0 — — C8 C4 1V8 RSTIN 3V/5V START R-0 R-0 RW-1 RW-1 RW-0 RW-0 RW-0 RW-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0011uuuub on RIU = 0. Note: The AUX card interface does not have register PCR. C4 and C8 are external ports that are internally pulled up (10kΩ to VCCx), writing a 1 to C4, C8 configures the weak pullup.
PAGE 21
Multiprotocol Dual Smart Card Interface Address 09h 7 6 5 4 3 2 1 0 TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU = 0. counters. These counters are only used when a card is supplied an active clock. See the Timeout Counter Operation section for details on configurable modes. Bits 7 to 0: Timeout Counter Register 1 Bits (TOL7 to TOL0).
PAGE 22
DS8007 Multiprotocol Dual Smart Card Interface Mixed Status Register (MSR) Address 0Ch 7 6 5 4 3 2 1 0 CLKSW FE BGT CRED PRB PRA INTAUX TBE/RBF R-0 R-1 R-0 R-1 R-0 R-0 R-0 R-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to u1u1uuu0b on RIU = 0. Bit 7: Clock Switch (CLKSW).
PAGE 23
Multiprotocol Dual Smart Card Interface Address 0Ch 7 6 5 4 3 2 1 0 — PEC2 PEC1 PEC0 FTE1 FL2 FL1 FL0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu0uuub on RIU = 0. if PEC2–PEC0 = 000b, only one parity error needs to be detected for the PE bit to be set; if PEC2–PEC0 = 111b, 8 parity errors must be detected, etc.
PAGE 24
DS8007 Multiprotocol Dual Smart Card Interface UART Status Register (USR) Address 0Eh 7 6 5 TO3 TO2 TO1 R-0 R-0 R-0 4 3 2 1 0 EA PE OVR FER TBE/RBF R-0 R-0 R-0 R-0 R-0 R = unrestricted read, W = unrestricted write, -n = value after reset. All register bits are reset to 00000000b on RIU = 0. Note: If any of the bits TO3, TO2, TO1, EA, PE, OVR, or FER are set, then a USR read operation clears the bit, causing an interrupt less than 2µs after the rising edge of the RD strobe.
PAGE 25
Multiprotocol Dual Smart Card Interface Address 0Fh 7 6 5 4 3 2 1 0 — PRTLB PRTLA SUPL PRLB PRLA INTAUXL PTL R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0 R = unrestricted read, W = unrestricted write, -n = value after reset, x = always reflects state of external device pin. This register is reset to 0uuuxxxub on RIU = 0. Note: A minimum of 2µs is needed between successive reads of the HSR to allow for hardware updates.
PAGE 26
DS8007 Multiprotocol Dual Smart Card Interface Card Interface Voltage Regulation and Step-Up Converter Operation The VDD and VDDA pins supply power to the DS8007. Voltage supervisor circuitry detects the input voltage levels and automatically engages a step-up converter if necessary to generate the appropriate voltages to the card interfaces according to the control register settings.
PAGE 27
Multiprotocol Dual Smart Card Interface DS8007 VRST = 2.1V TO 2.5V VDD RESULTING FROM VDD < VRST DELAY DRIVEN LOW EXTERNALLY VDRST = ~1.25V DELAY tW RSTOUT INT SUPL BIT SUPL BIT CLEARED BY HSR READ ONLY Figure 8.
PAGE 28
DS8007 Multiprotocol Dual Smart Card Interface Activation Sequencing operating conditions (e.g., the card is present and the supply voltage is correct). These conditions can be ascertained through the HSR, MSR, and CSR bits. An activation sequence can only be requested by a host device through the parallel bus interface.
PAGE 29
Multiprotocol Dual Smart Card Interface The host device can request a deactivation sequence by resetting the START bit to 0 for the desired card interface. The deactivation (from the deassertion of the START bit, step 1 of the deactivation sequence, to VCCx decrease to less than 0.4V) is less than 150µs. Emergency Deactivation An emergency deactivation occurs if unsatisfactory operating conditions are detected.
PAGE 30
DS8007 Multiprotocol Dual Smart Card Interface Timeout Counter Operation The timeout counter assists the host device in timing real-time events associated with the communication protocols: the Work Wait Time (WWT), Block Waiting Time (BWT), etc. The timeout counter registers count ETUs, so the input clock to the timeout counter is derived from the output of the programmable divided clock (per card PDR register). The timeout counter requires the card be powered and have an active clock.
PAGE 31
Multiprotocol Dual Smart Card Interface TOC VALUE 71h 75h TOR3 TOR2 Start Bit 85h E5h F1h F5h Stopped Start Bit/Autoreload Start Bit 7Ch TOR1 Start Bit DESCRIPTION Counter 1 is stopped. Counters 3 and 2 form a 16-bit counter operating in start bit mode for both transmission and reception. TOR3 and TOR2 registers can be changed during the count, the current count is not affected, and the values are taken into account at the next START bit detected on the I/Ox pin.
PAGE 32
DS8007 Multiprotocol Dual Smart Card Interface ISO UART Implementation Reset Operation The CSR.RIU control bit resets the ISO UART. The CSR.RIU must be reset prior to any activation. CSR.RIU must be returned to 1 by software before any UART action can take place. Synchronous Mode The synchronous mode of operation is invoked by setting the synchronous/asynchronous card select bit (for a given card interface) to logic 1.
PAGE 33
Multiprotocol Dual Smart Card Interface PDR /31: PSC = 0 /32: PSC = 1 PD7:PD0 = 00h TO FFh ETU 1 EN 0 CLR fCLK TO3, TO2, TO1 CLK 0 UCR2x.PSC 2 x fCLK TOC COUNTERS DS8007 CLOCK PRESCALER SOFTWARE MODE 1 (ALIGNED ETU GENERATOR) ETU UCR2x.CKU CLOCK PRESCALER PDR /31: PSC = 0 /32: PSC = 1 PD7:PD0 = 00h TO FFh 0.5 ETU 0.25 ETU EN FRACTIONAL ETU COUNTERS 10.5 ETU TO 15 ETU CLK CLR RSTx START BIT GATE EN FRAME-ERRORDETECTED COUNTER 10.25 ETU CLK Figure 11.
PAGE 34
DS8007 Multiprotocol Dual Smart Card Interface parameters continue to be used until a successful PPS exchange is completed. The negotiated Fn, Dn values are then used after a successful PPS exchange. If the card comes up in specific mode (i.e., TA(2) is present in ATR), then the indicated Fi, Di values apply immediately after successful ATR if bit 5 of the TA(2) character is 0. If bit 5 of TA(2) is 1, implicit values should be used.
PAGE 35
Multiprotocol Dual Smart Card Interface The ISO UART is designed to support two possible character encoding/decoding formats: direct and inverted. The direct character coding convention transmits and receives data LSb first and associates a high logic level with a bit 1 and a low logic level with a bit 0. The inverse character coding convention transmits and receives data most significant bit first and associates a high logic level with a bit 0 and a low logic level with a bit 1. The UCR1.
PAGE 36
DS8007 Multiprotocol Dual Smart Card Interface Block Guard Time The block guard time for the asynchronous serial communication between the smart card reader (DS8007) and the ICC is defined as the minimum delay between consecutive start bits sent in the opposite direction. The DS8007 implements an internal ETU counter specifically to help the host device assess that this minimum block guard time is being met.
PAGE 37
Multiprotocol Dual Smart Card Interface Receive Mode The ISO UART receive mode is in effect if the associated UCR1.T/R bit is 0. When the ISO UART is changed to receive mode, the MSR.FE bit is set to 1 to indicate that the receive FIFO is empty. When at least one unread receive character exists in the FIFO, the FE bit is cleared. When the FIFO, with depth defined by FL2–FL0, is full, the TBE/RBF bit is set to 1 to indicate that the receive buffer is full.
PAGE 38
DS8007 Multiprotocol Dual Smart Card Interface Error-Signal Generation The T = 1 protocol does not support error-signal generation. When configured to receive using the T = 0 protocol (UCR1.PROT = 0), the DS8007 supports errorsignal generation in response to parity.
PAGE 39
Multiprotocol Dual Smart Card Interface Table 6.
PAGE 40
13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7 GND 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 C15 22pF C13 22pF 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 1 30 22 CE 24 OE 29 WE C1 0.1μF U1 CY62148BLL-70SXC VCC 32 VCCO Y2 14.
PAGE 41
Multiprotocol Dual Smart Card Interface REVISION NUMBER REVISION DATE 0 1/07 1 10/07 2 3 DESCRIPTION PAGES CHANGED Initial release — In the Features section, changed 6kV (min) to 8kV (min); added new bullet for EMVcertified reference design and EV kit availability 1 8/08 In the General Description, added “ISO 7816” to “UART” for clarification; in the Features section, added clarification about the integrated ISO 7816 UART 1 7/11 Added assembly-related specifications to the Absolute Maximum