Datasheet

DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
28 of 38
MOVX CHARACTERISTICS—DS80C323
VARIABLE CLOCK
PARAMETER SYMBOL
MIN MAX
UNITS STRETCH
2t
CLCL
-11 t
MCS
=0
RD Pulse Width
t
RLRH
t
MCS
-11
ns
t
MCS
>0
2t
CLCL
-11 t
MCS
=0
WR
Pulse Width
t
WLWH
t
MCS
-11
ns
t
MCS
>0
2t
CLCL
-32 t
MCS
=0
RD Low to Valid Data In
t
RLDV
t
MCS
-36
ns
t
MCS
>0
Data Hold After Read t
RHDX
0 ns
t
CLCL
-5 t
MCS
=0
Data Float After Read t
RHDZ
2t
CLCL
-7
ns
t
MCS
>0
2.5t
CLCL
-43 t
MCS
=0
ALE Low to Valid Data In t
LLDV
1.5t
CLCL
-45+t
MCS
ns
t
MCS
>0
3t
CLCL
-40 t
MCS
=0 Port 0 Address to Valid Data
In
t
AVDV1
2t
CLCL
-42+t
MCS
ns
t
MCS
>0
3.5t
CLCL
-58 t
MCS
=0
Port 2 Address to Valid Data
In
t
AVDV2
2.5t
CLCL
-59+t
MCS
ns
t
MCS
>0
0.5t
CLCL
-18 0.5t
CLCL
+7 t
MCS
=0
ALE Low to RD or WR
Low
t
LLWL
1.5t
CLCL
-11 1.5t
CLCL
+8
ns
t
MCS
>0
t
CLCL
-10 t
MCS
=0
Port 0 Address Valid to RD
or
WR Low
t
AVWL1
2t
CLCL
-10
ns
t
MCS
>0
1.5t
CLCL
-27 t
MCS
=0
Port 2 Address Valid to RD
or
WR Low
t
AVWL2
2.5t
CLCL
-25
ns
t
MCS
>0
-14 t
MCS
=0
Data Valid to WR Transition
t
QVWX
t
CLCL
-13
ns
t
MCS
>0
t
CLCL
-15 t
MCS
=0
Data Hold After Write t
WHQX
2t
CLCL
-13
ns
t
MCS
>0
RD Low to Address Float
t
RLAZ
(Note 5) ns
-1 14 t
MCS
=0
RD or WR High to
ALE High
t
WHLH
t
CLCL
-5 t
CLCL
+16
ns
t
MCS
>0
Note: t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the value of
t
MCS
for each Stretch selection.
M2 M1 M0 MOVX CYCLES t
MCS
0 0 0 2 machine cycles 0
0 0 1 3 machine cycles (default) 4 t
CLCL
0 1 0 4 machine cycles 8 t
CLCL
0 1 1 5 machine cycles 12 t
CLCL
1 0 0 6 machine cycles 16 t
CLCL
1 0 1 7 machine cycles 20 t
CLCL
1 1 0 8 machine cycles 24 t
CLCL
1 1 1 9 machine cycles 28 t
CLCL