PRELIMINARY DS80C390 Dual CAN High-Speed Microprocessor www.dalsemi.
DS80C390 DESCRIPTION The DS80C390 is a fast 8051-compatible microprocessor. The redesigned processor core executes 8051 instructions up to 3 times faster than the original for the same crystal speed. The DS80C390 supports a maximum crystal speed of 40 MHz, resulting in apparent execution speeds of 100 MHz (approximately 2.5X). An optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency, reducing EMI.
DS80C390 DS80C390 BLOCK DIAGRAM Figure 1 3 of 58 110199
DS80C390 PIN DESCRIPTION Table 1 LQFP PLCC SIGNAL NAME VCC 8, 22, 40, 56 9, 25, 41, 57 46 17, 32, 51, 68 1, 18, 35, 52 57 45 56 PSEN 47 58 EA 26 36 MUX 2 11 RST 3 12 RSTOL 23, 24 33, 34 XTAL2, XTAL1 55 54 53 52 51 50 49 48 67 66 65 64 63 62 61 59 AD0 / D0 AD1 / D1 AD2 / D2 AD3 / D3 AD4 / D4 AD5 / D5 AD6 / D6 AD7 / D7 DESCRIPTION +5V GND Digital Circuit Ground ALE Address Latch Enable - Output.
DS80C390 58-64, 1 2-8, 10 P1.0-P1.7 58 59 60 61 62 63 64 1 35 36 37 38 39 42 43 44 4-7, 10-13 2 3 4 5 6 7 8 10 46 47 48 49 50 53 54 55 13-16, 19-22 A0 A1 A2 A3 A4 A5 A6 A7 A8 (P2.0) A9 (P2.1) A10 (P2.2) A11 (P2.3) A12 (P2.4) A13 (P2.5) A14 (P2.6) A15 (P2.7) P3.0-P3.7 4 5 6 7 10 11 12 13 14 15 16 19 20 21 Port 1 - I/O. Port 1 can function as an 8-bit bi-directional I/O port, the non-multiplexed A0 - A7 signals (when the MUX pin =1), and as an alternate interface for internal resources.
DS80C390 13 34-27 22 45, 44, 42-37 34 33 32 31 30 29 28 27 21-14 45 44 42 41 40 39 38 37 31-27, 25-23 21 20 19 18 17 16 15 14 31 30 29 28 27 25 24 23 9, 26, 43, 60 P4.0-P4.7 P5.0-P5.7 P3.7 RD External Data Memory Read Strobe Port 4 - I/O. Port 4 can function as an 8-bit bi-directional I/O port, and as the source for external address and chip enable signals for program and data memory. Port pins are configured as I/O or memory signals via the P4CNT register.
DS80C390 80C32 COMPATIBILITY The DS80C390 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has been made to keep the core device familiar to 80C32 users while adding many new features. Because the device runs the standard 8051 instruction set, in general software written for existing 80C32based systems will work on the DS80C390.
DS80C390 required the same amount of time: two machine cycles or 24 oscillator cycles. In the DS80C390, the MOVX instruction takes as little as two machine cycles or 8 oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the device usually uses one instruction cycle for each instruction byte.
C0IR C0TE C0RE IE SADDR0 SADDR1 C0M1C C0M2C C0M3C C0M4C C0M5C P3 C0M6C C0M7C C0M8C C0M9C C0M10C IP SADEN0 SADEN1 C0M11C C0M12C C0M13C C0M14C C0M15C SCON1 SBUF1 PMR STATUS MCON TA T2CON T2MOD RCAP2L RCAP2H TL2 TH2 COR PSW MCNT0 MCNT1 MA MB MC C1RMS0 C1RMS1 WDCON C1TMA0 C1TMA1 ACC C1C C1S C1IR C1TE C1RE INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 MSRDY MSRDY MSRDY MSRDY MSRDY P3.7 MSRDY MSRDY MSRDY MSRDY MSRDY - ETI ETI ETI ETI ETI P3.
EIE MXAX C1M1C C1M2C C1M3C C1M4C C1M5C B C1M6C C1M7C C1M8C C1M9C C1M10C EIP C1M11C C1M12C C1M13C C1M14C C1M15C CANBIE C0IE C1IE EWDI EX5 EX4 EX3 EX2 MSRDY MSRDY MSRDY MSRDY MSRDY ETI ETI ETI ETI ETI ERI ERI ERI ERI ERI INTRQ INTRQ INTRQ INTRQ INTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ MTRQ MTRQ MTRQ MTRQ MTRQ ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH DTUP DTUP DTUP DTUP DTUP MSRDY MSRDY MSRDY MSRDY MSRDY CANBIP MSRDY MSRDY MSRDY MSRDY MSRDY ETI ETI ETI ETI ETI C0IP ETI ETI ETI ETI ETI ERI ERI ERI
DS80C390 ARITHMETIC ACCELERATOR SEQUENCING Divide (32/16 or 16/16) Load MA with dividend LSB. Load MA with dividendLSB+1* Load MA with dividend LSB+2* Load MA with dividend MSB. Load MB with divisor LSB. Load MB with divisor MSB. Poll the MST bit until cleared (9 machine cycles). Read MA to retrieve the quotient MSB. Read MA to retrieve the quotient LSB+2. Read MA to retrieve the quotient LSB+1. Read MA to retrieve the quotient LSB. Read MB to retrieve the remainder MSB.
DS80C390 MEMORY ADDRESSING The DS80C390 incorporates three internal memory areas: § 256 bytes of scratchpad (or direct) RAM § 4 KB of SRAM configurable as various combinations of MOVX data memory, stack memory, and MOVC program memory § 512 bytes of RAM reserved for the CAN message centers.
DS80C390 INTERNAL MOVX SRAM The DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory, program memory, or optional stack memory. The specific configuration and locations are governed by the Internal Data Memory Configuration bits (IDM1, IDM0) in the Memory Control Register (MCON;C6h). Note that when the SA bit (ACON.2) is set, the first 1kB of the MOVX data memory is reserved for use by the 10-bit expanded stack.
DS80C390 PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7 P4CNT.5-3 000 100 101 110 111(default) CE0 CE1 0h-7FFFh 0h-1FFFFh 0h-3FFFFh 0h-7FFFFh 0-FFFFFh 8000h-FFFFh 20000h-3FFFFh 40000h-7FFFFh 80000h-FFFFFh 100000h-1FFFFFh CE2 CE3 10000h-17FFFh 18000h-1FFFFh 40000h-5FFFFh 60000h-7FFFFh 80000h-BFFFFh C0000h-FFFFFh 100000h-17FFFFh 180000h-1FFFFFh 200000h-2FFFFFh 300000h-3FFFFFh The DS80C390 incorporates a feature allowing PCE and CE signals to be combined.
DS80C390 The reset default of one Stretch cycle results in a three cycle MOVX for any external access. Therefore, the default off-chip RAM access is not at full speed. This is a convenience to existing designs that utilize slower RAM. When maximum speed is desired, software should select a Stretch value of zero. When using very slow RAM or peripherals, the application software can select a larger Stretch value.
DS80C390 ENHANCED DUAL DATA POINTERS The DS80C390 contains two data pointers, DPTR0 and DPTR1, designed to improve performance in applications that require high data throughput. Incorporating a second data pointer allows the software to greatly speed up block data (MOVX) moves by using one data pointer as a source register and the other as the destination register.
DS80C390 80C32 Idle and power down (Stop) modes, the DS80C390 provides a new Power Management Mode. This mode allows the processor to continue instruction execution, yet at a very low speed to significantly reduce power consumption (below even Idle mode). The DS80C390 also features several enhancements to Stop mode that make this extremely low power mode more useful. Each of these features is discussed in detail below.
DS80C390 SYSTEM CLOCK CONFIGURATION Table 10 CD1 0 0 0 1 1 CD0 0 0 1 0 1 4X/ 2X 0 1 N/A N/A N/A Name Frequency Multiplier (2X) Frequency Multiplier (4X) Reserved Divide-by-four (Default) Power Management Mode Clocks/MC 2 1 Max. External Frequency 20 MHz 10 MHz 4 1024 40 MHz 40 MHz The system clock and machine cycle rate changes one machine cycle after the instruction changing the control bits. Note that the change will affect all aspects of system operation, including timers and baud rates.
DS80C390 POWER MANAGEMENT MODE (PMM) Crystal Speed 11.0592 MHz 16 MHz 25 MHz 33 MHz 40 MHz Machine Cycle Rate Full Operation PMM (4 clocks per (1024 clocks per machine cycle) machine cycle) 2.765 MHz 10.8 kHz 4.0 MHz 15.6 kHz 6.25 MHz 24.4 kHz 8.25 MHz 32.2 kHz 10.0 MHz 39.1 kHz Operating Current Estimates Full Operation PMM (4 clocks per (1024 clocks per machine cycle) machine cycle) 13.1 ma 4.8 ma 17.2 ma 5.6 ma 25.7 ma 7.0 ma 32.8 ma 8.
DS80C390 Software should not rely on a lower-priority level interrupt source to remove PMM (Switchback) when a higher level is in service. Check the current priority service level before entering PMM. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt service level before entering PMM.
DS80C390 During Stop mode the crystal oscillator is halted to maximize power savings. Typically 4 - 10 ms are required for an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator feature is enabled by setting the Ring Oscillator Select bit, RGSL (EXIF.1).
DS80C390 EMI REDUCTION One of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The microcontroller allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit to a 1. When ALEOFF = 1, ALE will automatically toggle during an off-chip MOVX. However, ALE will remain static when performing on-chip memory access. The default state of ALEOFF is 0 so ALE normally toggles at a frequency of XTAL/4.
DS80C390 during the debug process to determine where watchdog reset commands must be located in the application software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor from power saving modes. The Watchdog timer is controlled by the Clock Control (CKCON) and the Watchdog Control (WDCON) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the Watchdog time-out period. Of course, the 4X/ 2X (PMR.3) and CD1 :0 (PMR.
DS80C390 EXTERNAL RESET PINS The DS80C390 has both reset input (RST) and reset output ( RSTOL ) pins. The RSTOL pin supplies an active low Reset when the microprocessor is issued a Reset from either a high on the RST pin, a time out of the watchdog timer, a crystal oscillator fail, or an internally detected power-fail. The timing of the RSTOL pin is dependent on the source of the reset.
DS80C390 CONTROLLER AREA NETWORK (CAN) MODULE The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0B specification. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware.
DS80C390 Each of the message centers is identical with the exception of message center 15. Message center 15 has been designed as a receive only center and is also buffered through the use of a two message FIFO to help prevent message loss in a message overrun situation. The receipt of a third message before either of the first two are read will overwrite the second message, leaving the first message undisturbed.
DS80C390 CAN 0 MESSAGE CENTERS 2-14 MESSAGE CENTER 2 REGISTERS (similar to Message Center 1) MESSAGE CENTER 3 REGISTERS (similar to Message Center 1) MESSAGE CENTER 4 REGISTERS (similar to Message Center 1) MESSAGE CENTER 5 REGISTERS (similar to Message Center 1) MESSAGE CENTER 6 REGISTERS (similar to Message Center 1) MESSAGE CENTER 7 REGISTERS (similar to Message Center 1) MESSAGE CENTER 8 REGISTERS (similar to Message Center 1) MESSAGE CENTER 9 REGISTERS (similar to Message Center 1) MESSAGE CENTER 10 R
DS80C390 MOVX MESSAGE CENTERS FOR CAN 1 CAN 1 CONTROL/STATUS/MASK REGISTERS Register 7 6 5 4 3 2 1 0 MOVX Data Address1 C1MID0 C1MA0 C1MID1 C1MA1 C1BT0 C1BT1 C1SGM0 C1SGM1 C1EGM0 C1EGM1 C1EGM2 C1EGM3 C1M15M0 C1M15M1 C1M15M2 C1M15M3 MID07 M0AA7 MID17 M1AA7 SJW1 SMP ID28 ID20 ID28 ID20 ID12 ID4 ID28 ID20 ID12 ID4 MID06 M0AA6 MID16 M1AA6 SJW0 TSEG26 ID27 ID19 ID27 ID19 ID11 ID3 ID27 ID19 ID11 ID3 MID05 M0AA5 MID15 M1AA5 BPR5 TSEG25 ID26 ID18 ID26 ID18 ID10 ID2 ID26 ID18 ID10 ID2 MID04 M0AA4 MID1
DS80C390 CAN 1 MESSAGE CENTER 15 C1M15AR0 C1M15AR1 C1M15AR2 C1M15AR3 Reserved CAN 1 MESSAGE 15 ARBITRATION REGISTER 0 CAN 1 MESSAGE 15 ARBITRATION REGISTER 1 CAN 1 MESSAGE 15 ARBITRATION REGISTER 2 CAN 1 MESSAGE 15 ARBITRATION REGISTER 3 C1M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 0 EX/ ST MEME C1M15D0CAN 1 MESSAGE 15 DATA BYTE 0 - 7 C1M15D7 Reserved WTOE xxxxF0h - F1h xxxxF2h xxxxF3h xxxxF4h xxxxF5h MDME xxxxF6h xxxxF7h - FEh xxxxFFh Notes: 1 The first two bytes of the CAN 1 MOVX memory address are dependen
DS80C390 compared directly or via a mask register. A special set of arbitration registers dedicated to Message center 15 allow added flexibility in filtering this location. If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message against two 8-bit Media Arbitration register bytes. The MDME bit in the CAN Message Center Format Registers (C0MxF.0 or C1MxF.
DS80C390 If the WTOE bit is set, the incoming message will be received and written over the existing data bytes in that message center. The Receiver Overwrite bit (ROW) will also be set in the corresponding Message Center Control Register, located in SFR memory. Message center 15 is unique in that it incorporates a buffer that can receive up to two messages without loss.
DS80C390 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Voltage on VCC relative to ground Operating Temperature Storage Temperature Soldering Temperature -0.3 V to (VCC + 0.5 V) -0.3 V to 6.0 V -40 °C to +85 °C -55 °C to +125 °C 160 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS80C390 NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. Active current measured with 40 MHz clock source on XTAL1, VCC=RST= 5.5 V, all other pins disconnected. 2. Idle mode current measured with 40 MHz clock source on XTAL1, VCC= 5.5 V, RST= EA =VSS, all other pins disconnected. 3. Stop mode current measured with XTAL1 = RST = EA = VSS, VCC= 5.5 V, all other pins disconnected. This value is not guaranteed. Users who are sensitive to this specification should contact Dallas Semiconductor for more information.
DS80C390 AC ELECTRICAL CHARACTERISTICS (Multiplexed address/data bus) 40 MHz PARAMETER SYMBOL MIN MAX Oscillator Freq. (Ext. Osc) 1 / tCLCL 0 40 (Ext.
DS80C390 MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE MOVX CHARACTERISTICS (Multiplexed address/data bus) PARAMETER SYMBOL MIN MOVX ALE Pulse Width tLHLL2 Port 0 MOVX Address, CE0 − 4 , PCE0− 4 Valid to ALE Low Address Hold after MOVX Read/Write tAVLL2 0.375 tMCS -5 0.5 tMCS -5 1.5 tMCS -10 0.125 tMCS -5 0.25tMCS -5 1.25 tMCS -10 0.125 tMCS -5 1.125 tMCS -5 0.5 tMCS -5 CST •tMCS -10 0.
DS80C390 Port 0 Address, Port 4 CE, Port 5 PCE to Valid Data In tAVDV1 Port 2, 4 Address to Valid Data In tAVDV2 ALE Low to RD or WR Low tLLWL Port 0 Address, Port 4 CE, Port 5 PCE to RD or WR Low Port 2, 4 Address to or WR Low tAVWL1 Data Valid to WR Transition Data hold after WR high tQVWX Low to Address Float RD or WR High to ALE, Port 4 CE or Port 5 PCE High tRLAZ tWHLH RD tAVWL2 tWHQX 0.75 tMCS -20 (C ST +0.375)•tMCS -20 (C ST +1.375)•tMCS -20 0.875 tMCS -20 (C ST +0.
DS80C390 gggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg g 37 of 58 110199
DS80C390 lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllloooooooooooooooooooooooooooooooooooooooooo k 38 of 58 110199
DS80C390 MULTIPLEXED 2 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 READ 39 of 58 110199
DS80C390 MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 WRITE MULTIPLEXED 3 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE 40 of 58 110199
DS80C390 MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 READ MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 WRITE 41 of 58 110199
DS80C390 MULTIPLEXED 9 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 READ 42 of 58 110199
DS80C390 MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 WRITE ELECTRICAL CHARACTERISTICS (Non-multiplexed address/data bus) 40 MHz PARAMETER SYMBOL MIN MAX Oscillator Freq. (Ext. Osc) 1 / tCLCL 0 40 (Ext. Crystal) 1 40 tPLPH PSEN Pulse Width tPLIV PSEN Low to Valid Instruction In tPXIX 0 Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN Port 1 Address, Port 4 CE to Valid Instruction In Port 2, 4 Address to Valid Instruction In tAVIV1 VARIABLE CLOCK MIN MAX 0 40 1 40 0.5 tMCS - 5 0.
DS80C390 NON-MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE 44 of 58 110199
DS80C390 MOVX CHARACTERISTICS (Non-multiplexed address/data bus) PARAMETER Input Instruction Float after SYMBOL MIN tPXIZ 0.5 tMCS -5 0.75 tMCS -5 2.75 tMCS -10 0.
DS80C390 Ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc l 46 of 58 110199
DS80C390 ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc c 47 of 58 110199
DS80C390 NON-MULTIPLEXED 2 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE NON-MULTIPLEXED 2 CYCLE DATA MEMORY CE0 - 3 READ 48 of 58 110199
DS80C390 NON-MULTIPLEXED 2 CYCLE DATA MEMORY CE0- 3 WRITE NON-MULTIPLEXED 3 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE 49 of 58 110199
DS80C390 NON-MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 READ NON-MULTIPLEXED 3 CYCLE DATA MEMORY CE0 - 3 WRITE 50 of 58 110199
DS80C390 NON-MULTIPLEXED 9 CYCLE DATA MEMORY PCE0 - 3 READ OR WRITE NON-MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 READ 51 of 58 110199
DS80C390 NON-MULTIPLEXED 9 CYCLE DATA MEMORY CE0 - 3 WRITE tMCS TIME PERIODS System Clock Selection CD1 CD0 4X/ 2X 1 0 0 0 0 0 X 1 0 X 1 1 tMCS 1 tCLCL 2 tCLCL 4 tCLCL 1024 tCLCL EXTERNAL CLOCK CHARACTERISTICS PARAMETER Clock high time Clock low time Clock rise time Clock fall time SYMBOL tCHCX tCLCX tCLCH tCHCL MIN 8 8 MAX 4 4 UNITS ns ns ns ns EXTERNAL CLOCK DRIVE 52 of 58 110199
DS80C390 SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER Serial port clock cycle time SM2=0:2 clocks per cycle SM2=1:4 clocks per cycle Output data setup to clock rising SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle Output data hold from clock rising M2=0:12 clocks per cycle SM2=1:4 clocks per cycle Input data hold after clock rising SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle Clock rising edge to input data valid SM2=0:12 clocks per cycle SM2=1:4 clocks per cycle SYMBOL tXLXL TYPICAL UN
DS80C390 SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH-SPEED OPERATION, TXD CLK = XTAL/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK=XTAL/12 (SM2=0) 54 of 58 110199
DS80C390 EXPLANATION OF AC SYMBOLS This microcontroller uses timing parameters and symbols similar to the original 8051 family. The following list of timing symbols is provided as an aid to understanding the timing diagrams.
DS80C390 68-PIN PLCC 56 of 58 110199
DS80C390 64-PIN LQFP 57 of 58 110199
DS80C390 DATA SHEET REVISION SUMMARY The following represent the key differences between the 092499 and the 101999 version of the DS80C390 data sheet. Please review this summary carefully. 1. 2. 3. 4. Corrected P5.2 and P5.3 pin descriptions. Corrected description of sequence to activate the crystal frequency multiplier. Corrected references to PQFP to read LQFP. Added RSTOL timing information.
