Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 44 (16.59x16.59) 8-Bit 33 MHz I/O number 32

AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and

ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

REV: 040507

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS89C430 and DS89C450 offer the highe st

performance available in 8051-com patible

microcontrollers. They feature ne wly designed

processor cores that execute instructions up to 1 2

times faster than the original 8 051 at the same

crystal speed. Typical a pplications will experience a

speed improvement up to 10x. At 1 million

instructions per second (MIPS) per megahertz, the

microcontrollers achieve 33 MIPS performa nce from

a maximum 33MHz clock rate.

The DS89C440 is a 32 kB version of th e DS89C450

that is no lo nger available. The DS8 9C450 can be

used as a drop-in replacement.

The Ultra-High-Speed Flash Microcontroller User’s Guide should

be used in conjunction with this data sheet. Download it at

www.maxim-ic.com/microcontrollers

ORDERING INFORMATION

PART

FLASH

MEMORY SIZE

PIN-PACKAGE

DS89C430-MNL

16kB 40 PDIP

DS89C430-MNL+ 16kB 40 PDIP

DS89C430-QNL 16kB 44 PLCC

DS89C430-QNL+ 16kB 44 PLCC

DS89C430-ENL 16kB 44 TQFP

DS89C430-ENL+ 16kB 44 TQFP

DS89C440-xxx

Contact factory or replace with

DS89C430 or DS89C450.

DS89C450-MNL

64kB 40 PDIP

DS89C450-MNL+ 64kB 40 PDIP

DS89C450-QNL 64kB 44 PLCC

DS89C450-QNL+ 64kB 44 PLCC

DS89C450-ENL 64kB 44 TQFP

DS89C450-ENL+ 64kB 44 TQFP

+ Denotes a lead(Pb)-free/RoHS-compliant device.

Complete Selector Guide appears at end of data sheet.

Pin Configurations appear at end of data sheet.

FEATURES

 High-Speed 8051 Architecture

One Clock-Per-Machine Cycle

DC to 33MHz Operation

Single Cycle Instruction in 30ns

Optional Variable Length MOVX to Access

Fast/Slow Peripherals

Dual Data Pointers with Automatic

Increment/Decrement and Toggle Select

Supports Four Paged Memory-Access Modes

 On-Chip Memory

16kB/64kB Flash Memory

In-Application Programmable

In-System Programmable Through Serial Port

1kB SRAM for MOVX

 80C52 Compatible

8051 Pin and Instruction Set Compatible

Four Bidirectional, 8-Bit I/O Ports

Three 16-Bit Timer Counters

256 Bytes Scratchpad RAM

 Power-Management Mode

Programmable Clock Divider

Automatic Hardware and Software Exit

 ROMSIZE Feature

Selects Internal Program Memory Size from

0 to 64kB

Allows Access to Entire External Memory Map

Dynamically Adjustable by Software

 Peripheral Features

Two Full-Duplex Serial Ports

Programmable Watchdog Timer

13 Interrupt Sources (Six External)

Five Levels of Interrupt Priority

Power-Fail Reset

Early Warning Power-Fail Interrupt

Electromagnetic Interference (EMI) Reduction

APPLICATIONS

Data Logging Telephones

White Goods HVAC

Building Energy

Control and

Management

Uninterruptible

Power Supplies

Automotive Test

Equipment

Industrial Control

and Automation

Motor Control Vending

Magstripe

Reader/Scanner

Gaming

Equipment

Programmable

Logic Controllers

Building Security

and Door Access

Control

Consumer

Electronics

Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C450

Summary of content (46 pages)

PAGE 1
LE AVAILAB DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers GENERAL DESCRIPTION FEATURES The DS89C430 and DS89C450 offer the highe st performance available in 8051-com patible microcontrollers. They feature ne wly designed processor cores that execute instructions up to 1 2 times faster than the original 8 051 at the same crystal speed. Typical a pplications will experience a speed improvement up to 10x.
PAGE 2
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………………-0.3V to (VCC + 0.5V) Voltage Range on VCC Relative to Ground…………………………………………………………………………………..-0.3V to +6.0V Ambient Temperature Range (under bias)…………………………………………………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………………………………………….
PAGE 3
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Note 1: Note 2: Note 3: Specifications to -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below that point. This indicates that there is a range of voltages [(VMIN to VRST (min)] where the processor's operation is not guaranteed, but the reset trip point has not been reached.
PAGE 4
DS89C430/DS89C450 AC CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.
PAGE 5
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 0 Address to Valid Instruction In Port 2 Address to Valid Instruction In PSEN Low to Port 0 Address Float RD Pulse Width (P3.7) (Note 16) WR Pulse Width (P3.6) (Note 16) RD (P3.
PAGE 6
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER Port 0 Address to Valid Data In (Note 16) Port 2 Address to Valid Data In (Note 16) SYMBOL 1-CYCLE 2-CYCLE 4-CYCLE PAGE MODE 1 PAGE MODE 1 PAGE MODE 1 MIN MIN MAX MAX MIN MAX PAGE MODE 2 MIN tAVDV0 tAVDV2 MAX NONPAGE MODE MIN MAX 3tCLCL - 20 3tCLCL - 20 + tSTC1 + tSTC1 tCLCL - 20 1.5tCLCL - 3.
PAGE 7
DS89C430/DS89C450 Ultra-High-Speed Flash Micrcontrollers Note 15: The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/ maximum external clock speed. The term “1/tCLCL” used in the AC Characteristics variable timing table is determined from the following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot exceed the rated speed of the device.
PAGE 8
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 2. Page Mode 1 Timing XTAL1 tCLCL tLHLL ALE tAVLL2 tPLPH tLLAX tLLAX3 PSEN tWHLH tLLAX2 tLLWL RD tRLRH WR tPXIX tRHDX tAVIV2 Port 0 MOVX MOVX tWLWH tAVWL2 tPLIV tRLDV OPCODE tWHQX tQVWX DATA DATA OPCODE tAVDV2 Port 2 LSB LSB LSB MSB LSB MSB LSB MSB LSB MSB Figure 3.
PAGE 9
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers EXTERNAL CLOCK CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN MAX UNITS Clock High Time tCHCX 10 ns Clock Low Time tCLCX 10 ns Clock Rise Time tCLCH 5 ns Clock Fall Time tCHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.
PAGE 10
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 4.
PAGE 11
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers POWER-CYCLE TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Crystal Startup Time (Note 18) tCSU 8 ms Power-On Reset Delay (Note 19) tPOR 65,536 tCLCL Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an 11.0592MHz crystal manufactured by Fox Electronics.
PAGE 12
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN DESCRIPTION PIN NAME FUNCTION PDIP PLCC TQFP 40 12, 44 6, 38 VCC 20 1, 22, 23, 34 16, 17, 28, 39 GND Logic Ground 9 10 4 RST External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wire-ORed external reset sources.
PAGE 13
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN DESCRIPTION (continued) PIN NAME PDIP PLCC TQFP 1 2 40 P1.0 2 3 41 P1.1 3 4 42 P1.2 4 5 43 P1.3 5 6 7 6 7 8 44 1 2 ALTERNATE FUNCTION P1.4 P1.0 T2 External I/O for Timer/Counter2 P1.1 T2EX Timer 2 Capture/Reload Trigger P1.5 P1.2 RXD1 Serial Port 1 Receive P1.6 9 3 P1.7 21 24 18 P2.0 (A8) 22 25 19 P2.1 (A9) 23 26 20 P2.2 (A10) 24 27 21 P2.3 (A11) 25 28 22 P2.4 (A12) 26 29 23 P2.
PAGE 14
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 5.
PAGE 15
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430 and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation.
PAGE 16
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers All standard SFR locations from the 8051 are duplicated in the DS89C430, and several SFRs have been added for the unique features of the DS89C430. Most of these features are controlled by bits in SFRs located in unused locations in the 8051 SFR map, allowing for increased functionality while maintaining complete instruction set compatibility. Table 1 shows the SFRs and their locations. Table 2 specifies the default reset condition for all SFR bits.
PAGE 17
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 1. SFR Register Map (continued) REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TH1 8Dh CKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0 P1 90h P1.7/INT5 P1.6/INT4 P1.5/INT3 P1.4/INT2 P1.3/TXD1 P1.2/RXD1 P1.1/T2EX P1.
PAGE 18
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 2.
PAGE 19
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 2.
PAGE 20
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 6.
PAGE 21
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Program Memory Access On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430 and through FFFFh (64kB) on the DS89C450. Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C430 to behave like a device with less on-chip memory.
PAGE 22
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers fetch that takes four clocks. Page mode 1 is the only external addressing mode where the CPU does not require stalls for external memory access, but page misses result in reduced external access performance. On-Chip Program Memory The processor can fetch the entire on-chip program memory range automatically. By default, the reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory.
PAGE 23
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers The signature bytes can be read in ROM loader mode or in parallel programming mode. Reading data from addresses 30h, 31h, and 60h provides signature information on manufacturer, part, and extension as follows: ADDRESS VALUE MEANING 30h DAh Manufacturer ID 31h 43h DS89C430 Device ID 31h 44h DS89C440 Device ID (Contact factory or replace with DS89C430 or DS89C450.
PAGE 24
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 4. In-Application Programming Commands FC3:FC0 COMMAND OPERATION 0000 Read Mode Default state. All flash blocks are in read mode. Note: The upper bank of flash memory is inaccessible for execution unless the FC3:0 bits are in the read mode (0000b) state. 0001 Verify Option Control Register Read data from the option control register. Data is available in the FDATA at the end of the following machine cycle. FDATA.
PAGE 25
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ROM Loader The full on-chip flash program memory space, security flash block, and external SRAM can be programmed insystem from an external source through serial port 0 under the control of a built-in ROM loader. The ROM loader also has an auto-baud feature that determines which baud-rate frequencies are being used for communication and sets the baud-rate generator for that speed.
PAGE 26
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External Memory The DS89C430 executes external memory cycles for code fetches and read/writes of external program and data memory. A nonpage external memory cycle is four times slower than the internal memory cycles (i.e., an external memory cycle contains four system clocks).
PAGE 27
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External Data Memory Interface in Nonpage Mode Operation Just like the program memory cycle, the external data memory cycle is four times slower than the internal data memory cycle in nonpage mode. A basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for nonpage mode operation.
PAGE 28
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 8. Nonpage Mode, External Data Memory Access (Stretch = 0, CD1:CD2 = 10) MOVX Instruction 1st Machine Cycle 2nd Machine Cycle XTAL1 ALE PSEN RD/WR Port 0 A Port 2 MOVX A INST A A DATA A MOVX Instruction Fetch Memory Access Stretch = 0 Figure 9.
PAGE 29
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Page Mode, External Memory Cycle Page mode retains the basic circuitry requirement for an original 8051 external memory interface, but alters the configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles. Additionally, the functions of ALE and PSEN are altered to support this mode of operation. Setting the PAGEE (ACON.7) bit to logic 1 enables page mode.
PAGE 30
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 10.
PAGE 31
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:    PSEN is asserted for both a page hit and a page miss for a full clock cycle. The execution of external MOVX instruction causes a page miss. A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction. Figure 10 shows the external memory cycle for this bus structure.
PAGE 32
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 7. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 00) MD2:MD0 STRETCH CYCLES RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11 000 0 0.25 0.5 1 1024 001 1 0.75 1.5 3 3072 010 2 1.75 3.5 7 7168 011 3 2.75 5.5 11 11,264 100 7 3.75 7.5 15 15,360 101 8 4.75 9.5 19 19,456 110 9 5.75 11.
PAGE 33
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 10. Page Mode 2, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 11) MD2:MD0 STRETCH CYCLES 000 RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11 0 0.
PAGE 34
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 12.
PAGE 35
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 13.
PAGE 36
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Interrupt Priority There are five levels of interrupt priority: Level 4 to 0. The highest interrupt priority is level 4, which is reserved for the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is enabled. All interrupts also have a natural hierarchy.
PAGE 37
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Timer/Counters The DS89C430 incorporates three 16-bit timers. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 12 summarizes the timer functions. Timers 0 and 1 both have three modes of operations. They can each be used as a 13-bit timer/counter, a 16-bit timer/counter, or an 8-bit timer/counter with autoreload.
PAGE 38
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers during the three machine cycles following the writing of the 55h. Writing to a timed-access-protected bit outside of these three machine cycles has no effect on the bit. The timed-access process is address, data, and time dependent. A processor running out of control and not executing system software statistically is not able to perform this timed sequence of steps, and as such, does not accidentally alter the protected bits.
PAGE 39
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 14. System Clock Sources 4X/2X CTM CLOCK MULTIPLIER CRYSTAL OSCILLATOR MUX DIVIDE 1024 SYSTEM CLOCK RING OSCILLATOR RING ENABLE CD0 SELECTOR CD1 Bandgap-Monitored Interrupt and Reset Generation The power monitor in the DS89C430 monitors the VCC pin in relation to the on-chip bandgap voltage reference. Whenever VCC falls below VPFW, an interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI (WDCON.
PAGE 40
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Watchdog Timer The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 217 of the crystal oscillator clock, with the watchdog reset set to time out 512 system clock cycles later. This results in a 33MHz crystal oscillator producing an interrupt timeout every 3.9718ms, followed 15.5µs later by a watchdog reset.
PAGE 41
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External/Hardware Reset A hardware reset can be initiated by asserting the RST pin high for at least three external clock cycles while the external clock is running. The reset is asserted immediately. When the RST pin is taken to a logic low, the microcontroller exits the reset state within a delay that depends on the state of the flash memory at the time the reset was asserted.
PAGE 42
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation.
PAGE 43
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Stop Mode Stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. Stop mode is invoked by setting the stop bit (PCON.1) to logic 1. The processor enters stop mode on the instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are enabled.
PAGE 44
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SELECTOR GUIDE PART DS89C430-MNL DS89C430-MNL+ DS89C430-QNL DS89C430-QNL+ DS89C430-ENL DS89C430-ENL+ DS89C430-MNG DS89C430-MNG+ DS89C430-QNG DS89C430-QNG+ DS89C430-ENG DS89C430-ENG+ DS89C440-xxx DS89C450-MNL DS89C450-MNL+ DS89C450-QNL DS89C450-QNL+ DS89C450-ENL DS89C450-ENL+ DS89C450-MNG DS89C450-MNG+ DS89C450-QNG DS89C450-QNG+ DS89C450-ENG DS89C450-ENG+ TEMP RANGE FLASH MEMORY SIZE MAX CLOCK SPEED (MHz) PIN-PACKAGE -40°C to +85°C 16kB x 8 33 4
PAGE 45
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN CONFIGURATIONS TOP VIEW 1 6 40 7 39 DS89C430 DS89C450 17 P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 29 18 PLCC 33 34 28 23 22 DS89C430 DS89C450 44 12 1 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 10 DS89C430 31 11 DS89C450 30 29 12 28 13 27 14 26 15 25 16 24 17 23 18 22 19 21 20 VCC P0.0 P0.1 P0.
PAGE 46
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers REVISION HISTORY DATE 111003 DESCRIPTION New product release. DC Electrical Characteristics table: Corrected typo—Under Supply Current for Active and Idle Mode, changed Units from “A” to “mA.” 032204 Note 15: Changed number of external clock cyles per system clock and minimum external clock speeds. Flash Memory Programming Characteristics table: Removed Note 20 (room temperature only) from the Data Retention parameter.