9-3280; Rev 5; 2/12 KIT ATION EVALU E L B A AVAIL 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Features The MAX1020/MAX1022/MAX1057/MAX1058 integrate a multichannel, 10-bit, analog-to-digital converter (ADC) and an octal, 10-bit, digital-to-analog converter (DAC) in a single IC. These devices also include a temperature sensor and configurable general-purpose I/O ports (GPIOs) with a 25MHz SPI-/QSPI™-/MICROWIRE®-compatible serial interface.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V DVDD to AVDD......................................................-3.0V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND ........................-0.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (V AVDD = V DVDD = 2.7V to 3.6V (MAX1057), external reference V REF = 2.5V (MAX1057), V AVDD = V DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 0.3 0.2 0.1 0.4 0.3 0.2 0.1 MAX1020/MAX1022/MAX1058 0 4.875 5.000 5.125 0.1 MAX1057 0 2.7 3.0 3.3 3.6 -40 -15 10 35 60 TEMPERATURE (°C) ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE -0.1 0.1 0 -0.1 -0.2 -0.3 0.1 0 -0.1 -0.2 MAX1020/MAX1022/MAX1058 -0.3 512 0.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1057), external VREF = 2.5V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX1057 0.25 GAIN ERROR (LSB) GAIN ERROR (LSB) 0.25 0 0 -0.5 -0.25 -1.0 MAX1020/MAX1022/MAX1058 -0.50 4.750 4.875 5.000 5.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE 0 -0.1 -0.2 0.1 0 -0.1 -0.2 MAX1020/MAX1022/MAX1058 512 768 0 512 768 1024 1023 1026 1029 1032 1035 OUTPUT CODE DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE 0.15 0.10 0.05 0.4 0.3 0.2 0.1 MAX1057 EXTERNAL REFERENCE = 2.5V MAX1020/MAX1022/MAX1058 EXTERNAL REFERENCE = 4.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1057), external VREF = 2.5V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE DAC FULL-SCALE ERROR vs. LOAD CURRENT -1.5 -2.0 -2.5 -1 -2 -3 MAX1057 1.0 1.5 2.0 2.5 10 15 20 25 30 0 0.5 1.0 1.5 2.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports -40 -80 -100 -60 -100 -120 -140 -140 -140 -160 50 100 150 200 100 200 150 0 50 100 DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT SOURCING 1.27 1.26 1.25 1.24 SINKING 1.23 SOURCING 1.22 DAC OUTPUT = MIDSCALE MAX1020/MAX1022/MAX1058 2.00 GPIO OUTPUT VOLTAGE (V) SINKING 2.02 1.28 DAC OUTPUT VOLTAGE (V) 2.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1057), external VREF = 2.5V (MAX1057), VAVDD = VDVDD = 5V (MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DAC-TO-DAC CROSSTALK RLOAD = 10kΩ, CLOAD = 100pF DAC-TO-DAC CROSSTALK RLOAD = 10kΩ, CLOAD = 100pF TEMPERATURE SENSOR ERROR vs.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) NEGATIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) MAX1020 toc55 MAX1020 toc57 MAX1020 toc56 MAX1057 SCLK 2V/div SCLK 1V/div VOUT 100mV/div AC-COUPLED MAX1057 VOUT 1V/div VOUT 100mV/div AC-COUPLED VLDAC 1V/div MAX1020/MAX1022/MAX1058 200ns 200ns 1µs NEGAT
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description MAX1020 MAX1022 MAX1057/ MAX1058 1, 2 — — 3 3 4 EOC 4 4 7 DVDD Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor. 5 5 8 DGND Digital Ground. Connect DGND to AGND. 6 6 9 DOUT Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in modes 00, 01, and 10.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1020 MAX1022 MAX1057/ MAX1058 NAME FUNCTION Reference 1 Input. Reference voltage; leave unconnected to use the internal reference (2.5V for the MAX1057 or 4.096V for the MAX1020/MAX1022/MAX1058). REF1 is the positive reference in ADC external differential reference mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Detailed Description The MAX1020/MAX1022/MAX1057/MAX1058 integrate a multichannel, 10-bit ADC and an octal, 10-bit DAC in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI-/ QSPI-/MICROWIRE-compatible serial interface. The ADC is available in 8/12/16 input-channel versions. The octal DAC outputs settle within 2.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports USER-PROGRAMMABLE I/O MAX1020/MAX1022/MAX1057/MAX1058 AVDD GPIOA0– GPIOB0– GPIOC0– GPIOA3 GPIOB3 GPIOC3 DVDD MAX1057 MAX1058 GPIO CONTROL OSCILLATOR INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT0 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT1 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT2 INPUT REGISTER DAC REGISTER 10-BIT DAC BUF
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 1.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Analog Input (T/H) The equivalent circuit of Figure 2 shows the ADC input architecture of the MAX1020/MAX1022/MAX1057/ MAX1058. In track mode, a positive input capacitor is connected to AIN0–AIN15 in single-ended mode and AIN0, AIN2, and AIN4–AIN14 (only positive inputs) in differential mode.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports The first 2 bytes of data read out after a temperature measurement always contain the 12-bit temperature result, preceded by four leading zeros, MSB first. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports The GPIOs can sink and source current. The MAX1057/MAX1058 GPIOA0–GPIOA3 can sink and source up to 15mA. GPIOB0–GPIOB3 and GPIOC0– GPIOC3 can sink 4mA and source 2mA. The MAX1020 GPIOA0 and GPIOA1 can sink and source up to 15mA. The MAX1020 GPIOC0 and GPIOC1 can sink 4mA and source 2mA. See Table 3. erence. Set REFSEL[1:0] = 11 to program the ADC for external differential reference mode.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Conversion Register Select active analog input channels, scan modes, and a single temperature measurement per scan by issuing a command byte to the conversion register. Table 4 details channel selection, the four scan modes, and how to request a temperature measurement.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT — 7 (MSB) Set to zero to select setup register. FUNCTION — 6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference-mode configuration. REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports If any of the above conditions exist, the ADC reference is always on, but there is a 188 clock-cycle delay before temperature-sensor measurements begin, if requested. Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. FUNCTION UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Configure AIN8 and AIN9 for unipolar differential conversion.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register. Hold CS low and run 16 SCLK cycles before pulling CS high. If the last 2 bits of the setup register are 00 or 01, neither the unipolar-mode register nor the bipolar-mode register is written. Any subsequent byte is recognized as a new command byte.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Select Register Write a command byte 0001XXXX to the DAC select register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command byte controls the DAC serial interface. See Table 20 and the DAC Serial Interface section.
CS rising edge. All GPIOs default to inputs upon powerup. GPIO Write Write the command byte 00000010 to indicate a GPIO write operation. The eight SCLK cycles following the command byte load data from DIN into the GPIO write register in the MAX1020. The 16 SCLK cycles following the command byte load data from DIN into the GPIO write register in the MAX1057/MAX1058. See Tables 15 and 16. The register bits are updated after the last CS rising edge.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Serial Interface Write a command byte 0001XXXX to the DAC select register to indicate the word to follow is written to the DAC serial interface, as detailed in Tables 1, 10, 20, and 21. Write the next 16 bits to the DAC interface register, as shown in Tables 20 and 21. Following the high-to-low transition of CS, the data is shifted synchronously and latched into the input register on each falling edge of SCLK.
Table 20. DAC Serial-Interface Configuration 16-BIT SERIAL WORD MSB LSB CONTROL BITS DESCRIPTION DATA BITS C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 X X X X X X X X X X X X X X NOP FUNCTION No operation. X X X X X X X X X RESET 0 0 0 1 1 X X X X X X X X X X X Pull-High Preset all internal registers to FFFh and leave output buffers in their present state.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CONTROL BITS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 C3 C2 C1 C0 DATA BITS DESCRIPTION FUNCTION D3 D2 D1 D0 — — — — — — — — 0 — — — — — — — — 0 — — — — — — — — 1 — — — — — — — — 0 — — — — — — — — 1 0 1 0 0 1 1 0 0 0 1 X Power-Up Power up individual DAC buffers indicated by data in DAC0 through DAC7.
Applications Information Internally Timed Acquisitions and Conversions Using CNVST ADC Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequence is initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 6 for clock mode 00 timing after a command byte is issued. See Table 5 for details on programming the clock mode in the setup register.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 tRDS EOC X = DON'T CARE. Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion. tCSW CNVST (CONVERSION 2) (ACQUISITION 1) (ACQUISITION 2) CS tDOV SCLK (CONVERSION 1) DOUT MSB1 LSB1 MSB2 EOC X = DON'T CARE. Figure 7.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DIN (CONVERSION BYTE) (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 tDOV LSB1 MSB2 EOC X = DON'T CARE. Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required). version. However, coupled noise may result in degraded ADC SNR.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (ACQUISITION1) (CONVERSION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC X = DON'T CARE. Figure 9.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports tCL SCLK 1 tDS 2 3 D13 D14 D12 D11 D0 D1 tDOT tDOE D15 D7 DOUT 32 16 8 5 4 tDH D15 DIN tCH D14 D6 D13 D5 tDOD D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10) DAC/GPIO Timing Figures 10–13 detail the timing diagrams for writing to the DAC and GPIOs.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1020/MAX1022/MAX1057/MAX1058 tCH tCL SCLK 1 2 3 32 16 8 5 4 tDH tDS D15 DIN D14 D13 D12 D11 D1 D0 tDOE tDOT D15 D7 DOUT D14 D6 tDOD D13 D5 D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 11.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CS tGOD GPIO INPUT/OUTPUT tGSU Figure 13. GPIO Timing tLDACPWL LDAC tS ±1 LSB OUT_ Figure 14. LDAC Functionality LDAC Functionality Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently low to make the DAC register transparent. The DAC output typically settles from zero to full scale within ±1 LSB after 2µs. See Figure 14.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD(dB) = 20 x log (SignalRMS / NoiseRMS) Bipolar ADC Offset Error While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Full-Power Bandwidth DAC Power-Supply Rejection A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports + 28 29 30 31 AIN7 N.C. AIN6 AIN5 AIN4 AIN3 33 32 AIN9 AIN8 35 34 REF2/AIN10 36 28 29 30 31 N.C. N.C. AIN4 AIN3 AIN2 AIN1 33 32 REF2/AIN6 AIN5 35 34 CNVST/AIN7 36 + AIN0 REF1 GPIOA0 GPIOA1 1 27 2 26 EOC DVDD DGND DOUT 3 25 4 24 SCLK DIN OUT0 7 21 8 20 GPIOC1 GPIOC0 N.C. RES_SEL CS LDAC 9 19 OUT7 5 23 3 25 4 24 SCLK DIN OUT0 7 21 8 20 AIN1 N.C.
MAX1020/MAX1022/MAX1057/MAX1058 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 5/04 Initial release — 4 3/08 Changed timing characteristic specification 7 5 2/12 Removed A and B grade, updated style. 1–8, 16, 19, 21, 22, 40, 42, 43 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.