9-3294; Rev 3; 3/08 KIT ATION EVALU E L B AVAILA 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Features The MAX1040/MAX1042/MAX1046/MAX1048 integrate a multichannel, 10-bit, analog-to-digital converter (ADC) and a quad, 10-bit, digital-to-analog converter (DAC) in a single IC. The devices also include a temperature sensor and configurable general-purpose I/O ports (GPIOs) with a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial interface.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ABSOLUTE MAXIMUM RATINGS Maximum Current into OUT_.............................................100mA Continuous Power Dissipation (TA = +70°C) 36-Pin Thin QFN (6mm x 6mm) (derate 26.3mW/°C above +70°C) ..........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ..
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1040/MAX1042/MAX1046/MAX1048 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1040/MAX1042/MAX1046/MAX1048 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.066 4.096 4.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.
Typical Operating Characteristics (AVDD = DVDD = 5V, external VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ANALOG SHUTDOWN CURRENT vs. TEMPERATURE 0.3 0.2 0.1 0 4.875 5.000 5.125 0.2 0.1 MAX1040 toc03 0.2 0.1 0 -0.1 -0.2 -0.3 -40 5.250 -15 10 35 60 85 0 256 512 TEMPERATURE (°C) OUTPUT CODE ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE ADC OFFSET ERROR vs.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ANALOG SUPPLY CURRENT vs. SAMPLING RATE 1.5 1.0 0.5 1.96 1.94 100 150 200 250 1.90 4.750 300 SAMPLING RATE (ksps) DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.1 0 -0.1 -0.2 256 512 768 -15 10 35 60 0 -0.05 0.25 0.20 0.15 0.10 0.05 0 1023 1026 1029 1032 1035 4.750 1038 4.875 5.000 5.125 5.
Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, external VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) 4.09 4.08 35 60 85 24.86 24.84 4.750 5.000 MAX1040 toc22 0 5.125 -40 5.250 -40 -80 -100 -40 -60 -80 -100 -60 -80 -140 -140 -160 -160 150 200 0 150 0 200 50 100 150 ANALOG INPUT FREQUENCY (kHz) DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT GPIO OUTPUT VOLTAGE vs.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports TEMPERATURE SENSOR ERROR vs. TEMPERATURE MAX1040 toc30 MAX1040 toc29 MAX1040 toc28 1.00 TEMPERATURE SENSOR ERROR (°C) DYNAMIC RESPONSE RISE TIME RLOAD = 10kΩ, CLOAD = 100pF DAC-TO-DAC CROSSTALK RLOAD = 10kΩ, CLOAD = 100pF 0.75 0.50 VOUTA 2V/div CS 2V/div VOUTB 10mV/div AC-COUPLED VOUT 2V/div 0.25 0 -0.25 -0.50 -0.75 -1.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description PIN NAME FUNCTION MAX1040 MAX1042 MAX1046 MAX1048 1, 2, 16–19, 24, 25 16–19 1, 2, 16–19, 24, 25, 31, 34 16–19, 31, 34 D.C. Do Not Connect. Do not connect to this pin. 3 3 3 3 EOC Active-Low End-of-Conversion Output. Data is valid after the falling edge of EOC. 4 4 4 4 DVDD Digital Positive Power Input. Bypass DVDD to DGND with a 0.1µF capacitor.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports PIN MAX1040 22 MAX1042 22 MAX1046 22 MAX1048 22 NAME FUNCTION RES_SEL Reset Select. Selects DAC wake-up mode. Set RES_SEL low to wake up the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs with a 100kΩ resistor to VREF. Set RES_SEL high to power up the DAC input register to FFFh. Set RES_SEL low to power up the DAC input register to 000h. Reference 1 Input. Reference voltage.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Detailed Description The MAX1040/MAX1042/MAX1046/MAX1048 integrate a multichannel 10-bit ADC and a quad 10-bit DAC in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI/QSPI-/MICROWIRE-compatible serial interface. The ADC is available in a 4 or an 8 input-channel version. The four DAC outputs settle within 2.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports USER-PROGRAMMABLE I/O MAX1040/MAX1042/MAX1046/MAX1048 AVDD GPIOC0, GPIOC1 GPIOA0, GPIOA1 DVDD MAX1042 GPIO CONTROL OSCILLATOR INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT0 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT1 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONING OUT2 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER OUTPUT CONDITIONI
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 1.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Analog Input (T/H) The equivalent circuit of Figure 2 shows the ADC input architecture of the MAX1040/MAX1042/MAX1046/ MAX1048. In track mode, a positive input capacitor is connected to AIN0–AIN7 in single-ended mode and AIN0, AIN2, AIN4, and AIN6 in differential mode. A negative input capacitor is connected to AGND in single-ended mode or AIN1, AIN3, AIN5, and AIN7 in differential mode.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Celsius (two’s complement), at a resolution of 8 LSB per degree. See the Temperature Measurements section for details on converting the digital code to a temperature. 10-Bit DAC In addition to the 10-bit ADC, the MAX1040/MAX1042/ MAX1046/MAX1048 also include four voltage-output, 10-bit, monotonic DACs with less than 1 LSB integral nonlinearity error and less than 0.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Clock Modes Internal Clock The MAX1040/MAX1042/MAX1046/MAX1048 can operate from an internal oscillator. The internal oscillator is active in clock modes 00, 01, and 10. Figures 6, 7, and 8 show how to start an ADC conversion in the three internally timed conversion modes. Read out the data at clock speeds up to 25MHz through the SPI interface.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports and 7 for timing specifications for starting a scan with CNVST. A conversion is not performed if it is requested on a channel or one of the channel pairs that has been configured as CNVST or REF2. For channels configured as differential pairs, the CHSEL0 bit is ignored and the two pins are treated as a single differential channel. For the MAX1046/MAX1048, the CHSEL2 bit must be zero.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT FUNCTION — 7 (MSB) Set to zero to select setup register. — 6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference-mode configuration. REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 5c. Clock Mode 11 REFSEL1 REFSEL0 0 0 VOLTAGE REFERENCE OVERRIDE CONDITIONS AIN Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 external conversion clock cycles. Temperature Internal reference required. There is a programmed delay of 244 external conversion clock cycles for the internal reference.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. FUNCTION UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion (MAX1040/MAX1042). Set UCH4/5 to 0 on the MAX1046/MAX1048. UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion (MAX1040/MAX1042).
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Select Register Write a command byte 0001XXXX to the DAC select register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command Table 10. DAC Select Register BIT NAME — BIT FUNCTION 7 (MSB) Set to zero to select DAC select register.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Serial Interface Write a command byte 0001XXXX to the DAC select register to indicate the word to follow is written to the DAC serial interface, as detailed in Tables 1, 10, 17, and 18. Write the next 16 bits to the DAC interface register, as shown in Tables 17 and 18.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 16-BIT SERIAL WORD MSB LSB CONTROL DATA BITS BITS C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 X X X X X X X X X X DESCRIPTION X X X X NOP FUNCTION No Operation. Reset all internal registers to 000h and leave output buffers in their present state. Preset all internal registers to FFFh and leave output buffers in their present state.
Table 18.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Internally Timed Acquisitions and Conversions Using CNVST ADC Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequence is initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 6 for clock mode 00 timing after a command byte is issued.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 tRDS EOC Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion. tCSW CNVST (CONVERSION 2) (ACQUISITION 1) (ACQUISITION 2) CS tDOV SCLK (CONVERSION 1) DOUT MSB1 LSB1 MSB2 EOC Figure 7.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (CONVERSION BYTE) (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 tDOV LSB1 MSB2 EOC Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required). version. However, coupled noise may result in degraded ADC SNR. If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (CONVERSION BYTE) DIN (ACQUISITION1) (CONVERSION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC X = DON'T CARE. Figure 9.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports SCLK 1 tDS 2 3 D13 D14 D12 D11 D1 D0 tDOT tDOE D15 D7 DOUT 32 16 8 5 4 tDH D15 DIN tCH D14 D6 D13 D5 tDOD D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10) DAC/GPIO Timing Figures 10–13 detail the timing diagrams for writing to the DAC and GPIOs. Figure 10 shows the timing specifications for clock modes 00, 01, and 10.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports tCH tCL SCLK 1 2 3 32 16 8 5 4 tDH tDS D15 DIN D14 D13 D12 D11 D1 D0 tDOT tDOE D15 D7 DOUT D14 D6 tDOD D13 D5 D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 11.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports tGOD tGSU GPIO INPUT/OUTPUT Figure 13. GPIO Timing tLDACPWL LDAC tS ±1 LSB OUT_ Figure 14. LDAC Functionality LDAC Functionality Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently low to make the DAC register transparent. The DAC output typically settles from zero to full scale within ±1 LSB after 2µs. See Figure 14.
MAX1040/MAX1042/MAX1046/MAX1048 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar ADC Offset Error Signal-to-Noise Plus Distortion For an ideal converter, the first transition occurs at 0.5 LSB, above zero. Offset error is the amount of deviation between the measured first transition point and the ideal first transition point.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Power-Supply Rejection DAC PSR is the amount of change in the converter’s value at full-scale as the power-supply voltage changes from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the powersupply voltage. DAC Digital Feedthrough DAC digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 36 35 34 33 32 31 30 29 28 AIN1 AIN2 AIN3 AIN4 N.C. N.C. AIN5 36 35 34 33 32 31 30 29 28 D.C. 1 27 AIN0 GPIOA0 1 27 AIN0 D.C. 2 26 REF1 GPIOA1 2 26 REF1 EOC 3 25 D.C. EOC 3 25 GPIOC1 DVDD 4 24 D.C. DVDD 4 24 GPIOC0 DGND 5 23 N.C. DGND 5 DOUT 6 22 RES_SEL DOUT 6 22 RES_SEL SCLK 7 21 CS SCLK 7 21 CS MAX1040 DIN 8 20 LDAC OUT0 9 DIN 8 20 LDAC OUT0 9 D.C. D.C. D.C. N.C.
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports REVISION NUMBER REVISION DATE 4 3/08 DESCRIPTION Changed timing characteristic specification PAGES CHANGED 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
