Datasheet

MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
38 ______________________________________________________________________________________
t
CSH
SCLK
DIN
DOUT
CS
1234
32
16
8
D15
D14
D13 D12 D11
5
D15
D7
D14
D6
D13
D5
D12
D4
D0
D1
D0
t
DOD
t
DOT
t
CSS
t
CSPWH
D1
t
DOE
t
DS
t
DH
t
CH
t
CL
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t
S
is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.