Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal TQFP 80 EP

General Description

The MAX105 is a dual, 6-bit, analog-to-digital converter

(ADC) designed to allow fast and precise digitizing of

in-phase (I) and quadrature (Q) baseband signals. The

MAX105 converts the analog signals of both I and Q

components to digital outputs at 800Msps while achiev-

ing a signal-to-noise ratio (SNR) of typically 37dB with

an input frequency of 200MHz, and an integral nonlin-

earity (INL) and differential nonlinearity (DNL) of ±0.25

LSB. The MAX105 analog input preamplifiers feature a

400MHz, -0.5dB, and a 1.5GHz, -3dB analog input

bandwidth. Matching channel-to-channel performance

is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees

phase. Dynamic performance is 36.4dB signal-to-noise

plus distortion (SINAD) with a 200MHz analog input sig-

nal and a sampling speed of 800MHz. A fully differen-

tial comparator design and encoding circuits reduce

out-of-sequence errors, and ensure excellent

metastable performance of only one error per 10

clock

cycles.

In addition, the MAX105 provides LVDS digital outputs

with an internal 6:12 demultiplexer that reduces the out-

put data rate to one-half the sample clock rate. Data is

output in two’s complement format. The MAX105 oper-

ates from a +5V analog supply and the LVDS output

ports operate at +3.3V. The data converter’s typical

power dissipation is 2.6W. The device is packaged in

an 80-pin, TQFP package with exposed paddle, and is

specified for the extended (-40°C to +85°C) tempera-

ture range. For a lower-speed, 400Msps version of the

MAX105, please refer to the MAX107 data sheet.

Applications

VSAT Receivers

WLANs

Test Instrumentation

Communications Systems

Features

♦ Two Matched 6-Bit, 800Msps ADCs

♦ Excellent Dynamic Performance

36.4dB SINAD at f

≈ 200MHz and

CLK

≈ 800MHz

♦ Typical INL and DNL: ±0.25LSB

♦ Channel-to-Channel Phase Matching: ±0.2°

♦ Channel-to-Channel Gain Matching: ±0.04dB

♦ 6:12 Demultiplexer reduces the Data Rates to

400MHz

♦ Low Error Rate: 10

Metastable States at

800Msps

♦ LVDS Digital Outputs in Two’s Complement

Format

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

________________________________________________________________ Maxim Integrated Products 1

REF

PRIMARY

PORT

AUXILIARY

PORT

PRIMARY

PORT

AUXILIARY

PORT

I ADC

Q ADC

MAX107

Block Diagram

19-2006; Rev 0; 5/01

Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX105ECS -40°C to +85°C 80-Pin TQFP-EP

Pin Configuration appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Summary of content (21 pages)

PAGE 1
9-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter’s typical power dissipation is 2.6W.
PAGE 2
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier ABSOLUTE MAXIMUM RATINGS AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V OVCCI and OVCCQ to OGND ...................................-0.3V to +4V AGND to OGND ................................................... -0.3V to +0.3V P0I± to P5I± and A0I± to A5I± DREADY+, DREADY- to OGNDI .............-0.3V to OVCCI+0.3V P0Q± to P5Q±, A0Q± to A5Q± DOR+ and DOR- to OGNDQ ................-0.3V to OVCCQ+0.3V REF to AGNDR...............
PAGE 3
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted.
PAGE 4
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier ELECTRICAL CHARACTERISTICS (continued) (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) PARAMETER Signal-to-Noise Plus Distortion Ratio SYMBOL CONDITIONS fIN = 200.018MHz at -0.
PAGE 5
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL= 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted.
PAGE 6
Typical Operating Characteristics (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted.
PAGE 7
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier 40 fIN = 199.8535MHz 36 -34 MAX105 toc11 fIN = 199.8535MHz fIN = 199.8535MHz -38 32 28 THD (dB) SINAD (dB) 36 32 -46 28 24 -8 -7 -6 -5 -4 -3 -2 -1 -50 24 0 -10 -9 ANALOG INPUT POWER (dB FS) -8 -7 -6 -5 -4 -3 -2 -1 -10 -9 0 SFDR vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT SNR vs. TEMPERATURE 45 MAX105 toc13 50 fIN = 199.8535MHz 48 fIN = 199.
PAGE 8
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier Typical Operating Characteristics (continued) (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) -43 AMPLITUDE (dB) 38 fIN = 202.346MHz 36 34 32 6.0 fIN = 202.0761MHz 5.
PAGE 9
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier PIN NAME FUNCTION 1, 20 T.P. Test Point. Do not connect. 2 REF Reference Output 3 AVCCR Analog Reference Supply. Supply voltage for the internal bandgap reference. Bypass to AGNDR with 0.01µF in parallel with 47pF for proper operation. 4 AGNDR Reference, Analog Ground. Connect to AGND for proper operation. 5, 8 AGNDI I-Channel, Analog Ground. Connect to AGND for proper operation. 6 INI- I-Channel, Differential Input.
PAGE 10
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105 Pin Description (continued) 10 PIN NAME FUNCTION 31 A3Q+ Auxiliary Output Data Bit 3, Q-Channel 32 A3Q- Complementary Auxiliary Output Data Bit 3, Q-Channel 33 P3Q+ Primary Output Data Bit 3, Q-Channel 34 P3Q- Complementary Primary Output Data Bit 3, Q-Channel 37 A2Q+ Auxiliary Output Data Bit 2, Q-Channel 38 A2Q- Complementary Auxiliary Output Data Bit 2, Q-Channel 39 P2Q+ Primary Output Data Bit 2, Q-Channel
PAGE 11
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier PIN NAME FUNCTION 62 P2I+ Primary Output Data Bit 2, I-Channel 63 A2I- Complementary Auxiliary Output Data Bit 2, I-Channel 64 A2I+ Auxiliary Output Data Bit 2, I-Channel 65, 72 OVCCI I-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to OGND with 0.01µF in parallel with 47pF for proper operation. 66, 71 OGNDI I-Channel Outputs, Digital Ground.
PAGE 12
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier DREADY+/DREADY- MAX105 INI+ I ADC PRE-AMP INI- REF 2kΩ PRIMARY DATA PORT P0I-P5I P0I+/P0I- AUXILIARY DATA PORT A0I-A5I A0I+/A0I- P5I+/P5I- A5I+/A5IAVCC CM BUFFER 10kΩ 1:2 CLK+ REFERENCE CLK10kΩ DOR 2kΩ CM BUFFER REF Q ADC INQ+ PRE-AMP PRIMARY DATA PORT P0Q-P5Q P0Q+/P0Q- AUXILIARY DATA PORT A0Q-A5Q A0Q+/A0Q- P5Q+/P5Q- INQ- REF A5Q+/A5Q- DOR+/DOR- Figure 1.
PAGE 13
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier IN-PHASE INPUTS (INI+, INQ+) INVERTED INPUTS (INI-, INQ-) OUT-OF-RANGE BIT (DOR+, DOR-) OUTPUT CODE > +400mV + VREF AC – Coupled to AGND_ 1 011111 +400mV - 0.5LSB + VREF AC – Coupled to AGND_ 0 011111 0V + VREF AC – Coupled to AGND_ 0 000000/111111 -400mV + 0.5LSB + VREF AC – Coupled to AGND_ 0 100000 < -400mV + VREF AC – Coupled to AGND_ 1 100000 MAX105 Table 1.
PAGE 14
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier AGND 50Ω 100pF CLK+, INI+, INQ+ D 0° Differential Clock (Sine-Wave Drive) The advantages of differential clock drive (Figure 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. Refer to Single-Ended Clock Inputs (Sine-Wave Drive) for proper input amplitude requirements.
PAGE 15
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105 ADC SAMPLE MAX105 ADCs SAMPLE ON THE RISING EDGE OF CLK+ CLK- N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 CLK CLK+ DREADYDREADY DREADY+ AUXILIARY DATA PORT N N+2 N+4 N+6 N+8 N+10 PRIMARY DATA PORT N+1 N+3 N+5 N+7 N+9 N+11 NOTE: THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK CYCLES.
PAGE 16
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier DREADY+/DREADYFROM PREVIOUS STAGE MAX2108 PRIMARY DATA PORT P0I-P5I QUADRATURE DEMODULATOR NYQUIST FILTER I ADC PRE-AMP AUXILIARY DATA PORT A0I-A5I REF 2kΩ AVCC CM BUFFER 10kΩ 1:2 LO D S P REFERENCE 90° 10kΩ DOR 2kΩ NYQUIST FILTER CM BUFFER PRE-AMP PRIMARY DATA PORT P0Q-P5Q REF Q ADC AUXILIARY DATA PORT A0Q-A5Q DOR+/DOR- Figure 8.
PAGE 17
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105 PC BOARD AVCC 10µF 10nF PC BOARD AGND FERRITE-BEAD SUPPRESSORS PC BOARD OVCC OVCCI, OVCCQ 10µF 10nF 10nF 47pF 4 x 10nF PC BOARD OGND AVCCR OVCCI AVCCR OVCCI 47pF AGNDR 10nF OGNDI AGNDR OGNDI AVCCI AVCCI 10nF MAX105 OVCCI OVCCI 47pF 47pF AGNDI 10nF OGNDI OGNDI AGNDI AVCCQ AVCCQ 10nF OVCCQ 47pF OVCCQ 47pF AGNDQ OGNDQ AVCC OVCCQ 10nF AGNDQ OGNDQ AVCC 10nF 47pF OVCCQ 47pF AGND AGND 10nF OGNDQ OGN
PAGE 18
MAX105 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier DIE 80-PIN TQFP PACKAGE WITH EXPOSED PAD BONDING WIRE EXPOXY THERMAL LAND COPPER PLANE, 1oz. EXPOSED PAD COPPER TRACE, 1oz. PC BOARD COPPER TRACE, 1oz. TOP LAYER GROUND PLANE AGND, DGND POWER PLANE GROUND PLANE (AGND) 6 x 6 ARRAY OF THERMAL VIAS THERMAL LAND COPPER PLANE, 1oz. MAX105 Figure 10.
PAGE 19
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier CLK+ tAW MAX105 ANALOG INPUT THD = 20 x log (V22 + V32 + V4 2 + V52 ) / V12 ) tAD tAJ SAMPLING INSTANT tAW: APERTURE WIDTH tAJ: APERTURE JITTER tAD: APERTURE DELAY Figure 11. Aperture Timing clock design limits aperture jitter to typically 1.5psRMS. Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
PAGE 20
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier 20 61 P2I- 62 P2I+ 63 A2I- 64 A2I+ 65 OVCCI 66 OGNDI 67 P3I- 68 P3I+ 69 A3I- 70 A3I+ 71 OGNDI 72 OVCCI 73 P4I- 74 P4I+ 75 A4I- 76 A4I+ 77 P5I- 78 P5I+ 79 A5I- 80 A5I+ MAX105 Pin Configuration T.P.
PAGE 21
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.