Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 28

General Description

The MAX1061/MAX1063 low-power, 10-bit analog-to-

digital converters (ADCs) feature a successive-approxi-

mation ADC, automatic power-down, fast wake-up

(2µs), an on-chip clock, +2.5V internal reference, and a

high-speed, byte-wide parallel interface. They operate

with a single +3V analog supply and feature a V

LOGIC

pin that allows them to interface directly with a +1.8V to

+3.6V digital supply.

Power consumption is only 5.7mW (V

= V

LOGIC

) at

the maximum sampling rate of 250ksps. Two software-

selectable power-down modes enable the MAX1061/

MAX1063 to be shut down between conversions;

accessing the parallel interface returns them to normal

operation. Powering down between conversions can

cut supply current to under 10µA at reduced sampling

rates.

Both devices offer software-configurable analog inputs

for unipolar/bipolar and single-ended/pseudo-differen-

tial operation. In single-ended mode, the MAX1061 has

eight input channels and the MAX1063 has four input

channels (four and two input channels, respectively,

when in pseudo-differential mode).

Excellent dynamic performance and low power, com-

bined with ease of use and small package size, make

these converters ideal for battery-powered and data-

acquisition applications or for other circuits with demand-

ing power consumption and space requirements.

The MAX1061 is available in a 28-pin QSOP package,

while the MAX1063 is available in a 24-pin QSOP. For

pin-compatible +5V, 10-bit versions, refer to the

MAX1060/MAX1064 data sheet.

Applications

Industrial Control Systems Data Logging

Energy Management Patient Monitoring

Data-Acquisition Systems Touch Screens

Features

♦ 10-Bit Resolution, ±0.5 LSB Linearity

♦ +3V Single-Supply Operation

♦ User-Adjustable Logic Level (+1.8V to +3.6V)

♦ Internal +2.5V Reference

♦ Software-Configurable, Analog Input Multiplexer

8-Channel Single Ended/

4-Channel Pseudo-Differential (MAX1061)

4-Channel Single Ended/

2-Channel Pseudo-Differential (MAX1063)

♦ Software-Configurable, Unipolar/Bipolar Inputs

♦ Low Power

1.9mA (250ksps)

1.0mA (100ksps)

400µA (10ksps)

2µA (Shutdown)

♦ Internal 3MHz Full-Power Bandwidth Track/Hold

♦ Byte-Wide Parallel (8 + 2) Interface

♦ Small Footprint: 28-Pin QSOP (MAX1061)

24-Pin QSOP (MAX1063)

MAX1061/MAX1063

250ksps, +3V, 8-/4-Channel, 10-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________

Maxim Integrated Products

19-2724; Rev 1; 3/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART

MAX1061ACEI+

0°C to +70°C

TEMP RANGE

PIN-PACKAGE

28 QSOP

Ordering Information

Pin Configurations

±0.5

INL

(LSB)

MAX1061BCEI+

0°C to +70°C

±128 QSOP

Denotes a lead(Pb)-free/RoHS-compliant package.

Ordering Information continued at end of data sheet.

Typical Operating Circuits appear at end of data sheet.

TOP VIEW

LOGIC

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CLKWR

INT

D0/D8

D1/D9

HBEN

QSOP

MAX1063

Pin Configurations continued at end of data sheet.

MAX1061BEEI+

MAX1061AEEI+

-40°C to +85°C

±1

-40°C to +85°C

±0.528 QSOP

28 QSOP

Summary of content (20 pages)

PAGE 1
9-2724; Rev 1; 3/09 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface The MAX1061/MAX1063 low-power, 10-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up (2µs), an on-chip clock, +2.5V internal reference, and a high-speed, byte-wide parallel interface. They operate with a single +3V analog supply and feature a VLOGIC pin that allows them to interface directly with a +1.8V to +3.6V digital supply.
PAGE 2
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V VLOGIC to GND.........................................................-0.3V to +6V CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND ................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.
PAGE 3
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.6 V VDD + 0.3 2.6 2.3 1.2 0.
PAGE 5
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) 0.2 MAX1061/63 toc02 0.3 0.20 0.15 0.10 0 -0.1 0.05 1000 0 WITH INTERNAL REFERENCE 100 -0.5 -0.10 -0.2 WITH EXTERNAL REFERENCE 10 -0.15 -0.3 -0.20 -0.4 1 -0.25 400 600 800 1000 1200 0 200 OUTPUT CODE 600 800 1000 0.1 1200 100 RL = ∞ CODE = 1010100000 2.1 2.00 IDD (mA) 1.9 1.90 1.8 1.85 1.7 1.80 3.
PAGE 7
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.50 2.49 2.49 -0.5 2.48 2.48 3.0 3.3 -40 3.6 -15 35 60 OFFSET ERROR vs. TEMPERATURE 3.3 GAIN ERROR vs. TEMPERATURE -0.250 35 60 3.0 3.3 VDD (V) LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE LOGIC SUPPLY CURRENT vs.
PAGE 8
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.
PAGE 9
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Converter Operation The MAX1061/MAX1063 ADCs use a successiveapproximation (SAR) conversion technique and an input track/hold (T/H) stage to convert an analog input signal to a 10-bit digital output. Their parallel (8 + 2) output format provides an easy interface to standard microprocessors (µPs). Figure 2 shows the simplified internal architecture of the MAX1061/MAX1063.
PAGE 10
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Track/Hold 10-BIT CAPACITIVE DAC REF CHOLD INPUT 12pF MUX – + CH0 COMPARATOR ZERO CH1 RIN 800Ω CH2 CH3 CH4 CSWITCH HOLD TRACK CH5 CH6 CH7 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
PAGE 11
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval ends (three external cycles or approximately 1µs in internal clock mode) (Figure 4).
PAGE 12
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tACQ tCSWS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D7–D0 ACQMOD = 0 tINT1 INT RD HBEN tD0 tTR tD01 HIGH-Z HIGH/LOW BYTE VALID DOUT HIGH-Z HIGH/LOW BYTE VALID Figure 4.
PAGE 13
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Internal Clock Mode Select internal clock mode to release the µP from the burden of running the SAR conversion clock. To select this mode, bit D7 of the control byte must be set to 1 and D6 must be set to zero. The internal clock frequency is then selected, resulting in a conversion time of 3.6µs. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating.
PAGE 14
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWS tDH WR ACQMOD = 0 WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = 1 ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWH tDH WR ACQMOD = 1 WR GOES HIGH WHEN CLK IS LOW. ACQMOD = 0 Figure 6b. External Clock and WR Timing (External Acquisition Mode) Table 2.
PAGE 15
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface A2 A1 A0 CH0 CH1 0 0 0 + - CH2 CH3 CH4* CH5* CH6* CH7* 0 0 1 - + 0 1 0 + - 0 1 1 - + 1 0 0 + - 1 0 1 - + 1 1 0 + - 1 1 1 - + *Channels CH4–CH7 apply to MAX1061 only. Applications Information Power-On Reset When power is first applied, internal power-on reset circuitry activates the MAX1061/MAX1063 in external clock mode and sets INT high.
PAGE 16
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to V DD . The DC input resistance at REF is 25kΩ. Therefore, an external reference at REF must deliver up to 200µA DC load current during a conversion and have an output impedance less than 10Ω. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor.
PAGE 17
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface UNIPOLAR MODE BIPOLAR MODE Full scale VREF + COM Positive full scale VREF/2 + COM Zero scale COM Zero scale COM — — Negative full scale -VREF/2 + COM sion cycles, and 2 read cycles. This assumes that the results of the last conversion are read before the next control byte is written.
PAGE 18
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK WR RD HBEN D7–D0 CONTROL BYTE D7–D0 D9–D8 D7–D0 D9–D8 CONTROL BYTE LOW HIGH BYTE BYTE LOW BYTE ACQUISITION CONVERSION ACQUISITION STATE HIGH BYTE SAMPLING INSTANT Figure 10.
PAGE 19
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface CLK VLOGIC +1.8V TO +3.6V CS REF WR REFADJ 4.7µF +3V MAX1063 VDD +2.5V 0.1µF RD +1.8V TO +3.6V VLOGIC +3V MAX1061 VDD µP CONTROL INPUTS CLK µP CONTROL INPUTS CS REF WR REFADJ 4.7µF 0.1µF RD HBEN +2.
PAGE 20
MAX1061/MAX1063 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Revision History REVISION NUMBER REVISION DATE 0 4/03 Initial release 3/09 Updated Ordering Information table with lead-free information and updated Package Information section 1 DESCRIPTION PAGES CHANGED — 1, 19, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.