Datasheet

MAX1065/MAX1066
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-and-
hold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed inter-
face to most microprocessors (µPs). The
Functional
Diagram shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The sin-
gle-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AV
DD
and/or AGND, allow the input to swing
from AGND - 0.3V to AV
DD
+ 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
Track and Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
8 _______________________________________________________________________________________
CS
R/C
REF POWER-
DOWN BIT
EOC
D0–D13
HBEN*
DATA VALID
D7/D13–D0/D8*
HIGH/LOW
BYTE VALID
t
ACQ
t
CONV
t
CSH
t
CSL
t
DH
t
DO
t
DO1
t
EOC
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
t
DS
t
DV
HI–Z
HI-Z
HIGH/LOW
BYTE VALID
t
BR
t
BR
Figure 2. MAX1065/MAX1066 Timing Diagram
DGND
1mA
C
LOAD
= 20pF
D0–D13
D0–D13
C
LOAD
= 20pF
1mA
DGND
DV
DD
a) HIGH-Z TO V
OH,
V
OL
TO V
OH,
AND
V
OH
TO HIGH-Z
b) HIGH-Z TO V
OL,
V
OH
TO V
OL,
AND
V
OL
TO HIGH-Z
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time