Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 38

19-5741; Rev 3; 8/12

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MAX11040K/MAX11060

24-/16-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADCs

EVALUATION KIT AVAILABLE

General Description

The MAX11040K/MAX11060 are 24-/16-bit, 4-channel,

simultaneous-sampling, sigma-delta analog-to-digital

converters (ADCs). The devices allow simultaneous

sampling of as many as 32 channels using a built-in

cascade feature to synchronize as many as eight

devices. The serial interface of the devices allows read-

ing data from all the cascaded devices using a single

command. Four modulators simultaneously convert

each fully differential analog input with a programmable

data output rate ranging from 0.25ksps to 64ksps. The

devices achieve 106dB SNR at 16ksps and 117dB SNR

at 1ksps (MAX11040K). The devices operate from a

single +3V supply. The differential analog input range is

±2.2V when using the internal reference; an external

reference is optional. Each input is overvoltage protect-

ed up to ±6V without damage. The devices use an

internal crystal oscillator or an external source for clock.

The devices are compatible with SPI, QSPI™,

MICROWIRE

, and DSP-compatible 4-wire serial inter-

faces. An on-board interface logic allows one serial inter-

face (with a single chip select) to control up to eight

cascaded devices or 32 simultaneous sampling analog

input channels.

The devices are ideally suited for power-management

systems. Each channel includes an adjustable sam-

pling phase enabling internal compensation for phase

shift due to external dividers, transformers, or filters at

the inputs. The output data rate is adjustable with a

0.065% resolution (at 16ksps or below) to track the

varying frequency of a periodic input. A SYNC input

allows periodic alignment of the conversion timing of

multiple devices with a remote timing source.

The devices are available in a 38-pin TSSOP package speci-

fied over the -40°C to +105°C industrial temperature range.

Applications

Power-Protection Relay Equipment

Multiphase Power Systems

Industrial Data-Acquisition Systems

Medical Instrumentation

Features

o Four Fully Differential Simultaneously Sampled

Channels

o Cascadable for Up to 32 Channels of

Simultaneous Sampling

o 106dB (MAX11040K) SNR at 16ksps

o 117dB (MAX11040K) SNR at 1ksps

o 0.25% Error Over a 1000:1 Dynamic Range,

Processed Over 16.7ms (MAX11040K)

o ±2.2V Full-Scale Input Range

o ±6V Overvoltage Protected Inputs

o Internal Crystal Oscillator

o 2.5V, 50ppm/°C Internal Reference or External

Reference

o Programmable Output Data Rate

0.25ksps to 64ksps Range

0.065% Resolution

o Programmable Sampling Phase

0 to 333µs Delay in 1.33µs Steps

o SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire

Serial Interface

o Cascadable Interface Allows Control of Up to

Eight Devices with a Single CS Signal

o 3.0V to 3.6V Analog Supply Voltage

o 2.7V to V

AVDD

Digital Supply Voltage

o 38-Pin TSSOP Package

Ordering Information

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

MAX11040KGUU+ -40°C to +105°C 38 TSSOP

MAX11060GUU+ -40°C to +105°C 38 TSSOP

MICROWIRE is a registered trademark of National Semiconductor Corp.

QSPI is a trademark of Motorola, Inc.

MAX11040K

24-BIT

ADC

DIGITAL

FILTER

2.5V

REFERENCE

CRYSTAL

OSCILLATOR

REFIO

AIN3+

AIN3-

REF3

24-BIT

ADC

DIGITAL

FILTER

AIN2+

AIN2-

REF2

24-BIT

ADC

DIGITAL

FILTER

AIN1+

AIN1-

REF1

24-BIT

ADC

DIGITAL

FILTER

AIN0+

AIN0-

REF0

REGISTERS AND

DIGITAL

CONTROL

SERIAL

INTERFACE

DOUT

DIN

SCLK

CASCOUT

CASCIN

DRDYOUT

DRDYIN

SYNC

FAULTOVRFLW

CLKOUTXOUT DGNDAGND XIN

Functional Diagram

Summary of content (35 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs General Description The MAX11040K/MAX11060 are 24-/16-bit, 4-channel, simultaneous-sampling, sigma-delta analog-to-digital converters (ADCs). The devices allow simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. The serial interface of the devices allows reading data from all the cascaded devices using a single command.
PAGE 2
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs ABSOLUTE MAXIMUM RATINGS AIN_ _ to AGND (VAVDD < 3V or VDVDD < 2.7V or FAULTDIS = 1 or SHDN = 1 or fXIN CLOCK < 20MHz) ..............-3.5V to +3.5V REFIO, REF_ to AGND............................-0.3V to (VAVDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) TSSOP (derated 13.7mW/°C above +70°C)..............
PAGE 3
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Bandwidth CONDITIONS MIN -3dB Latency (Note 8) Passband Flatness From DC to 1.
PAGE 4
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.
PAGE 5
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SCLK Rise to DOUT Valid SYMBOL tDOT CONDITIONS CLOAD = 30pF MIN TYP MAX 1.
PAGE 6
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Typical Operating Characteristics (MAX11040K) (VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF, TA = +25°C, unless otherwise noted.) 250 0.5 1.5 2.5 DIFFERENTIAL INPUT VOLTAGE (V) MAX11040K/11060 toc03 1 MILLION 62.5Hz CYCLES 0.1 0.01 0.001 0.10030 -0.5 0.10024 0 -1.5 0.10018 50 -0.005 -2.5 0.10012 100 -0.004 0.
PAGE 7
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Typical Operating Characteristics (MAX11040K continued) (VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF, TA = +25°C, unless otherwise noted.) -120 0.04 0.02 0 -0.02 -0.04 0.06 1000 1500 -0.10 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR vs. TEMPERATURE 0.2 0 -0.2 -0.4 0.
PAGE 8
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Typical Operating Characteristics (MAX11040K continued) (VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1μF, TA = +25°C, unless otherwise noted.) IDVDD 10 IAVDD 15 10 5 5 0 0 IDVDD MAX11040K/11060 toc18 20 500 AVDD = DVDD 400 SUPPLY CURRENT (nA) VAVDD = VDVDD = 3.
PAGE 9
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Pin Configuration TOP VIEW + AIN0- 1 38 AIN2- AIN0+ 2 37 AIN2+ REF0 3 36 REF2 AGND 4 35 AGND AIN1- 5 34 AIN3- AIN1+ 6 33 AIN3+ REF1 7 AGND 8 MAX11040K MAX11060 32 REF3 31 AGND REFIO 9 30 AVDD AGND 10 29 AGND DGND 11 28 DGND DVDD 12 27 DVDD CASCIN 13 26 XIN CASCOUT 14 25 XOUT CS 15 24 SYNC SCLK 16 23 DRDYIN DIN 17 22 DRDYOUT DOUT 18 21 CLKOUT FAULT 19 20 OVRFLW TSSOP Pin Descrip
PAGE 10
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Pin Description (continued) PIN NAME 11, 28 DGND Digital Ground 12, 27 DVDD Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1μF capacitor in parallel with a 0.01μF capacitor as close as possible to the device. 13 14 10 CASCIN FUNCTION Cascade Input.
PAGE 11
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Pin Description (continued) PIN 22 23 NAME FUNCTION Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the DRDYOUT availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when DRDYIN = 1. See the Multiple Device Connection section. DRDYIN Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high.
PAGE 12
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Typical Operating Circuit 1µF 3.3V 3.3V 0.01µF 20pF DVDD XIN AIN0+ AIN0REF0 1µF AIN1+ AIN1- The devices operate from a single 3.0V to 3.6V analog supply and a 2.7V to VAVDD digital supply. The 4-wire serial interface is SPI/QSPI/MICROWIRE and DSP compatible. 1µF 0.01µF AVDD AIN0+ AIN0- 24.
PAGE 13
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Digital Filter The devices contain an on-chip digital lowpass filter that processes the data stream from each modulator and generates the high-resolution output data. The lowpass filter frequency response is determined by the programmable output data rate. At the nominal 16ksps output data rate, the -3dB bandwidth of the filter is 3.4kHz. The passband flatness is better than ±0.1dB from 0 to 1.74kHz.
PAGE 14
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Modulator Clock The modulator clock is created by dividing the frequency at the XIN input by a factor of 8. The XIN input is driven either directly by an external clock or by the on-chip crystal oscillator. Crystal Oscillator The on-chip oscillator requires an external crystal (or resonator) with a 24.576MHz operating frequency connected between XIN and XOUT, as shown in Figure 3.
PAGE 15
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs When the analog input voltage changes between the ADC full scale and the fault threshold faster than the latency of the converter, OVRFLW goes low with the FAULT output. OVRFLW remains invalid until a valid clock frequency is available at XIN.
PAGE 16
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs FAULT-DETECTION THRESHOLD (VPFT OR |VNFT|) |AIN+ - AIN-| LATENCY LATENCY LATENCY FULL SCALE (|0.88VREF|) RECOVERY TIME DIGITAL OUTPUT DATA AT DOUT LATENCY FAULT OVRFLW Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery Reference The devices operate with either a +2.5V internal bandgap reference or an external reference source between +2.3V and +2.7V applied at REFIO.
PAGE 17
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs DRDYIN, and DRDYOUT. For single-device applications, connect CASCIN and DRDYIN to DGND and drive CS low to transfer data in and out of the devices. With DRDYIN low, a falling edge at the data-ready signal output (DRDYOUT) indicates that new conversion results are available for reading in the 96-bit data register. A falling edge on SCLK clocks in data at DIN.
PAGE 18
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Registers The devices include four registers accessible by 7 command bytes. The command bytes provide read and write access to the Data Rate Control register, the Sampling Instant Control register, and the Configuration register, and read access to the Data register. See Table 2. Figure 9 shows the CASCIN and CASOUT timing diagram. Figure 10 is the XIN clock, CLKOUT, SYNC, and DRDYOUT timing diagram.
PAGE 19
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Sampling Instant Control Register By default, the devices sample all 4 input channels simultaneously. To delay the sampling instant on one or more channels, program the appropriate byte in the Sampling Instant Control register. The delay of the actual sampling instant of each individual channel from the default sampling instant (PHI_[7:0] = 0x00) is adjustable between 32 to 819,121 XIN clock cycles, which is 1.
PAGE 20
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Data Register The Data register contains the results of the ADC conversion. The result is reported in two’s complement format. The register contains one or two pieces of information, depending on the state of EN24BIT in the Configuration register. When EN24BIT is set to zero, the Data register contains the ADC data truncated to 19 bits, followed by the device and channel addresses (see Table 5).
PAGE 21
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Table 7. Data Register (MAX11060) (continued) BIT NAME [31:29] 000 [28:26] IC[2:0] [25:24] 10 [23:8] CH3DATA[15:0] [7:5] 000 [4:2] IC[2:0] [1:0] 11 DESCRIPTION — Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 2 address tag = 10 Channel 3 16-bit conversion result (two’s complement) — Device address tag. IC[2:0] starts with 000 for the device nearest the master.
PAGE 22
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs The data length of the Data-Rate Control register is 16 bits total for writes and reads (see Table 2). Changes to the Data-Rate Control register take effect after 16 conversion periods (Figure 12), i.e., the ADC continues to operate at the old data rate for another 16 periods. Also, the last sample at the old data rate (sample 16 in Figure 12) may contain some noise component and should be discarded.
PAGE 23
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Table 8. Data-Rate Control Register BITS NAME DESCRIPTION Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor. FSAMPC [15:13] FSAMPC[2:0] [12:11] Reserved Coarse Cycle Factor Sample Rate in ksps (fXIN CLOCK = 24.576MHz) 000 4 16 001 128 0.5 010 64 1 011 32 2 100 16 4 101 8 8 110 2 32 111 1 64 Set to 0. Output data rate fine adjusts bits.
PAGE 24
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0] (continued) FSAMPC[2:0] 100 101 000 110 111 FSAMPF[10:0] OUTPUT DATA RATE (sps) OUTPUT DATA PERIOD (24.576MHz CLOCK CYCLES) 11xxxxxxxxx 2000.7 12284 10111111111 2000.7 12284 00000000001 3997.4 6148 00000000000 4000.0 6144 11xxxxxxxxx 4001.3 6142 10111111111 4001.3 6142 00000000001 7994.
PAGE 25
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Multiple Device Connection Daisy chain up to eight devices for applications that require up to 32 simultaneously sampled inputs over a single SPI-/DSP-compatible serial interface with a single chip-select signal, and single interface commands that apply to all devices in the chain. The eight devices effectively operate as one device.
PAGE 26
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs To ensure that all devices have their data ready, connect DRDYIN of device 0 to ground, and connect DRDYIN of device n to the DRDYOUT of device n-1 for all devices. DRDYOUT does not go low until DRDIN is low and the conversion of the device is complete. In this configuration, DRDYOUT of the last device goes low only when all devices in the chain have their data ready.
PAGE 27
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs CS DIN B15 B14 B13 X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SCLK HIGH-Z HIGH-Z DOUT CASCOUT0 (CASCIN0 = 0) CASCOUT1 CASCOUT2 CASCOUT3 CASCOUT4 CASCOUT5 CASCOUT6 CASCOUT7 X = RESERVED Figure 15.
PAGE 28
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs OUT with a period tS. The effect of a SYNC falling edge as shown in Figure 16 is described in sequence below: SYNC for Simultaneous Sampling with Multiple Devices The SYNC input permits multiple devices to sample simultaneously. The mismatch between the power-up reset of multiple devices causes the devices to begin conversion at different times.
PAGE 29
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Referring back to the analog input, since the entire sampling section of the converter also paused for two clock cycles, the sampling point for sample 5 is also paused by two clock cycles, possibly creating a small disturbance at the SYNC falling edge. This disturbance is filtered with the digital filter, which makes it less distinct.
PAGE 30
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Applications Information Multiple Device Synchronization Synchronizing Multiple Devices Using a Shared XIN Clock Source To synchronize multiple devices sharing a single XIN clock source, transition the SYNC input that is shared by all devices high to low. When an external sync source is not available, connect DRDYOUT of the last device to the SYNC input of all devices in the chain.
PAGE 31
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Signal Distortion at SYNC Falling Edges Each SYNC falling edge causes a disruption in the digital filter timing proportional to the delay from the previous falling edge of DRDYOUT to the falling edge of SYNC. Any analysis of the output data that assumes a uniform sampling period sees an error proportional to that delay, with a maximum value determined by the maximum derivative of the analog input.
PAGE 32
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Source Impedance and Input Sampling Network The source impedance that drives the analog inputs affects the sampling period. Low-Impedance Sources Minimize the source impedance to ensure the input capacitor fully charges during the sampling phase. The required source resistance is defined by the equation below: RSOURCE _ MAX < = tSAMP ⎛ 1 ⎞ K x CSAMP x In⎜ ⎟ ⎝ Error ⎠ 120ns ⎛ 1 ⎞ 1.
PAGE 33
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs To compensate the result of an FFT for the devices’ output data: 1) Calculate the inverse (1/x) of the equation provided in the Digital Filter section for each frequency in the FFT. 2) Multiply the FFT of the devices’ output data by the result of the above step. Power Supplies AVDD and DVDD provide power to the devices. The AVDD powers up the analog section, while the DVDD powers up the digital section.
PAGE 34
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Package Information Chip Information PROCESS: BiCMOS 34 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO.
PAGE 35
MAX11040K/MAX11060 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs Revision History REVISION NUMBER REVISION DATE 0 2/11 Initial release of the MAX11040K — 1 4/11 Initial release of the MAX11060 1 2 11/11 Updated Absolute Maximum Ratings 2 8/12 Updated the Multiple Device Digital Interface and the Synchronizing Multiple Devices Using a Shared XIN Clock Source sections and Figure 13 3 DESCRIPTION PAGES CHANGED 25, 26 29, 30 Maxim Integrated cannot assume respons