9-0283; Rev 5; 11/98 KIT ATION EVALU LE B A IL A AV Low-Cost, 2-Channel, ±14-Bit Serial ADCs The MAX110/MAX111 analog-to-digital converters (ADCs) use an internal auto-calibration technique to achieve 14-bit resolution plus overrange, with no external components. Operating supply current is only 550µA (MAX110) and reduces to 4µA in power-down mode, making these ADCs ideal for high-resolution battery-powered or remote-sensing applications.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................................+6V VSS to GND (MAX110)..............................................+0.3V to -6V AGND to DGND.....................................................-0.3V to +0.3V VIN1+, VIN1- ......................................(VDD + 0.3V) to (VSS - 0.3V) VIN2+, VIN2- ......................................(VDD + 0.3V) to (VSS - 0.3V) VREF+, VREF- ..........
Low-Cost, 2-Channel, ±14-Bit Serial ADCs (VDD = 5V ±5%, VSS = -5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = -1.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUTS Differential Reference Input Voltage Range VREF 0 3.0 V Absolute Reference Input Voltage Range VREF+, VREF- VSS + 2.25 VDD 2.25 V Reference Input Current IREF+, IREF- VREF+ = 2.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs ELECTRICAL CHARACTERISTICS—MAX111 (VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs (VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUTS Differential Reference Input Voltage Range VREF 0 1.5 V Absolute Reference Input Voltage Range VREF+, VREF- 0 VDD - 3.2 V Reference Input Current IREF+, IREF- VREF+ = 1.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed by power-supply rejection tests. Tests are performed at VDD = 5V and VSS = -5V (MAX110). Note 2: 32,768 LSBs cover an input voltage range of ±VREF (15 bits). An additional bit (OFL) is set for VIN > VREF. Note 3: Guaranteed by design. Not subject to production testing.
, , Low-Cost, 2-Channel, ±14-Bit Serial ADCs 0.05 0.04 0 MAX110 toc02 -0.10 -2 0 2 -4 4 -2 0 2 4 VIN (V) VIN (V) MAX110 RELATIVE ACCURACY vs. OVERSAMPLING FREQUENCY (fOSC) MAX110 RELATIVE ACCURACY vs. TEMPERATURE VDD = 4.75V VSS = -4.75V TA = +85°C 0.10 ÷1 MODE 0.03 ÷2 MODE 0.02 0.01 0.08 0.06 0.04 0.02 ÷ 4 MODE 0 0 0 0.25 0.50 0.75 1.00 1.25 -50 fOSC (MHz) -25 0 25 50 75 100 TEMPERATURE (°C) MAX110 POWER DISSIPATION vs.
____________________________Typical Operating Characteristics (continued) (MAX111, VDD = 5V, VREF+ = 1.5V, VREF- = 0V, differential input (VIN+ = -VIN-), fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 clocks/conv, TA = +25°C, unless otherwise noted.) MAX111 RELATIVE ACCURACY (-VREF < VIN < VREF) MAX111 RELATIVE ACCURACY (-0.667VREF < VIN < 0.667VREF) RELATIVE ACCURACY (%FSR) 0.05 0 -0.05 MAX110-TOC7 0.10 MAX110-TOC6 0.10 RELATIVE ACCURACY (%FSR) 0.05 0 -0.05 -0.10 -0.10 -2.0 -1.5 -1.0 -0.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs PIN NAME DIP/SO SSOP 1 1 2 3 FUNCTION IN1+ Channel 1 Positive Analog Input 2 REF- Negative Reference Input 3 REF+ Positive Reference Input 4 6 VDD 5 7 RCSEL 6 8 XCLK Clock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = VDD. XCLK must be connected to VDD or GND through a resistor (1MΩ or less) when RC OSC mode is selected.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs DIN DITHER GENERATOR IN1+ IN1IN2+ IN2- SCLK CS IN+ INPUT MUX IN- INTEGRATOR Gm Σ ∫ REF+ REF- SERIAL SHIFT REGISTER 16 16 UP/DOWN COUNTER - DOUT CONTROL REGISTER 16 Gm 16 TIMER + CONTROL LOGIC + CLOCK GENERATOR OSC DIVIDER NETWORK, DIVIDE BY 1, 2, OR 4 MAX110 MAX111 BUSY RCSEL XCLK RC OSCILLATOR Figure 1.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 +5V +5V VDD VDD RCSEL RCSEL MAX110 MAX111 MAX110 MAX111 +5V GND TTL/CMOS GND 1MΩ XCLK XCLK VSS (AGND) VSS (AGND) -5V (0V) -5V (0V) ( ) ARE FOR MAX111. ( ) ARE FOR MAX111. Figure 3a. Connection for External-Clock Mode ADC Operation The output data from the MAX110/MAX111 is arranged in twos-complement format (Figures 4, 5).
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs OUTPUT CODE POL OFL D13...D0 1 00 . . .000 +OVERFLOW 0 0 0 11 . . .111 0 0 11 . . .110 0 0 11 . . .101 -OVERFLOW 0 0 11 . . .100 0 0 0 0 00 . . .001 00 . . .001 0 0 00 . . .000 1 1 1 1 11 . . .111 11 . . .110 1 1 1 1 1 1 00 . . .011 00 . . .010 00 . . .001 1 1 00 . . .000 1 0 11 . . .111 +OVERFLOW TRANSITION -OVERFLOW TRANSITION - VREF INPUT VOLTAGE (LSBs) VREF -1LSB Figure 4.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 CS tCSH tCK tCSS SCLK tCK tDH tDS DIN MSB LSB tDO tDH tDA DOUT POL OFL MSB DO BUSY END OF CONVERSION START OF CONVERSION Figure 6. Detailed Serial-Interface Timing +5V SS I/O SCK µP MISO MOSI MASKABLE INTERRUPT CS SCLK MAX110 DOUT MAX111 DIN BUSY a. SPI/QSPI I/O SK µP SI SO MASKABLE INTERRUPT or I/O CS SCLK MAX110 DOUT MAX111 DIN BUSY b.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs 1ST BYTE READ/WRITE MAX110 MAX111 2ND BYTE READ/WRITE BUSY CS SCLK DOUT POL OFL D13 DIN NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DV2 NU NU CHS CAL NUL PDX PD Figure 8a.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs 15 14 13 NO-OP NU NU 12 11 10 9 CONV4 CONV3 CONV2 CONV1 8 7 6 5 4 3 2 1 0 DV4 DV2 NU NU CHS CAL NUL PDX PD ↑ First bit clocked in. BIT 15 NAME DESCRIPTION NO-OP If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a new conversion begins when CS returns high.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs Table 2. Allowable Input Multiplexer Configurations CAL NUL CHS NO-OP ADC IN+ ADC IN- DESCRIPTION 0 0 0 1 IN1+ IN1- Channel 1 connected to ADC inputs. Conversion begins when CS returns high. 0 0 1 1 IN2+ IN2- Channel 2 connected to ADC inputs. Conversion begins when CS returns high. 0 1 0 1 IN1- IN1- IN1- connected to the ADC inputs; offset-null mode selected.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs Table 3 describes the three steps required to calibrate the ADC completely. Once the ADC is calibrated to the selected channel, set CAL = 0 and NUL = 0 and leave CHS unchanged in the next control word to perform a signal conversion on the selected analog input channel.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs 0 -10 GAIN (dB) -20 -30 -40 -50 -60 CONVERSION TIME LINE CYCLE PERIOD 0.1 SIGNAL FREQUENCY IN Hz 1 FOR 100ms CONVERSION TIME (see Table 6) 1 2 3 4 5 6 7 8 9 10 10 20 30 40 50 60 70 80 90100 Figure 9.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs +5V -5V 4.7µF *R = 10Ω +5V GND 4.7µF GND 4.7µF *R = 10Ω 0.1µF 0.1µF VDD GND MAX110/MAX111 POWER SUPPLIES POWER SUPPLIES 0.1µF VSS +5V VDD DGND GND DIGITAL CIRCUITRY MAX110 AGND +5V DGND DIGITAL CIRCUITRY MAX111 *OPTIONAL *OPTIONAL Figure 10a. MAX110 Power-Supply Grounding Connections Figure 10b.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs +5V 0.1µF +5V VDD 22k REF+ 1/2 MAX492 +5V 30mV FULL-SCALE 10k 1k REF1µF +5V MAX111 1k 121k 49.9k 2k 49.9k 121k 1k IN1+ CS IN1- DIN DOUT 1µF +5V SCLK AGND GND 1/2 MAX492 Figure 11. Weigh Scale Application Capacitive Loading Effects of XCLK in Internal RC-Oscillator Mode When using the internal RC oscillator, capacitive loading effects on the XCLK pin must be minimized.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 +5V 1/4 MAX479 IN2+ VDD IN210k 10k MAX110 1/4 MAX479 1k +5V 1µF VIN 243k TEMP K-TYPE MAX874 OUT IN1+ CS IN1- DIN 1k 243k 10k 1k DOUT REF+ REF- SCLK VSS 1µF 1/4 MAX479 1M -5V Figure 12. Thermocouple Circuit with Software Compensation unloaded, and subtracting this value from actual weight measurements. The lowpass filtering action of the MAX111’s sigma-delta converter helps minimize noise.
MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE INL(%) MAX110AEPE -40°C to +85°C 16 Plastic DIP ±0.03 MAX110BEPE -40°C to +85°C 16 Plastic DIP ±0.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs PDIPN.EPS SOICW.
SSOP.EPS ___________________________________________Package Information (continued) CDIPS.EPS MAX110/MAX111 Low-Cost, 2-Channel, ±14-Bit Serial ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.