Datasheet

16
MAX11135–MAX11143
500ksps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
Pin Description
MAX11135
MAX11138
MAX11141
(4 CHANNEL)
MAX11136
MAX11139
MAX11142
(8 CHANNEL)
MAX11137
MAX11140
MAX11143
(16 CHANNEL)
NAME FUNCTION
— —
26, 27, 28,
1–11
AIN0–AIN13 Analog Inputs
— 26, 27, 28, 1–5 — AIN0–AIN7 Analog Inputs
26, 27, 28, 1 — — AIN0–AIN3 Analog Inputs
2–11 6–11 — GND Ground
— — 12
CNVST/
AIN14
Active-Low Conversion Start Input/Analog Input 14
12 12 —
CNVST
Active-Low Conversion Start Input
— — 13
REF-/
AIN15
External Differential Reference Negative Input /Analog
Input 15
13 13 — REF- External Differential Reference Negative Input
14, 16 14, 16 14, 16 GND Ground
15 15 15 REF+
External Positive Reference Input. Apply a reference
voltage at REF+. Bypass to GND with a 0.47FF
capacitor.
17, 18 17, 18 17, 18 V
DD
Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
19 19 19 SCLK
Serial Clock Input. Clocks data in and out of the serial
interface
20 20 20
CS
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance or three-state.
21 21 21 DIN
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
22 22 22 DGND Digital I/O Ground
23 23 23 OVDD
Interface Digital Power-Supply Input. Bypass to GND
with a 10FF in parallel with a 0.1FF capacitors.
24 24 24 DOUT
Serial Data Output. Data is clocked out on the falling
edge of SCLK. When CS is high, DOUT is high
impedance or three-state.
25
25 25
EOC
End of Conversion Output. Data is valid after EOC pulls
low (Internal clock mode only).
— — — EP
Exposed Pad. Connect EP directly to GND plane for
guaranteed performance.