Datasheet

12 _____________________________________________________________________________________
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Single-Conversion Mode
with Self-Calibration at Wake-Up
The MAX11201 can be put in self-calibration mode imme-
diately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration and, when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with self-
calibration.
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
SLEEP
MODE
1 2 1 23
24
CONVERSION IS DONE
DATA IS AVAILABLE
t
9
t
11
t
10
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT
SLEEP MODE
D0
RDY/DOUT
D23
D22
D23 D22
SCLK
CONVERSION IS DONE
DATA IS AVAILABLE
1
D23
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
CALIBRATION STARTS ON 26TH SCLK
t
8
D22 D0
2 3 24
1 225 26
D23 D22
SCLK
RDY/DOUT
25TH SCLK PULLS
RDY/DOUT HIGH