Datasheet

4 ______________________________________________________________________________________
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
DVDD
= +1.7V, V
REFP
- V
REFN
= V
AVDD
; internal clock, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25NC under normal conditions, unless otherwise noted.)
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: V
AINP
= V
AINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
Note 6: The MAX11201A has no normal-mode rejection at 50Hz or 60Hz.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Rising Edge Data Hold
Time
t
4
Allows for positive edge data read 3 ns
RDY/DOUT Fall to SCLK Rising
Edge
t
5
0 ns
Next Data Update Time;
No Read Allowed
t
6
MAX11201A 155
Fs
MAX11201B 169
Data Conversion Time t
7
MAX11201A 8.6
ms
MAX11201B 73
Data Ready Time After Calibration
Starts (CAL + CNV)
t
8
MAX11201A 208.3
ms
MAX11201B 256.1
SCLK High After RDY/DOUT
Goes Low to Activate Sleep Mode
t
9
MAX11201A 0 8.6
ms
MAX11201B 0 73
Time from RDY/DOUT Low to
SCLK High for Sleep-Mode
Activation
t
10
MAX11201A 0 8.6
ms
MAX11201B 0 73
Data Ready Time After Wake-Up
From Sleep Mode
t
11
MAX11201A 8.6
ms
MAX11201B 73
Data Ready Time After Calibration
From Sleep Mode Wake-Up (CAL
+ CNV)
t
12
MAX11201A 208.4
ms
MAX11201B 256.2