Datasheet

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MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Functional Diagram
Detailed Description
The MAX11201 is an ultra-low-power (< 245FA active),
high-resolution, low-speed, serial-output ADC. This device
provides the highest resolution per unit power in the indus-
try and is optimized for applications that require very high
dynamic range with low power such as sensors on a 4mA
to 20mA industrial control loop. The MAX11201 provides
a high-accuracy internal oscillator, which requires no
external components. When used with the specified data
rates, the internal digital filter provides more than 100dB
rejection of 50Hz or 60Hz line noise. The MAX11201 pro-
vides a simple, system-friendly, 2-wire serial interface in
the space-saving, 10-pin FMAX package.
Power-On Reset (POR)
The MAX11201 utilizes power-on reset (POR) supply-
monitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
The MAX11201 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hys-
teresis. Both POR circuits have lowpass filters that pre-
vent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1µF capaci-
tors placed as close as possible to the package pin.
Buffers
The MAX11201 includes signal input buffers capable of
reducing the average input current from 1.4FA/V on the
analog inputs to a constant 20nA. The MAX11201 analog
inputs provide > 100MI input impedance for connecting
directly to high-impedance sources.
Analog Inputs
The MAX11201 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-V
REF
to
+V
REF
).
Internal Oscillator
The MAX11201 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11201A) or 2.25275MHz (MAX11201B).
The internal oscillator clock is divided down to run the
digital and analog timing.
TIMING
CLOCK GENERATOR
DIGITAL LOGIC
AND SERIAL-
INTERFACE
CONTROLLER
DIGITAL FILTER
(SINC
4
)
3RD-ORDER
DELTA-SIGMA
MODULATOR
CLK
AVDD
MAX11201
REFP
REFN
AINP
AINN
DVDD
GND
SCLK
RDY/DOUT