Datasheet

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MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power,

Delta- Sigma ADCs with Programmable Gain

and GPIO

EVALUATION KIT AVAILABLE

19-5334; Rev 2; 12/14

General Description

The MAX11203/MAX11213 are ultra-low-power (< 300µA

active current), high-resolution, serial-output ADCs. These

devices provide the highest resolution per unit power

in the industry, and are optimized for applications that

require very high dynamic range with low power, such

as sensors on a 4mA to 20mA industrial control loop.

Optional input buffers provide isolation of the signal inputs

from the switched capacitor sampling network allowing

these converters to be used with high-impedance sources

without compromising available dynamic range or linear-

ity. The devices provide a high-accuracy internal oscillator

that requires no external components. When used with

the specified data rates, the internal digital filter provides

more than 100dB rejection of 50Hz or 60Hz line noise. The

devices are configurable using the SPI interface and are

available in a 16-pin QSOP package.

Applications

Sensor Measurement (Temperature and Pressure)

Portable Instrumentation

Battery Applications

Weigh Scales

Benets and Features

● Minimize Power Consumption with Ultra-Low Power

Dissipation

• Operating-Mode Current Drain < 300µA (max)

• Sleep-Mode Current Drain < 0.4µA

● Improve Measurement Quality with Excellent DC/AC

Accuracy

• 16-Bit Noise-Free Resolution and No Missing

Codes

• 570nVRMS Noise at 10sps, ±3.6V

Input

• 3ppm INL (typ), 20ppm (max)

● Lower System Cost with Integrated Functionality

• Programmable Gain (1 to 128) (MAX11213)

• Four SPI-Controlled GPIOs for External Mux Control

• Optional Input Buffers on Both Signal and

Reference Inputs

• > 100dB (min) 50Hz/60Hz Rejection

● Increase System Accuracy with Built-in Self

Calibration

• On-Demand Offset and Gain Self-Calibration and

System Calibration

• User-Programmable Offset and Gain Registers

● Increase System Robustness and Reliability with

±2kV ESD Protection

• 2.7V to 3.6V Analog Supply Range

• 1.7V to 3.6V Digital and I/O Supply Range

• -40°C to 85°C Operating Temperature Range

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Functional Diagram

TIMING

CLOCK GENERATOR

DIGITAL LOGIC

AND SERIAL-

INTERFACE

CONTROLLER

3RD-ORDER

DELTA-SIGMA

MODULATOR

SCLK

DIN

CLK

GPIO

RDY/DOUT

GPIO1

GPIO2

GPIO3

GPIO4

AVDD

REFP

REFN

AINP

AINN

DVDD

GND

*PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11213.

DIGITAL FILTER

(SINC

)

PROGRAMMABLE

GAIN*

1–128

MAX11203

MAX11213*

Summary of content (26 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO General Description The MAX11203/MAX11213 are ultra-low-power (< 300µA active current), high-resolution, serial-output ADCs. These devices provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power, such as sensors on a 4mA to 20mA industrial control loop.
PAGE 2
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Absolute Maximum Ratings Any Pin to GND.....................................................-0.3V to +3.9V AVDD to GND........................................................-0.3V to +3.9V DVDD to GND.......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND ............................................. -0.3V to (VAVDD + 0.
PAGE 3
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Electrical Characteristics (continued) (VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.
PAGE 4
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Electrical Characteristics (continued) (VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.6 V 3.
PAGE 5
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Typical Operating Characteristics (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = 2.5V; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) 200 TA = +25°C 180 160 TA = +85°C 220 CURRENT (µA) CURRENT (µA) TA = +85°C 240 TA = +25°C 200 180 280 260 TA = +85°C CURRENT (µA) 240 ANALOG ACTIVE CURRENT vs.
PAGE 6
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Typical Operating Characteristics (continue) (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = 2.5V; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) LINEF = 1 -45 -25 -5 15 35 55 75 -6 -8 -10 2.85 3.00 3.15 3.30 3.45 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V) 0 -20 -40 PSRR (dB) 0 -2 TA = +25°C -60 -80 AVDD -100 -6 DVDD -120 -8 -10 -2.
PAGE 7
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Pin Configuration TOP VIEW GPIO1 1 + 16 GPIO4 15 CLK GPIO2 2 GPIO3 3 GND 4 MAX11203 MAX11213 14 SCLK 13 RDY/DOUT REFP 5 12 DIN REFN 6 11 CS AINN 7 10 DVDD AINP 8 9 AVDD QSOP Pin Description PIN NAME 1 GPIO1 General-Purpose I/O 1. Register controllable using SPI. FUNCTION 2 GPIO2 General-Purpose I/O 2. Register controllable using SPI. 3 GPIO3 General-Purpose I/O 3.
PAGE 8
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Detailed Description The MAX11203/MAX11213 are ultra-low-power (< 300FA active), high-resolution, low-speed, serial-output ADCs. These ADCs provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop.
PAGE 9
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO 2.048MHz oscillator. The 2.4576MHz oscillator provides maximum 60Hz rejection, and the 2.048MHz oscillator provides maximum 50Hz rejection. See Figures 1 and 2. For optimal simultaneous 50Hz and 60Hz rejection, apply a 2.25275MHz external clock at CLK. Reference The devices provide differential inputs REFP and REFN for an external reference voltage.
PAGE 10
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Table 3a. Example of Self-Calibration NOSYSO NOSCG NOSCO BIT NOSYSG REGISTER 1 Initial power-up 0x000000 0x000000 0x000000 0x000000 1 1 1 1 2 Enable self-calibration registers 0x000000 0x000000 0x000000 0x000000 1 1 0 0 3 Self-calibration, DIN = 10010000 0x00007E 0xBFD345 0x000000 0x000000 1 1 0 0 STEP DESCRIPTION SCOC SCGC SOC SGC Table 3b.
PAGE 11
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO NORMAL MODE REJECTION DATA RATE 120.0sps 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 GAIN (dB) GAIN (dB) NORMAL MODE REJECTION DATA RATE 10.0sps 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 1. Normal-Mode Frequency Response (2.
PAGE 12
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO It is not always necessary to transition to a high-impedance state between channel selections, but depends on the source analog signals as well as the control structure of the multiplexed switches.
PAGE 13
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Serial-Digital Interface is in progress if the RDY/DOUT output reads logic-high and the conversion is complete if the RDY/DOUT output reads logic-low. Data at RDY/DOUT changes on the falling edge of SCLK and is valid on the rising edge of SCLK. DIN and DOUT are transferred MSB first. Drive CS high to force DOUT high impedance and cause the devices to ignore any signals on SCLK and DIN.
PAGE 14
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO tDS tCSS0 tCP tCL tDH CS tDOT tDO1 tCH tDOD tDOH tCSS1 SCLK DIN 1 X HIGH-Z 1 1 X RS3 RS2 RS1 RS0 8 9 16 W/R X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 tDOE RDY/DOUT HIGH-Z Figure 7. SPI Register Access Read Command Byte or two’s complement), and single-cycle or continuous conversion mode. See Table 12.
PAGE 15
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Table 7. Operating Mode (MODE Bit) MODE BIT SETTING OPERATING MODE 0 The command byte initiates a conversion or an immediate power-down. See Tables 5 and 8. 1 The device interprets the command byte as a register access byte, which is decoded as per Tables 6 and 9. Table 8.
PAGE 16
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Table 10.
PAGE 17
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO STAT1: Status Register Table 11. STAT1 Register (Read Only) B7 B6 B5 B4 B3 B2 B1 B0 BIT NAME BIT SYSOR RATE2 RATE1 RATE0 OR UR MSTAT RDY DEFAULT 0 0 0 0 0 0 0 0 SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The SCGC calibration coefficient is maximum value of 1.9999999.
PAGE 18
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO CTRL1: Control 1 Register The byte-wide CTRL1 register is a bidirectional read/write register. The byte written to the CTRL1 register indicates if the part converts continuously or single cycle, if an external or internal clock is used, if the reference and signal buffers are activated, the format of the data when in bipolar mode, and if the analog signal input range is unipolar or bipolar.
PAGE 19
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO CTRL2: Control 2 Register The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the direction and values of the digital I/O ports. Table 13.
PAGE 20
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO DATA: Data Register The data register is a 24-bit read-only register. Any attempt to write data to the data register has no effect. The data read from this register is clocked out MSB first. The data register holds the conversion result. D15 is the MSB, and D0 is the LSB. The result is stored in a format according to the FORMAT bit in the CTRL1 register.
PAGE 21
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Table 16b.
PAGE 22
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO SGC: System Gain Calibration Register The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the system gain calibration value. The format is always in two’s complement binary format. A write to the system-calibration register is allowed.
PAGE 23
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO SCGC: Self-Calibration Gain Register The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the self-calibration gain calibration value. The format is always in two’s complement binary format. A write to the self-calibration register is allowed.
PAGE 24
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Applications Information See Figure 8 for the RTD temperature measurement circuit and Figure 9 for a resistive bridge measurement circuit. IREF1 = K x IREF2 IREF2 REFP MAX11203 MAX11213 RREF IREF1 Often, circuit designers immediately look for an external op amp or programmable gain amplifier (PGA) when confronted with coupling low-amplitude signals to sampled digital systems.
PAGE 25
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Chip Information PROCESS: BiCMOS AVDD Package Information 16-BIT ADC RSTRAIN For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PAGE 26
MAX11203/MAX11213 16-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 6/10 Initial release — 1 10/12 Updated the Serial-Digital Interface section 14 2 12/14 Updated the General Description and Benefits and Features sections 1 DESCRIPTION Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.