Datasheet

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MAX11208
20-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Figure 1. Timing Diagram for Data Read After Conversion
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
t
5
t
3
1
D19
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
D18 0
2 3 24
t
1
t
4
t
7
t
2
t
6
SCLK
RDY/DOUT
1
D19
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
D18 0
2 3 24 25
SCLK
RDY/DOUT
25TH SLK RISING EDGE
PULLS RDY/DOUT
HIGH
1
D19
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
CALIBRATION STARTS ON 26TH SCLK
t
8
D18 0
2 3 24
1 225 26
D19 D18
SCLK
RDY/DOUT
25TH SCLK PULLS
RDY/DOUT HIGH