9-3488; Rev 2; 1/07 KIT ATION EVALU E L B A IL AVA Multichannel, True-Differential, Serial, 14-Bit ADCs Features ♦ 8-Channel Single-Ended or 4-Channel Differential Inputs (MAX1148/MAX1149) ♦ 4-Channel Single-Ended or 2-Channel Differential Inputs (MAX1146/MAX1147) ♦ Internal Multiplexer and T/H ♦ Single-Supply Operation 4.75V to 5.25V Supply (MAX1146/MAX1148) 2.7V to 3.6V Supply (MAX1147/MAX1149) ♦ Internal Reference +4.096V (MAX1146/MAX1148) +2.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ............................................-0.3V to +6.0V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7, COM to AGND..........................-0.3V to (VDD + 0.3V) REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND .....................
Multichannel, True-Differential, Serial, 14-Bit ADCs (VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/ MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/ MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Multichannel, True-Differential, Serial, 14-Bit ADCs (VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs VDD VDD 6kΩ DOUT 6kΩ DOUT CLOAD 50pF 6kΩ DGND DGND a) HIGH-Z TO VOH AND VOL TO VOH DOUT DOUT CLOAD 50pF 6kΩ DGND DGND b) HIGH-Z TO VOL AND VOH TO VOL CLOAD 50pF CLOAD 50pF DGND DGND a) VOH TO HIGH-Z Figure 1. Load Circuits for Enable Time b) VOL TO HIGH-Z Figure 2.
Multichannel, True-Differential, Serial, 14-Bit ADCs (VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.) 0.5 DNL (LSB) 0.5 0 0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 1.8 MAX1146 toc03 1.
Typical Operating Characteristics (continued) (VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.) REFERENCE VOLTAGE vs. SUPPLY VOLTAGE (MAX1147/MAX1149) 2.5015 4.0970 4.0965 4.0960 4.0955 4.0950 2.5010 4.
Multichannel, True-Differential, Serial, 14-Bit ADCs (VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.) OFFSET ERROR vs. SUPPLY VOLTAGE (MAX1146/MAX1148) OFFSET ERROR vs.
Typical Operating Characteristics (continued) (VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.) CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE (MAX1147/MAX1149) CHANNEL-TO-CHANNEL GAIN MATCHING vs.
Multichannel, True-Differential, Serial, 14-Bit ADCs PIN MAX1148 MAX1146 MAX1149 MAX1147 NAME FUNCTION 1 1 CH0 2 2 CH1 3 3 CH2 4 4 CH3 5 — CH4 6 — CH5 7 — CH6 8 — CH7 9 9 COM Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in unipolar and bipolar mode. 10 10 SHDN Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current to 0.2µA. Driving shutdown high enables the devices.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs Detailed Description The MAX1146–MAX1149 ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 14-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 4 shows the typical application circuit and Figure 5 shows a functional diagram of the MAX1148/MAX1149.
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146–MAX1149 ANALOG INPUT MUX CH0 MAX1148 MAX1149 CH1 REF CH2 CT/H+ IN+ 14-BIT CAPACITIVE DAC CH3 TRACK CH4 HOLD HOLD HOLD CH5 TRACK TRACK 14-BIT CAPACITIVE DAC IN- CH6 CT/HCH7 REF COM Figure 6. Equivalent Input Circuit Input Bandwidth Quick Look The MAX1146–MAX1149 feature input tracking circuitry with a 3.0MHz small-signal bandwidth. The 3.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs VDD 10Ω OSCILLOSCOPE 10Ω AIN CH7 0.01µF MAX1148 MAX1149 VDD DIN 0.1µF 4.7µF SHDN SCLK EXTERNAL CLOCK SCLK REFADJ DOUT SSTRB 0.01µF DOUT* SSTRB REF VREF COM 2.2µF CS CH1 DGND AGND MAX1149 VREF = +2.500V MAX1148 VREF = +4.096V VCOM ≤ AIN ≤ VREF CH2 CH3 CH4 *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF HEX Figure 7. Quick-Look Circuit Table 1.
Multichannel, True-Differential, Serial, 14-Bit ADCs SEL2 SEL1 SEL0 CH0 + 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM - + + + + + + + - Table 3.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs Digital Output In unipolar input mode, the digital output is straight binary (Figure 14). For bipolar input mode, the digital output is two’s complement binary (Figure 15). Data is clocked out on the falling edge of SCLK in MSB-first format. Use internal clock mode if the serial clock frequency is less than 100kHz or if serial clock interruptions could cause the conversion interval to exceed 140µs.
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146–MAX1149 CS SCLK 1 8 9 16 24 CB1 DIN START SEL2 SEL1 SEL0 SGL/DIF UNI/BIP PD1 PD0 tCONV tACQ SSTRB DOUT HIGH-Z D13 D12 D11 D10 INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT T/H SET TO CB1 OPEN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HIGH-Z RESET TO CB1 TRACK HOLD TRACK Figure 9.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs CS SCLK 1 8 1 4 10 11 18 CB1 DIN 1 4 10 11 CB2 START SEL2 SEL1 SEL0 SGL/DIFUNI/BIP PD1 START SEL2 SEL1 SEL0 SGL/DIF UNI/BIP PD1 PD0 tACQ tCONV START SEL2 PD0 tACQ tCONV SSTRB HIGH-Z DOUT D13 D12 D5 D4 D3 D2 D1 D0 D13 D12 D5 D4 SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT MUX SET TO CB1 INPUT T/H OPEN TRACK SET TO CB2 RESET TO CB1 HOLD TRACK OPEN HOLD RESET TO CB2 TRACK Figure 11.
Multichannel, True-Differential, Serial, 14-Bit ADCs +3.3V IN 24kΩ SAR ADC MAX1146– MAX1149 REF REF 3.000V OUT MAX6163 MAX1146– MAX1149 0.1µF 20kΩ 510kΩ 0.047µF GND REFADJ +5V VDD Figure 13. Reference Adjust Circuit 0.1µF 1.250V BANDGAP REFERENCE REFADJ 100kΩ REFERENCE BUFFER DISABLED DGND with a 0.01µF capacitor and bypass REF with a 2.2µF capacitor to AGND. AGND Transfer Function Figure 12.
1 LSB = VREF 16384 1 LSB = VREF 0...011 0...010 0...001 0...000 1 2 3 16381 16383 0...111 0...110 0...101 0...100 0...001 VREF 1...101 1...100 TWO'S COMPLEMENT BINARY OUTPUT CODE (LSB) 1...111 1...110 0 VREF 16384 VREF VREF BINARY OUTPUT CODE (LSB) MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs 0...000 1...111 1...011 1...010 1...001 1...000 0 1 2 3 INPUT VOLTAGE (LSB) 8191 8193 8192 INPUT VOLTAGE (LSB) 16381 16383 Figure 14.
Multichannel, True-Differential, Serial, 14-Bit ADCs CS MAX1146–MAX1149 VDD VDD CS SCK SCLK SCLK SCK MISO DOUT DOUT SDI CS I/O VDD QSPI MAX1146– MAX1149 SS PIC16/PIC17 MAX1146– MAX1149 Figure 17. QSPI Connections GND GND Figure 18. SPI Interface Connection for a PIC16/PIC17 Controller Table 8. Detailed SSPCON Register Content PICI6/PICI7 SETTINGS CONTROL BIT SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) WCOL Bit 7 X Write collision detection bit.
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs TMS32OLC3x Interface Figure 19 shows an application circuit to interface the MAX1146–MAX1149 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 20. Use the following steps to initiate a conversion in the MAX1146–MAX1149 and to read the results: Layout, Grounding, and Bypassing Careful PC board layout is essential for best system performance.
Multichannel, True-Differential, Serial, 14-Bit ADCs Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1146–MAX1149 are measured using the end-point method.
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146–MAX1149 Pin Configurations TOP VIEW CH0 1 20 VDD CH0 1 20 VDD CH1 2 19 SCLK CH1 2 19 SCLK CH2 3 18 CS CH2 3 18 CS 17 DIN CH3 4 CH3 4 N.C. 5 MAX1146 MAX1147 16 SSTRB CH4 5 15 DOUT CH5 6 N.C. 7 14 DGND CH6 7 14 DGND N.C. 8 13 AGND CH7 8 13 AGND COM 9 12 REFADJ COM 9 12 REFADJ N.C.
Multichannel, True-Differential, Serial, 14-Bit ADCs TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.