Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - ADC 12 Bit SSOP 36

________________General Description

The MAX115/MAX116 are high-speed, multichannel,

12-bit data-acquisition systems (DAS) with simultane-

ous track/holds (T/Hs). These devices contain a 12-bit,

2µs, successive-approximation analog-to-digital con-

verter (ADC), a +2.5V reference, a buffered reference

input, and a bank of four simultaneous-sampling T/H

amplifiers that preserve the relative phase information

of the sampled inputs. The MAX115/MAX116 have two

multiplexed inputs for each T/H, allowing a total of eight

inputs. In addition, the converter is overvoltage tolerant

to ±17V. A fault condition on any channel will not dam-

age the IC. Available input ranges are ±5V (MAX115)

and ±2.5V (MAX116).

The parallel interface’s data access and bus release

timing specifications are compatible with most popular

digital signal processors and 16-bit/32-bit microproces-

sors. The MAX115/MAX116 conversion results can be

accessed without resorting to wait-states.

________________________Applications

Multiphase Motor Control

Power-Grid Synchronization

Power-Factor Monitoring

Digital Signal Processing

Vibration and Waveform Analysis

____________________________Features

♦ Four Simultaneous-Sampling T/H Amplifiers with

Two Multiplexed Inputs (Eight Single-Ended

Inputs Total)

♦ 2µs Conversion Time per Channel

♦ Throughput: 390ksps (1 Channel)

218ksps (2 Channels)

152ksps (3 Channels)

116ksps (4 Channels)

♦ Input Range: ± 5V (MAX115)

± 2.5V (MAX116)

♦ Fault-Protected Input Multiplexer (±17V)

♦ Internal +2.5V or External Reference Operation

♦ Programmable On-Board Sequencer

♦ High-Speed Parallel DSP Interface

♦ Internal 10MHz Clock

MAX115/MAX116

2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

________________________________________________________________ Maxim Integrated Products 1

19-1928; Rev 0; 1/01

PART

MAX115CAX

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

36 SSOP

EVALUATION KIT

AVAILABLE

Ordering Information

MAX115EAX -40°C to +85°C 36 SSOP

MAX116CAX

0°C to +70°C 36 SSOP

MAX116EAX -40°C to +85°C 36 SSOP

For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

AGND

CH3B

CH3A

CH4B

CH4A

INT

CONVST

CLK

D10

D11 (MSB)

AGND

REFOUT

REFIN

CH1A

CH1B

CH2A

CH2B

SSOP

TOP VIEW

MAX115

MAX116

18 D3

D0/A2 (LSB)

D1/A3

DGND

Pin Configuration

Typical Operating Circuit

D0/A2

D1/A3

D10

D11

CH1A

CH1B

CH2A

CH2B

CH3A

CH3B

CH4A

CH4B

MAX115

MAX116

CONVST

CONTROL INTERFACE

CLK

REFOUT DGND

AGND

REFIN DV

4.7µF

16MHz

0.1µF

-5V

0.1µF

+5V

0.1µF

+5V

INT CS RD WR

Summary of content (14 pages)

PAGE 1
9-1928; Rev 0; 1/01 KIT ATION EVALU E L B A AVAIL 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs ____________________________Features The MAX115/MAX116 are high-speed, multichannel, 12-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 12-bit, 2µs, successive-approximation analog-to-digital converter (ADC), a +2.
PAGE 2
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ...........................................................-0.3V to 6V AVSS to AGND ............................................................0.3V to -6V DVDD to DGND ...........................................................-0.3V to 6V AGND to DGND .......................................................-0.3V to 0.3V CH_ _ to AGND....................................................................
PAGE 3
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs (AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Input Voltage Range VIN Input Current IIN Input Capacitance CIN MAX115 ±5 MAX116 ±2.
PAGE 4
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs (See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C, unless otherwise noted.
PAGE 6
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs ______________________________________________________________Pin Description PIN NAME FUNCTION 1, 2 CH2B, CH2A Channel 2 Multiplexed Inputs (single-ended) 3, 4 CH1B, CH1A Channel 1 Multiplexed Inputs (single-ended) 5 AVDD Analog Supply Voltage 6 REFIN External reference input/internal reference output. Bypass with a 0.1µF capacitor to AGND. 7 REFOUT 8, 36 AGND 9–16 D11–D4 Data Bits. D11 = MSB.
PAGE 7
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs AGND MAX115/MAX116 REFIN REFOUT BANDGAP REFERENCE 10kΩ CH1A A CH1B CH2A B A B MUX T/H 2.50V MUX T/H VREF CH2B MUX COMP CH3A A B MUX T/H CH3B 12-BIT DAC CH4A A CH4B B MUX SAR T/H VREF A0 4x12 RAM A1 D0/A2 AVDD D1/A3 AGND THREE-STATE OUTPUT DRIVERS AVSS D2 D3 D11 (MSB) CONTROL LOGIC 10MHz CLOCK MAX115 MAX116 BUS INTERFACE CLK CONVST INT CS RD WR DVDD DGND Figure 2.
PAGE 8
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs HOLD R1 BUFFER CH_A S1A S2A C HOLD 7pF HOLD R2 FROM MICROSEQUENCER TRACK TRACK R3 C IN S3A MUX R1 S1B S2B R2 CH_B C IN R3 S3B REFOUT DAC MAX115 MAX116 MAX115: R1 = ∞, R2 = R3 = 5kΩ MAX116: R1 = R2 = 5kΩ, R3 = ∞ SAR Figure 3. Equivalent Input Circuit The conversion timing and control sequences are derived from either an internal clock or an external clock, the CONVST signal, and the programmed mode.
PAGE 9
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 tCW CONVST tCONV INT tACQ tID tCWH tCWS CS tCRS tCRH RD tRD t WR t RD WR tDA tDH DATA CH1 DATA IN CH2 CH3 CH4 tAS tAH Figure 4. Timing Diagram acquisition time between conversions. The analog input appears as a 10kΩ resistor in parallel with a 16pF capacitor for the MAX115 and as a 1MΩ resistor in parallel with a 16pF capacitor for the MAX116.
PAGE 10
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs Table 1.
PAGE 11
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 OUTPUT CODE 011 . . . 111 REFOUT TO DAC 7 (2.5V) 011 . . . 110 4.7µF 000 . . . 010 000 . . . 001 AV = 1 000 . . . 000 REFIN MAX115 MAX116 6 111 . . . 111 (2.5V) OUT 111 . . . 110 111 . . . 101 MAX6325 10k 100 . . . 001 100 . . . 000 ZERO - FS 2.5V +FS - 1LSB INPUT VOLTAGE (LSB) MAX115: FS = 2 x VREFOUT, 1LSB = 4VREFOUT 4096 MAX116: FS = VREFOUT, 1LSB = 2VREFOUT 4096 Figure 7. External Reference Figure 8.
PAGE 12
MAX115/MAX116 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs VCC VCC HC161 1/2 HC74 PRE Q D Q CLR ENP ENT RD LOAD HC688 CLR VCC INT A B (LSB) 0 P0 1 C 2 D 3 RCO P1 P2 P3 P4 P5 P6 P7 EXTERNAL CLOCK VCC P=Q Q0 Q1 LATCH CLOCK (TO 16373 LATCH) Q2 Q3 10kΩ Q4 Q5 Q6 Q7 G CH1 0 0 CH2 1 0 CH3 0 1 CH4 1 1 EXTERNAL CLOCK Figure 9. Output Demultiplexer Circuit (LSB) values. Output coding is two-complement binary with 1LSB = 2.44mV for the MAX115 and 1LSB = 1.22mV for the MAX116.
PAGE 13
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 MAIN DC RESOLVER/ ENCODER AC AC MOTOR MOTOR 12 CH1 MAX115 MAX116 12 BIT ADC + MICROSEQUENCER B AUX A SIMULTANEOUS T/H DSP BUFFER A CH2 B MAIN DC R/E VOLTAGE/POSITION FEEDBACK POWER STAGE CONTROLLER CURRENT/TORQUE FEEDBACK EXTERNAL SETPOINTS A CH3 B A CH4 B TEMP VELOCITY FEEDBACK µC Figure 10. Vector Motor Control part of the current (torque) feedback loop.
PAGE 14
Bypass AVDD and AVSS with 0.1µF ceramic capacitors to AGND. Mount them with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Bypass DVDD with a 0.1µF ceramic capacitor to DGND. Chip Information TRANSISTOR COUNT: 4116 SUBSTRATE CONNECTED TO AVSS PROCESS: BiCMOS ________________________________________________________Package Information SSOP.