Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal QSOP 16

General Description

The MAX11618–MAX11621/MAX11624/MAX11625 are

serial 10-bit analog-to-digital converters (ADCs) with an

internal reference. These devices feature on-chip FIFO,

scan mode, internal clock mode, internal averaging,

and AutoShutdown™. The maximum sampling rate is

300ksps using an external clock. The MAX11624/

MAX11625 have 16 input channels, the MAX11620/

MAX11621 have 8 input channels, and the MAX11618/

MAX11619 have 4 input channels. These six devices

operate from either a +3V supply or a +5V supply, and

contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-com-

patible serial port.

The MAX11618–MAX11621 are available in 16-pin

QSOP packages. The MAX11624/MAX11625 are avail-

able in 24-pin QSOP packages. All six devices are

specified over the extended -40°C to +85°C tempera-

ture range.

Applications

System Supervision

Data-Acquisition Systems

Industrial Control Systems

Patient Monitoring

Data Logging

Instrumentation

Features

o Analog Multiplexer with Track/Hold

16 Channels (MAX11624/MAX11625)

8 Channels (MAX11620/MAX11621)

4 Channels (MAX11618/MAX11619)

o Single Supply

2.7V to 3.6V (MAX11619/MAX11621/MAX11625)

4.75V to 5.25V

(MAX11618/MAX11620/MAX11624)

o Internal Reference

2.5V (MAX11619/MAX11621/MAX11625)

4.096V (MAX11618/MAX11620/MAX11624)

o External Reference: 1V to V

o 16-Entry First-In/First-Out (FIFO)

o Scan Mode, Internal Averaging, and Internal Clock

o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing

Codes Over Temperature

o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible

Interface

o Small Packages

16-Pin QSOP (MAX11618–MAX11621)

24-Pin QSOP (MAX11624/MAX11625)

MAX11618–MAX11621/MAX11624/MAX11625

10-Bit, 300ksps ADCs

with FIFO and Internal Reference

________________________________________________________________

Maxim Integrated Products

19-5961; Rev 1; 9/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART

NUMBER

INPUTS

SUPPLY

VOLTAGE

RANGE (V)

PIN-

PACKAGE

MAX11618EEE+T 4 4.75 to 5.25 16 QSOP

MAX11619EEE+T 4 2.7 to 3.6 16 QSOP

MAX11620EEE+T 8 4.75 to 5.25 16 QSOP

MAX11621EEE+T 8 2.7 to 3.6 16 QSOP

MAX11624EEG+T 16 4.75 to 5.25 24 QSOP

MAX11625EEG+T 16 2.7 to 3.6 24 QSOP

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Note: All devices are specified over the -40°C to +85°C operating

temperature range.

Denotes a lead(Pb)-free/RoHS-compliant package.

Summary of content (21 pages)

PAGE 1
9-5961; Rev 1; 9/11 10-Bit, 300ksps ADCs with FIFO and Internal Reference The MAX11618–MAX11621/MAX11624/MAX11625 are serial 10-bit analog-to-digital converters (ADCs) with an internal reference. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock. The MAX11624/ MAX11625 have 16 input channels, the MAX11620/ MAX11621 have 8 input channels, and the MAX11618/ MAX11619 have 4 input channels.
PAGE 2
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN14, CNVST/AIN_, REF to GND ...........................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.
PAGE 3
10-Bit, 300ksps ADCs with FIFO and Internal Reference (V DD = 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V DD = 4.75V to 5.25V (MAX11618/MAX11620/MAX11624), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11619//MAX11621/MAX11625); VREF = 4.096V (MAX11618/MAX11620/MAX11624), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued) (V DD = 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V DD = 4.75V to 5.25V (MAX11618/MAX11620/MAX11624), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11619//MAX11621/MAX11625); VREF = 4.096V (MAX11618/MAX11620/MAX11624), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
10-Bit, 300ksps ADCs with FIFO and Internal Reference (V DD = 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V DD = 4.75V to 5.25V (MAX11618/MAX11620/MAX11624), f SAMPLE = 300kHz, f SCLK = 4.8MHz (50% duty cycle), V REF = 2.5V (MAX11619/MAX11621/MAX11625); V REF = 4.096V (MAX11618/MAX11620/MAX11624), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (continued) (VDD = 3V (MAX11619/MAX11621/MAX11625); VDD = 5V (MAX11618/MAX11620/MAX11624), fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) SINAD vs. FREQUENCY 0.3 64 MAX11618/MAX11620/ MAX11624 63 MAX11618/MAX11620/ MAX11624 90 SINAD (dB) 0.1 0 -0.1 61 SFDR (dB) 62 0.2 MAX11619/MAX11621/ MAX11625 60 59 80 MAX11619/MAX11621/ MAX11625 70 58 -0.2 57 MAX11619/MAX11621/ MAX11625 fSAMPLE = 300ksps -0.4 55 -0.
PAGE 7
10-Bit, 300ksps ADCs with FIFO and Internal Reference SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.7 EXTERNAL REFERENCE 1000 800 0.5 IDD (µA) IDD (µA) 1200 0.4 0.2 MAX11619/MAX11621/ MAX11625 fSAMPLE = 300ksps 400 200 MAX11618/MAX11620/ MAX11624 VDD = 5V 0.1 MAX11619/MAX11621/ MAX11625 VDD = 3V 0.1 0 0 0 0.3 0.2 0.3 600 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3V (MAX11619/MAX11621/MAX11625); VDD = 5V (MAX11618/MAX11620/MAX11624), fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 2.500 4.096 2.499 4.095 2.498 2.497 4.094 4.85 4.95 5.05 5.15 3.6 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.
PAGE 9
10-Bit, 300ksps ADCs with FIFO and Internal Reference 0.6 -1.0 85 60 35 -40 TEMPERATURE (°C) -15 10 35 60 4.75 85 4.95 5.25 GAIN ERROR vs. TEMPERATURE 1.0 MAX11618 toc27 -0.1 MAX11618/MAX11620 MAX11624 fSAMPLE = 300ksps 0.6 GAIN ERROR (LSB) MAX11619/MAX11621/ MAX11625 fSAMPLE = 300ksps 5.15 5.05 VDD (V) GAIN ERROR vs. SUPPLY VOLTAGE 0 GAIN ERROR (LSB) 4.85 TEMPERATURE (°C) MAX11618 toc28 10 0.1 0 0.4 -15 0.2 0.
PAGE 10
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference Pin Configurations + TOP VIEW + AIN0 1 24 EOC AIN1 2 23 DOUT 22 DIN AIN0 1 16 EOC AIN2 3 AIN1 2 15 DOUT AIN3 4 14 DIN AIN4 5 13 SCLK AIN5 6 19 VDD 18 GND AIN2 3 AIN3 4 MAX11618– MAX11621 21 SCLK MAX11624– MAX11625 20 CS 12 CS AIN6 7 AIN5 (N.C.) 6 11 VDD AIN7 8 17 REF AIN6 (N.C.) 7 10 GND AIN8 9 16 CNVST/AIN15 9 AIN9 10 15 AIN14 AIN10 11 14 AIN13 AIN11 12 13 AIN12 AIN4 (N.C.
PAGE 11
10-Bit, 300ksps ADCs with FIFO and Internal Reference MAX11618–MAX11621/MAX11624/MAX11625 CS tCP tCH tCSS0 tCSH1 tCL tCSH0 tCSS1 SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN0 AIN1 T/H AIN15 10-BIT SAR ADC FIFO AND ACCUMULATOR INTERNAL REFERENCE REF MAX11618–MAX11621 MAX11624/MAX11625 Figure 2.
PAGE 12
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference Converter Operation The MAX11618–MAX11621/MAX11624/MAX11625 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage signals into a 10-bit digital result. This singleended configuration supports unipolar signal ranges.
PAGE 13
10-Bit, 300ksps ADCs with FIFO and Internal Reference where RIN = 1.5kΩ, RS is the source impedance of the input signal, and tPWR = 1µs, the power-up time of the device. The varying power-up times are detailed in the explanation of the clock mode conversions. When the conversion is internally timed, tACQ is never less than 1.4µs, and any source impedance below 300Ω does not significantly affect the ADC’s AC performance.
PAGE 14
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01.
PAGE 15
10-Bit, 300ksps ADCs with FIFO and Internal Reference BIT NAME BIT — 7 (MSB) — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. MAX11618–MAX11621/MAX11624/MAX11625 Table 3. Setup Register* FUNCTION Set to zero to select setup register. REFSEL0 2 Reference mode configuration. — 1 Don’t care. — 0 (LSB) Don’t care. *See below for bit details.
PAGE 16
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) Set to 0 to select averaging register. FUNCTION — 6 Set to 0 to select averaging register. — 5 Set to 1 to select averaging register. AVGON 4 Set to 1 to turn averaging on. Set to zero to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans.
PAGE 17
10-Bit, 300ksps ADCs with FIFO and Internal Reference Output Data Format Figures 4–7 illustrate the conversion timing for the MAX11618–MAX11621/MAX11624/MAX11625. The 10bit conversion result is output in MSB-first format with four leading zeros followed by 10-bit data and two trailing zeros. DIN data is latched into the serial interface on the rising edge of SCLK. Data on DOUT transitions on the falling edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST.
PAGE 18
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6.
PAGE 19
10-Bit, 300ksps ADCs with FIFO and Internal Reference (ACQUISITION1) (ACQUISITION2) (CONVERSION1) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eight and ninth cycles, the pulse width must be less than 100µs.
PAGE 20
MAX11618–MAX11621/MAX11624/MAX11625 10-Bit, 300ksps ADCs with FIFO and Internal Reference Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX11618–MAX11621/MAX11624/MAX11625 is measured using the end-point method.
PAGE 21
10-Bit, 300ksps ADCs with FIFO and Internal Reference REVISION NUMBER REVISION DATE 0 6/11 Initial release 1 9/11 Released MAX11618–MAX11621. Updated Absolute Maximum Ratings, Transfer Function section, and Package Information. DESCRIPTION PAGES CHANGED — 1, 2, 19, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.