Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 16

General Description

The MAX11626–MAX11629/MAX11632/MAX11633 are

serial 12-bit analog-to-digital converters (ADCs) with an

internal reference. These devices feature on-chip FIFO,

scan mode, internal clock mode, internal averaging, and

AutoShutdown™. The maximum sampling rate is 300ksps

using an external clock. The MAX11632/MAX11633 have

16 input channels; the MAX11628/MAX11629 have 8

input channels; and the MAX11626/MAX11627 have 4

input channels. These six devices operate from either a

+3V supply or a +5V supply, and contain a 10MHz SPI-/

QSPI™-/MICROWIRE

-compatible serial port.

The MAX11626–MAX11629 are available in 16-pin QSOP

packages. The MAX11632/MAX11633 are available in

24-pin QSOP packages. All six devices are specified over

the extended -40°C to +85°C temperature range.

Applications

● System Supervision

● Data-Acquisition Systems

● Industrial Control Systems

● Patient Monitoring

● Data Logging

● Instrumentation

Features

● Analog Multiplexer with Track/Hold

• 16 Channels (MAX11632/MAX11633)

• 8 Channels (MAX11628/MAX11629)

• 4 Channels (MAX11626/MAX11627)

● Single Supply

• 2.7V to 3.6V (MAX11627/MAX11629/MAX11633)

• 4.75V to 5.25V

(MAX11626/MAX11628/MAX11632)

● Internal Reference

• 2.5V (MAX11627/MAX11629/MAX11633)

• 4.096V (MAX11626/MAX11628/MAX11632)

● External Reference: 1V to V

● 16-Entry First-In/First-Out (FIFO)

● Scan Mode, Internal Averaging, and Internal Clock

● Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing

Codes Over Temperature

● 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible

Interface

● Small Packages

• 16-Pin QSOP (MAX11626–MAX11629)

• 24-Pin QSOP (MAX11632/MAX11633)

Pin Configurations continued at end of data sheet.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

19-5323; Rev 5; 9/14

Note: All devices are specified over the -40°C to +85°C operat-

ing temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART

NUMBER

INPUTS

SUPPLY

VOLTAGE

RANGE (V)

PACKAGE

MAX11626EEE+ 4 4.75 to 5.25 16 QSOP

MAX11627EEE+ 4 2.7 to 3.6 16 QSOP

MAX11628EEE+ 8 4.75 to 5.25 16 QSOP

MAX11629EEE+ 8 2.7 to 3.6 16 QSOP

MAX11632EEG+ 16 4.75 to 5.25 24 QSOP

MAX11633EEG+ 16 2.7 to 3.6 24 QSOP

AIN0

TOP VIEW

EOC

DOUT

DIN

SCLK

GND

REF

MAX11626–

MAX11629

QSOP

AIN1

AIN2

AIN5 (N.C.)

AIN3

AIN4 (N.C.)

AIN6 (N.C.)

AIN7/(CNVST)

() MAX11626/MAX11627 ONLY

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Pin Congurations

Ordering Information

EVALUATION KIT AVAILABLE

Summary of content (22 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference General Description The MAX11626–MAX11629/MAX11632/MAX11633 are serial 12-bit analog-to-digital converters (ADCs) with an internal reference. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock.
PAGE 2
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Absolute Maximum Ratings VDD to GND.............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND...... -0.3V to (VDD + 0.3V) AIN0–AIN13, AIN_, CNVST/AIN_, REF to GND.......................................... -0.3V to (VDD + 0.3V) Maximum Current into Any Pin...........................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.
PAGE 3
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Electrical Characteristics (continued) (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Electrical Characteristics (continued) (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Timing Characteristics (Figure 1) (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE =300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/ MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted. VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.) 0 -0.2 -0.6 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps -0.8 -1.0 70 MAX11627/MAX11629/MAX11633 65 60 -0.
PAGE 7
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted. VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.) INTERNAL REFERENCE 1600 0.8 0.7 0.6 EXTERNAL REFERENCE 1000 800 0.4 0.3 600 0.
PAGE 8
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted. VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.) 0.4 10 35 60 85 4.85 MAX11626 toc20 2.52 10 35 60 2.49 2.48 2.47 85 -15 1.04 1.03 1.
PAGE 9
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Typical Operating Characteristics (continued) (VDD = +5V, VREF = +4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted. VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.) GAIN ERROR vs. SUPPLY VOLTAGE 0.4 0.3 0.2 0 4.75 4.85 4.95 5.05 5.15 -0.2 -0.3 -0.
PAGE 10
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Pin Description MAX11626 MAX11627 (4 CHANNELS) MAX11628 MAX11629 (8 CHANNELS) MAX11632 MAX11633 (16 CHANNELS) 5, 6, 7 — — N.C. — — 1–15 AIN0–AIN14 Analog Inputs NAME FUNCTION No Connection. Not internally connected. — 1–7 — AIN0–AIN6 Analog Inputs 1–4 — — AIN0–AIN3 Analog Inputs — — 16 CNVST/AIN15 Active-Low Conversion Start Input/Analog Input 15.
PAGE 11
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference CS tCSS0 tCL SCLK tCP tCH tCSH1 tCSH0 tCSS1 tDH tDS DIN tDOT tDOE tDOD DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN1 AIN2 T/H AIN15 12-BIT SAR ADC FIFO AND ACCUMULATOR INTERNAL REFERENCE REF MAX11626–MAX11629/MAX11632/MAX11633 Figure 2.
PAGE 12
MAX11626–MAX11629/ MAX11632/MAX11633 Converter Operation The MAX11626–MAX11629/MAX11632/MAX11633 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage signals into a 12-bit digital result. This single-ended configuration supports unipolar signal ranges.
PAGE 13
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11626– MAX11629/MAX11632/MAX11633’s input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15. A negative input capacitor is connected to GND. For external T/H timing, use clock mode 01. After the T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted.
PAGE 14
MAX11626–MAX11629/ MAX11632/MAX11633 Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. A conversion is not performed if it is requested on a channel that has been configured as CNVST.
PAGE 15
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Table 3. Setup Register* BIT NAME BIT FUNCTION — 7 (MSB) Set to 0 to select setup register. — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. REFSEL0 2 Reference mode configuration. — 1 Don’t care. — 0 (LSB) Don’t care. *See below for bit details.
PAGE 16
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT FUNCTION — 7 (MSB) Set to 0 to select averaging register. — 6 Set to 0 to select averaging register. — 5 Set to 1 to select averaging register. AVGON 4 Set to 1 to turn averaging on. Set to 0 to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans.
PAGE 17
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Power-Up Default State The MAX11626–MAX11629/MAX11632/MAX11633 power up with all blocks in shutdown, including the reference. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1) Output Data Format Figures 4–7 illustrate the conversion timing for the MAX11626–MAX11629/MAX11632/MAX11633.
PAGE 18
MAX11626–MAX11629/ MAX11632/MAX11633 CNVST 12-Bit, 300ksps ADCs with FIFO and Internal Reference (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS SCLK (CONVERSION1) DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 Timing (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6.
PAGE 19
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference (CONVERSION BYTE) DIN (ACQUISITION1) (ACQUISITION2) (CONVERSION1) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Timing Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eight and ninth cycles, the pulse width must be less than 100μs.
PAGE 20
MAX11626–MAX11629/ MAX11632/MAX11633 Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX11626–MAX11629/MAX11632/MAX11633 is measured using the end-point method.
PAGE 21
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Pin Configurations Chip Information PROCESS: BiCMOS TOP VIEW AIN0 1 + 24 EOC AIN1 2 23 DOUT AIN2 3 22 DIN AIN3 4 AIN4 5 21 SCLK MAX11632 MAX11633 20 CS Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 22
MAX11626–MAX11629/ MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 6/10 Initial release — 1 8/10 Initial release of MAX11628/MAX11629 and changed internal reference voltage 1 2 3/11 Added MAX11628 automotive qualified part to data sheet 1 3 10/11 Initial release of MAX11626/MAX11627 1 4 10/11 Updated the Electrical Characteristics, Typical Operating Characteristics global, and Time Differential Anal