9-5962; Rev 1; 9/11 KIT ATION EVALU E L B A AVAIL 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Features o Analog Multiplexer with True Differential Track/Hold 8-/4-Channel Single-Ended 4-/2-Channel True Differential Unipolar or Bipolar Inputs Applications System Supervision o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Interface Data-Acquisition Systems o Small 16-Pin QSOP Package o Single Supply 2.7V to 3.6V (MAX11635/MAX11637) 4.75V to 5.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN5, REF-/AIN6, CNVST/AIN7, REF+ to GND.........................................-0.3V to (VDD + 0.3V) Maximum Current into any Pin ............................................
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference (VDD = 2.7V to 3.6V (MAX11635/MAX11637), VDD = 4.75V to 5.25V (MAX11634/MAX11636), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11635/MAX11637), VREF = 4.096V (MAX11634/MAX11636) TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX11635/MAX11637), VDD = 4.75V to 5.25V (MAX11634/MAX11636), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11635/MAX11637), VREF = 4.096V (MAX11634/MAX11636) TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 TIMING CHARACTERISTICS (Figure 1) PARAMETER SYMBOL SCLK Clock Period tCP SCLK Pulse-Width High tCH SCLK Pulse-Width Low CONDITIONS MIN Externally clocked conversion 208 Data I/O 100 TYP MAX UNITS ns 40 tCL ns 40 ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 40 ns CS Rise to DOUT Disable tDOD CLOAD = 30pF 40 ns CS Fall to DOUT Enable tDOE CLOAD = 30pF 40 ns DIN to SCLK Rise Set
Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) SFDR vs. FREQUENCY SINAD vs. FREQUENCY 0.6 MAX11634/MAX11636 75 SINAD (dB) 0.4 0.2 0 -0.2 MAX11634/MAX11636 90 70 SFDR (dB) 0.8 100 MAX11634 toc05 80 MAX11634 toc04 1.0 MAX11635/MAX11637 65 80 70 60 -0.4 -0.
12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL REFERENCE 0.8 1600 0.7 EXTERNAL REFERENCE 800 0.5 IDD (µA) IDD (µA) 1200 0.4 0.2 0.3 600 0.3 0.2 400 0.1 MAX11634/MAX11636 VDD = 5V 0.1 0 0 4.75 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.85 4.95 5.05 MAX11635/MAX11637 VDD = 3V 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) VDD (V) VDD (V) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs.
Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE VREF (V) 4.097 4.096 4.11 2.500 2.499 4.095 4.85 4.95 5.05 5.25 5.15 4.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference 0.9 0.5 -0.1 GAIN ERROR (LSB) 1.1 0 MAX11634 toc26 MAX11634 toc25 0.6 GAIN ERROR (LSB) 0.4 0.3 -0.2 -0.3 0.2 0.7 -0.4 MAX11634/MAX11636 fSAMPLE = 300ksps 0.1 MAX11635/MAX11637 fSAMPLE = 300ksps -15 10 35 60 4.75 85 4.85 4.95 5.05 5.15 3.0 3.6 3.3 TEMPERATURE (°C) VDD (V) VDD (V) GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE SAMPLING ERROR vs. SOURCE IMPEDANCE 0.3 GAIN ERROR (LSB) 0.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 Pin Configuration TOP VIEW AIN0 1 + 16 EOC AIN1 2 15 DOUT AIN2 3 14 DIN AIN3 4 AIN4 (N.C.) 5 MAX11634– MAX11637 13 SCLK 12 CS AIN5 (N.C.) 6 11 VDD REF-/AIN6 (REF-) 7 10 GND CNVST/AIN7 (CNVST) 8 9 REF+ QSOP ( ) PINOUT FOR THE MAX11634/MAX11635. Pin Description PIN MAX11636 MAX11637 NAME 1–4 — AIN0–AIN3 5, 6 — N.C. No Connection. Not internally connected.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 CS tCP tCH tCSS0 tCSH1 tCL tCSH0 tCSS1 SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN0 AIN1 T/H 12-BIT SAR ADC FIFO AND ACCUMULATOR AIN7 REFREF+ INTERNAL REFERENCE MAX11634–MAX11637 Figure 2.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Converter Operation The MAX11634–MAX11637 ADCs use a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert temperature and voltage signals into a 12-bit digital result. Both single-ended and differential configurations are supported, with a unipolar signal range for singleended mode and bipolar or unipolar ranges for differential mode.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference CIN+ DAC COMPARATOR + HOLD GND (SINGLE-ENDED); AIN1, AIN3, AIN5, AIN7 (DIFFERENTIAL) CIN- HOLD HOLD VDD/2 Figure 3. Equivalent Input Circuit Unipolar/Bipolar Address the unipolar and bipolar registers through the setup register (bits 1 and 0). Program a pair of analog channels for differential operation by writing a 1 to the appropriate bit of the bipolar or unipolar register.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Applications Information Register Descriptions The MAX11634–MAX11637 communicate between the internal registers and the external circuitry through the SPI/QSPI-compatible serial interface. Table 1 details the registers and the bit names. Tables 2–7 show the various functions within the conversion register, setup register, averaging register, reset register, unipolar register, and bipolar register.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference BIT NAME — BIT FUNCTION 7 (MSB) Set to 1 to select conversion register X 6 Don’t care CHSEL2 5 Analog input channel select CHSEL1 4 Analog input channel select CHSEL0 3 Analog input channel select SCAN1 2 Scan mode select 1 Scan mode select SCAN0 X 0 (LSB) Don’t care *See below for bit details.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set to 0 to select setup register FUNCTION — 6 Set to 1 to select setup register CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST. Conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. Data is binary for unipolar mode and two’s complement for bipolar mode. Table 4.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Table 6. Averaging Register* BIT NAME BIT — 7 (MSB) Set to 0 to select averaging register FUNCTION — 6 Set to 0 to select averaging register Set to 1 to select averaging register — 5 AVGON 4 Set to 1 to turn averaging on. Set to 0 to turn averaging off.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Performing Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 4 for clock mode 00 timing. Initiate a scan by setting CNVST low for at least 40ns before pulling it high again.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6.
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference (ACQUISITION1) (CONVERSION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the second byte of data that is read out contains the next 8 bits (not b[7:0]).
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference OUTPUT CODE OUTPUT CODE FULL-SCALE TRANSITION 11. . .111 11. . .110 11. . .101 011. . . 111 V FS = REF + VCOM 2 011. . .110 ZS = COM 000. . . 010 000. . .001 FS = VREF + VCOM ZS = VCOM V 1 LSB = REF 4096 00. . .011 00. . .010 -VREF + VCOM 2 VREF 1 LSB = 4096 -FS = 000. . .000 111 . . .111 111 . . . 110 111 . . . 101 100 . . . 001 00. . . 001 100. . . 000 00. . .
12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Revision History REVISION NUMBER REVISION DATE 0 6/11 Initial release 1 9/11 Released the MAX11636/MAX11637 and revised the Transfer Function section. DESCRIPTION PAGES CHANGED — 1, 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.