Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal uMAX 8

General Description

The MAX11644/MAX11645 low-power, 12-bit, 1-/2-

channel analog-to-digital converters (ADCs) feature

internal track/hold (T/H), voltage reference, clock, and

an I

C-compatible 2-wire serial interface. These

devices operate from a single supply of 2.7V to 3.6V

(MAX11645) or 4.5V to 5.5V (MAX11644) and require

only 6μA at a 1ksps sample rate. AutoShutdown™ pow-

ers down the devices between conversions, reducing

supply current to less than 1μA at low throughput rates.

The MAX11644/MAX11645 each measure two single-

ended or one differential input. The fully differential ana-

log inputs are software configurable for unipolar or

bipolar, and single-ended or differential operation.

The full-scale analog input range is determined by the

internal reference or by an externally applied reference

voltage ranging from 1V to V

. The MAX11645 fea-

tures a 2.048V internal reference and the MAX11644

features a 4.096V internal reference.

The MAX11644/MAX11645 are available in an ultra-tiny

1.9mm x 2.2mm WLP package and an 8-pin μMAX

package. The MAX11644/MAX11645 are guaranteed

over the extended temperature range (-40°C to +85°C).

For pin-compatible 10-bit parts, refer to the MAX11646/

MAX11647 data sheet.

Applications

Features

♦ Ultra-Tiny 1.9mm x 2.2mm Wafer Level Package

♦ High-Speed I

C-Compatible Serial Interface

400kHz Fast Mode

1.7MHz High-Speed Mode

♦ Single-Supply

2.7V to 3.6V (MAX11645)

4.5V to 5.5V (MAX11644)

♦ Internal Reference

2.048V (MAX11645)

4.096V (MAX11644)

♦ External Reference: 1V to V

♦ Internal Clock

2-Channel Single-Ended or 1-Channel Fully

Differential

♦ Internal FIFO with Channel-Scan Mode

♦ Low Power

670µA at 94.4ksps

230µA at 40ksps

60µA at 10ksps

6µA at 1ksps

0.5µA in Power-Down Mode

♦ Software-Configurable Unipolar/Bipolar

MAX11644/MAX11645

Low-Power, 1-/2-Channel, I

C, 12-Bit ADCs

in Ultra-Tiny 1.9mm x 2.2mm Package

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-5225; Rev 1; 9/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE

PIN-

PACKAGE

C SLAVE

ADDRESS

MAX11644EUA+ -40°C to +85°C 8 μMAX 0110110

MAX11645EUA+ -40°C to +85°C 8 μMAX 0110110

MAX11645EWC+ -40°C to +85°C 12 WLP 0110110

Typical Operating Circuit and Selector Guide appear at end

of data sheet.

AutoShutdown is a trademark and μMAX is a registered trademark

of Maxim Integrated Products, Inc.

Denotes a lead(Pb)-free/RoHs-compliant package.

Handheld Portable

Applications

Medical Instruments

Battery-Powered Test

Equipment

Solar-Powered Remote

Systems

Received-Signal-Strength

Indicators

System Supervision

Power-Supply Monitoring

Summary of content (22 pages)

PAGE 1
9-5225; Rev 1; 9/10 KIT ATION EVALU E L B AVAILA Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VDD. The MAX11645 features a 2.048V internal reference and the MAX11644 features a 4.096V internal reference. The MAX11644/MAX11645 are available in an ultra-tiny 1.9mm x 2.2mm WLP package and an 8-pin μMAX® package.
PAGE 2
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package ABSOLUTE MAXIMUM RATINGS Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) μMAX only .....................................................................+300°C Soldering Temperature (reflow) ................
PAGE 3
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package (VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.
PAGE 4
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package TIMING CHARACTERISTICS (Figure 1) (VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.
PAGE 5
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package (VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time of SCL Signal After Acknowledge Bit tRCL1 Measured from 0.3VDD - 0.
PAGE 6
Typical Operating Characteristics (VDD = 3.3V (MAX11645), VDD = 5V (MAX11644), fSCL = 1.7MHz, 50% duty cycle, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL CODE 0.8 0.6 0.4 0.1 0.2 INL (LSB) 0.2 0 -0.1 0 -0.2 -0.2 -0.4 -0.3 -0.6 -0.4 -0.8 -0.5 500 1000 1500 2000 2500 3000 3500 4000 0 DIGITAL OUTPUT CODE 0 30k 40k MAX11644 toc05 MAX11644 toc04 0.6 SDA = SCL = VDD 0.5 0.4 600 INTERNAL REFERENCE MAX11645 0.3 500 0.
PAGE 7
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE NORMALIZED TO VALUE AT TA = +25°C MAX11644 1.00006 1.0004 1.00004 1.0002 1.00002 1.0000 0.9994 1.00000 0.99998 0.9998 0.9996 MAX11644 NORMALIZED TO REFERENCE VALUE AT VDD = 5V 1.00008 VREF (V) VREF NORMALIZED 1.0006 1.00010 0.99996 MAX11645 0.99992 0.9990 0.
PAGE 8
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package MAX11644/MAX11645 Pin Configuration TOP VIEW (BUMPS ON BOTTOM) 1 3 4 MAX11645 TOP VIEW + AIN0 1 AIN1 2 N.C. 2 3 MAX11644 MAX11645 REF 4 8 VDD 7 GND 6 SDA 5 SCL µMAX A AIN0 AIN1 GND REF B GND GND GND GND C VDD GND SDA SCL WLP Pin Description PIN 8 NAME FUNCTION μMAX WLP 1,2 A1, A2 AIN0, AIN1 3 — N.C. No connection. Not internally connected. 4 A4 REF Reference Input/Output.
PAGE 9
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package tR tF MAX11644/MAX11645 A) F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING t SDA tSU,DAT tHD,DAT tLOW tHD,STA tBUF tSU,STA tSU,STO SCL tHD,STA tHIGH tR tF S A Sr P B) HS-MODE 2-WIRE SERIAL-INTERFACE TIMING S tRDA tFDA SDA tSU,DAT tHD,DAT tLOW tBUF tHD,STA tSU,STO tSU,STA SCL tHD,STA tHIGH tRCL tFCL tRCL1 S Sr HS MODE A P S F/S MODE Figure 1.
PAGE 10
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package SDA SCL INPUT SHIFT REGISTER VDD SETUP REGISTER GND CONTROL LOGIC INTERNAL OSCILLATOR CONFIGURATION REGISTER AIN0 AIN1 T/H ANALOG INPUT MUX 12-BIT ADC OUTPUT SHIFT REGISTER AND RAM REF REFERENCE 4.096V (MAX11644) 2.048V (MAX11645) MAX11644 MAX11645 REF Figure 2. Simplified Functional Diagram serial interface supporting data rates up to 1.7MHz.
PAGE 11
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package MAX11645 hold SCL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = 1) bit. Hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 12 clock cycles.
PAGE 12
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Analog Input Range and Protection Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below GND or above VDD.
PAGE 13
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package operate in high-speed mode (HS mode) to achieve conversion rates up to 94.4ksps. Figure 1 shows the bus timing for the MAX11644/MAX11645’s 2-wire interface. HS Mode At power-up, the MAX11644/MAX11645 bus timing is set for F/S mode. The bus master selects HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care).
PAGE 14
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by seven address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX11644/MAX11645 (slave) issues an acknowledge. The master then writes to the slave.
PAGE 15
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package MAX11644/MAX11645 Table 2. Configuration Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SCAN1 SCAN0 X X X CS0 SGL/DIF BIT NAME 7 REG 6 SCAN1 5 SCAN0 4 X 3 X 2 X 1 CS0 0 SGL/DIF DESCRIPTION Register bit. 1 = setup byte (see Table 1), 0 = configuration byte. Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.
PAGE 16
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Data Byte (Read Cycle) A read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a START condition followed by seven address bits and a read bit (R/W = 1). If the address byte is successfully received, the MAX11644/MAX11645 (slave) issues an acknowledge. The master then reads from the slave.
PAGE 17
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Use internal clock mode if the SCL clock period exceeds 60μs. The MAX11644/MAX11645 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps, internal clock mode is recommended due to much smaller power consumption. Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations.
PAGE 18
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Table 6.
PAGE 19
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Layout, Grounding, and Bypassing Only use PCBs. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC package.
PAGE 20
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals. SUPPLIES 3V OR 5V VLOGIC = 3V/5V GND 4.7μF R* = 5Ω Effective Number of Bits 0.
PAGE 21
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Selector Guide 3.3V or 5V PART 0.1μF VDD RS* AIN0 ANALOG INPUTS AIN1 MAX11644 MAX11645 CREF 0.1μF 2 singleended/1 differential 4.096 4.5 to 5.5 ±1 MAX11645 2 singleended/1 differential 2.048 2.7 to 3.
PAGE 22
MAX11644/MAX11645 Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Revision History REVISION NUMBER REVISION DATE 0 4/10 Initial release 1 9/10 Added the WLP package to the Ordering Information, Absolute Maximum Ratings, Pin Configuration, Pin Description, and Package Information sections DESCRIPTION PAGES CHANGED — 1, 2, 8, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.