Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal uMAX 8

General Description

The MAX11646/MAX11647 low-power, 10-bit, 1-/2-

channel analog-to-digital converters (ADCs) feature

internal track/hold (T/H), voltage reference, a clock, and

an I

C-compatible 2-wire serial interface. These

devices operate from a single supply of 2.7V to 3.6V

(MAX11647) or 4.5V to 5.5V (MAX11646) and require

only 6µA at a 1ksps sample rate. AutoShutdown™ pow-

ers down the devices between conversions, reducing

supply current to less than 1µA at lower throughput

rates. The MAX11646/MAX11647 each measure two

single-ended or one differential input. The fully differen-

tial analog inputs are software configurable for unipolar

or bipolar and single-ended or differential operation.

The full-scale analog input range is determined by the

internal reference or by an externally applied reference

voltage ranging from 1V to V

. The MAX11647 fea-

tures a 2.048V internal reference and the MAX11646

features a 4.096V internal reference.

The MAX11646/MAX11647 are available in an ultra-tiny

1.9mm x 2.2mm WLP package and an 8-pin µMAX

package. These ADCs are guaranteed over the extend-

ed temperature range (-40°C to +85°C). For pin-com-

patible 12-bit parts, refer to the MAX11644/MAX11645

data sheet.

Applications

Handheld Portable Applications

Medical Instruments

Battery-Powered Test Equipment

Power-Supply Monitoring

Solar-Powered Remote Systems

Received-Signal-Strength Indicators

System Supervision

Features

♦ Ultra-Tiny 1.9mm x 2.2mm Wafer Level Package

♦ High-Speed I

C-Compatible Serial Interface

400kHz Fast Mode

1.7MHz High-Speed Mode

♦ Single Supply

2.7V to 3.6V (MAX11647)

4.5V to 5.5V (MAX11646)

♦ Internal Reference

2.048V (MAX11647)

4.096V (MAX11646)

♦ External Reference: 1V to V

♦ Internal Clock

♦ 2-Channel Single-Ended or 1-Channel Fully

Differential

♦ Internal FIFO with Channel-Scan Mode

♦ Low Power

670µA at 94.4ksps

230µA at 40ksps

60µA at 10ksps

6µA at 1ksps

0.5µA in Power-Down Mode

♦ Software-Configurable Unipolar/Bipolar

MAX11646/MAX11647

Low-Power, 1-/2-Channel, I

C, 10-Bit ADCs

in Ultra-Tiny 1.9mm x 2.2mm Package

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-5134; Rev 1; 9/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE

PIN-

PACKAGE

C SLAVE

ADDRESS

MAX11646EUA+ -40°C to +85°C 8 μMAX 0110110

MAX11647EUA+ -40°C to +85°C 8 μMAX 0110110

MAX11647EWC+ -40°C to +85°C 12 WLP 0110110

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Denotes a lead(Pb)-free/RoHs-compliant package.

Typical Operating Circuit and Selector Guide appear at end

of data sheet.

Summary of content (22 pages)

PAGE 1
9-5134; Rev 1; 9/10 KIT ATION EVALU E L B AVAILA Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The MAX11646/MAX11647 low-power, 10-bit, 1-/2channel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, a clock, and an I 2 C-compatible 2-wire serial interface. These devices operate from a single supply of 2.7V to 3.6V (MAX11647) or 4.5V to 5.5V (MAX11646) and require only 6µA at a 1ksps sample rate.
PAGE 2
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package ABSOLUTE MAXIMUM RATINGS Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) µMAX only ....................................................................+300°C Soldering Temperature (reflow) .................
PAGE 3
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package (VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN Internal Clock Frequency Aperture Delay (Note 6) TYP MAX 2.
PAGE 4
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.01 ±0.
PAGE 5
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package (VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) (Note 1) PARAMETER SYMBOL CONDITIONS MAX UNITS 20 80 ns Measured from 0.3VDD to 0.7VDD 20 160 ns Rise Time of SCL Signal (Current Source Enabled) tRCL Measured from 0.
PAGE 6
Typical Operating Characteristics (VDD = 3.3V (MAX11647), VDD = 5V (MAX11646), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.4 0.3 -0.1 AMPLITUDE (dBc) INL (LSB) 0.1 0 -0.1 -0.2 -140 200 400 600 800 400 600 800 0 1000 20k 30k 40k FREQUENCY (Hz) SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs.
PAGE 7
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 1.00004 -0.1 -0.2 1.00000 0.99998 0.99996 0.99994 0.99992 MAX11646 toc10 MAX11646, NORMALIZED TO REFERENCE VALUE AT VDD = 5V 1.00002 MAX11647, NORMALIZED TO REFERENCE VALUE AT VDD = 3.3V -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 0.99990 -40 -25 -10 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5 20 35 50 65 80 TEMPERATURE (°C) VDD (V) OFFSET ERROR vs.
PAGE 8
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package MAX11646/MAX11647 Pin Configuration TOP VIEW (BUMPS ON BOTTOM) 1 3 4 MAX11647 TOP VIEW + AIN0 1 AIN1 2 N.C. 2 3 MAX11646 MAX11647 REF 4 8 VDD 7 GND 6 SDA 5 SCL µMAX A AIN0 AIN1 GND REF B GND GND GND GND C VDD GND SDA SCL WLP Pin Description PIN 8 NAME μMAX WLP 1,2 A1, A2 AIN0, AIN1 3 — N.C. FUNCTION Analog Inputs No connection. Not internally connected.
PAGE 9
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package tR tF MAX11646/MAX11647 A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING t SDA tSU:DAT tHD:DAT tLOW tHD:STA tBUF tSU:STA tSU:STO SCL tHD:STA tHIGH tR tF S A Sr P B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING S tRDA tFDA SDA tSU:DAT tHD:DAT tLOW tBUF tHD:STA tSU:STO tSU:STA SCL tHD:STA tHIGH tRCL tFCL tRCL1 S Sr HS MODE A P S F/S MODE Figure 1.
PAGE 10
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package SDA SCL INPUT SHIFT REGISTER VDD CONTROL LOGIC SETUP REGISTER GND INTERNAL OSCILLATOR CONFIGURATION REGISTER AIN0 AIN1 10-BIT ADC T/H ANALOG INPUT MUX REF OUTPUT SHIFT REGISTER AND RAM REF REFERENCE 4.096V (MAX11646) 2.048V (MAX11647) MAX11646 MAX11647 Figure 2. Functional Diagram Power Supply VDD IOL VOUT SDA 400pF IOH Figure 3.
PAGE 11
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: Sufficiently low source impedance is required to ensure an accurate sample.
PAGE 12
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Single-Ended/Differential Input The SGL/DIF of the configuration byte configures the MAX11646/MAX11647 analog input circuitry for singleended or differential inputs (Table 2). In single-ended mode (SGL/DIF = 1), the digital conversion results are the difference between the analog input selected by CS0 and GND (Table 3).
PAGE 13
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package SLAVE ADDRESS 0110110 SLAVE ADDRESS S 0 1 1 0 1 1 0 R/W A SDA 1 SCL 2 3 4 5 6 7 8 9 Figure 7. Slave Address Byte Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address. When idle, the MAX11646/MAX11647 continuously wait for a START condition followed by their slave address.
PAGE 14
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by 7 address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX11646/MAX11647 (slave) issue an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table 1) if the most significant bit (MSB) is 1.
PAGE 15
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package MAX11646/MAX11647 Table 2. Configuration Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SCAN1 SCAN0 X X X CS0 SGL/DIF BIT NAME 7 REG 6 SCAN1 5 SCAN0 4 X 3 X 2 X 1 CS0 0 SGL/DIF DESCRIPTION Register bit. 1= setup byte (see Table 1), 0 = configuration byte. Scan-select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.
PAGE 16
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Internal Clock When configured for internal clock mode (CLK = 0), the MAX11646/MAX11647 use their internal oscillator as the conversion clock. In internal clock mode, the MAX11646/MAX11647 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins.
PAGE 17
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The MAX11646/MAX11647 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps internal clock mode is recommended due to much smaller power consumption. Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. The scanned results are written to memory in the same order as the conversion.
PAGE 18
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Applications Information Power-On Reset The configuration and setup registers (Tables 1 and 2) default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference. The memory contents are unknown after power-up. Automatic Shutdown Automatic shutdown occurs between conversions when the MAX11646/MAX11647 are idle.
PAGE 19
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Layout, Grounding, and Bypassing Only use PCBs. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package.
PAGE 20
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Differential Nonlinearity Effective Number of Bits Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate.
PAGE 21
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Selector Guide 3.3V or 5V PART 0.1μF VDD RS* ANALOG INPUTS AIN0 AIN1 MAX11646 2 SingleEnded/1 Differential 4.096 4.5 to 5.5 ±1 MAX11647 2 SingleEnded/1 Differential 2.048 2.7 to 3.6 ±1 SDA MAX11646 MAX11647 SCL RS* INTERNAL SUPPLY INPUT INL REFERENCE VOLTAGE CHANNELS (LSB) (V) (V) RC NETWORK* 2kΩ CREF 0.
PAGE 22
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package Revision History REVISION NUMBER REVISION DATE 0 1/10 Initial release 1 9/10 Added the WLP package to the Ordering Information, Absolute Maximum Ratings, Pin Configuration, Pin Description, and Package Information sections DESCRIPTION PAGES CHANGED — 1, 2, 8, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.