Datasheet

Figure 10. Timing Diagram for Data Out Reading After Conversion
Figure 9. DIN Timing for Register Write Operations
MSB
MSB-1 MSB-2DOUT
t
3
t
4
SCLK
t
12
t
5
0.7 x OVDD
0.3 x OVDD
t
6
t
8
t
11
t
7
0.7 x OVDD
0.3 x OVDD
0.7 x OVDD
0.7 x OVDD
t
10
t
9
0.7 x OVDD
t
13
CNVST
0.7 x OVDD
t
1
t
2
0.7 x OVDD
SCLK
0.3 x OVDD
DIN
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Maxim Integrated │ 21
MAX11901 16-Bit, 1.6Msps, Low-Power,
Fully Differential SAR ADC