Datasheet

(f
SAMPLE
= 1.6Msps, V
AVDD
= 1.8V, V
DVDD
= 1.8V, V
OVDD
= 1.5V to 3.6V, V
REFVDD
= 3.6V, V
REF
= 3.3V, Internal Ref Buffers On,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
Note 2: Limits are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3: See the Analog Inputs section.
Note 4: See the Definitions section at the end of the data sheet.
Note 5: See the Definitions section at the end of the data sheet. Error contribution from the external reference not included.
Note 6: Parameter is guaranteed by design.
Note 7: Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage.
Note 8: Sine wave input, f
IN
= 10kHz, A
IN
= -0.5dB below full scale.
Note 9: C
LOAD
= 10pF on DOUT. f
CONV
= 1.6Msps. All data is read out.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING
DIN to SCLK Rising Edge
Setup
t
1
4 ns
DIN to SCLK Rising Edge Hold t
2
1 ns
DOUT End-Of-Conversion
Low Time
t
3
10 ns
DOUT to SCLK Rising
Edge Hold
t
4
2.5 ns
DOUT to SCLK Rising
Edge Setup
t
5
100MHz SCLK 1.5 ns
SCLK High t
6
4.5 ns
SCLK Period t
7
10 ns
SCLK Low t
8
4.5 ns
CNVST Rising Edge To SCLK
Rising Edge
t
9
0 ns
SCLK Rising Edge to CNVST
Rising Edge
t
10
25 ns
CNVST High t
11
20 ns
CNVST High to EOC t
12
525 ns
Conversion Period t
13
625 ns
www.maximintegrated.com
Maxim Integrated │ 7
MAX11901 16-Bit, 1.6Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)