Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFN 28

General Description

The MAX1191 is an ultra-low-power, dual, 8-bit,

7.5Msps analog-to-digital converter (ADC). The device

features two fully differential wideband track-and-hold

(T/H) inputs. These inputs have a 440MHz bandwidth

and accept fully differential or single-ended signals.

The MAX1191 delivers a typical signal-to-noise and dis-

tortion (SINAD) of 48.6dB at an input frequency of

1.875MHz and a sampling rate of 7.5Msps while con-

suming only 12mW. This ADC operates from a 2.7V to

3.6V analog power supply. A separate 1.8V to 3.6V

supply powers the digital output driver. In addition to

ultra-low operating power, the MAX1191 features three

power-down modes to conserve power during idle peri-

ods. Excellent dynamic performance, ultra-low power,

and small size make the MAX1191 ideal for applica-

tions in imaging, instrumentation, and digital communi-

cations.

An internal 1.024V precision bandgap reference sets

the full-scale range of the ADC to ±0.512V. A flexible

reference structure allows the MAX1191 to use its inter-

nal reference or accept an externally applied reference

for applications requiring increased accuracy.

The MAX1191 features parallel, multiplexed, CMOS-

compatible tri-state outputs. The digital output format is

offset binary. A separate digital power input accepts a

voltage from 1.8V to 3.6V for flexible interfacing to dif-

ferent logic levels. The MAX1191 is available in a 5mm

× 5mm, 28-pin thin QFN package, and is specified for

the extended industrial (-40°C to +85°C) temperature

range.

For higher sampling frequency applications, refer to the

MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible

versions of the MAX1191 are also available. Refer to the

MAX1192 data sheet for 22Msps, and the MAX1193

data sheet for 45Msps.

Applications

Ultrasound and Medical Imaging

IQ Baseband Sampling

Battery-Powered Portable Instruments

Low-Power Video

WLAN, Mobile DSL, WLL Receiver

Features

♦ Ultra-Low Power

12mW (Normal Operation: 7.5Msps)

0.3µW (Shutdown Mode)

♦ Excellent Dynamic Performance

48.7dB SNR at f

= 1.875MHz

69dBc SFDR at f

= 1.875MHz

♦ 2.7V to 3.6V Single Analog Supply

♦ 1.8V to 3.6V TTL/CMOS-Compatible Digital

Outputs

♦ Fully Differential or Single-Ended Analog Inputs

♦ Internal/External Reference Option

♦ Multiplexed CMOS-Compatible Tri-State Outputs

♦ 28-Pin Thin QFN Package

♦ Evaluation Kit Available (Order MAX1193EVKIT)

MAX1191

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

________________________________________________________________ Maxim Integrated Products 1

MAX1191

5mm x 5mm THIN QFN

TOP VIEW

INA+

EXPOSED PADDLE

INA-

GND

CLK

GND

INB+

INB-

REFP

REFN

COM

REFIN

PD0

PD1

A/B

OGND

GND

Pin Configuration

Ordering Information

19-2836; Rev 1; 9/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1191ETI-T -40°C to +85°C

28 Thin QFN-EP*

(5mm x 5mm)

*EP = Exposed paddle.

Summary of content (27 pages)

PAGE 1
9-2836; Rev 1; 9/03 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ♦ Ultra-Low Power 12mW (Normal Operation: 7.5Msps) 0.3µW (Shutdown Mode) ♦ Excellent Dynamic Performance 48.7dB SNR at fIN = 1.875MHz 69dBc SFDR at fIN = 1.875MHz ♦ 2.7V to 3.6V Single Analog Supply ♦ 1.8V to 3.
PAGE 2
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .................-0.3V to (VDD + 0.3V) CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (VDD + 0.3V) PD0, PD1 to OGND .................................-0.3V to (OVDD + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVDD + 0.
PAGE 3
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 1.875MHz MIN TYP 59 69 MAX UNITS Spurious-Free Dynamic Range (Note 2) SFDR Third-Harmonic Distortion (Note 2) HD3 Intermodulation Distortion IMD fIN1 = 1MHz at -7dB FS, fIN2 = 1.
PAGE 4
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Maximum REFP/REFN/COM Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS 2 mA REFIN Input Resistance >500 kΩ REFIN Input Current -0.
PAGE 5
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Supply Current Digital Output Supply Current (Note 3) SYMBOL IDD IODD TYP MAX Normal operating mode, fIN = 1.875MHz at -0.5dB FS, CLK input from GND to VDD CONDITIONS MIN 4.0 5.0 Idle mode (tri-state), fIN = 1.
PAGE 6
ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.
PAGE 7
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) -20 -30 -40 -50 HD2 -60 HD3 fINB -30 -40 -50 fINA HD2 -60 -70 -70 -80 -80 -90 HD3 -90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs.
PAGE 9
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER fIN = 2.017059MHz 50 fIN = 2.
PAGE 10
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE 50 fIN = 2.017059MHz 49 SINAD (dB) 49 48 47 46 48 47 46 45 45 5 10 15 20 0 5 10 15 fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. SAMPLING RATE SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 11
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. CLOCK DUTY CYCLE SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE fIN = 2.017059MHz 49 SINAD (dB) 49 48 47 48 47 46 46 45 45 45 50 55 45 50 55 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%) TOTAL HARMONIC DISTORTION vs.
PAGE 12
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY 0.3 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 32 64 96 128 160 192 224 256 0 32 64 OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE VREFIN = 1.
PAGE 13
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SAMPLING RATE SUPPLY CURRENT vs. INPUT FREQUENCY 0.7 4.1 ANALOG SUPPLY CURRENT 0.6 4.0 0.5 3.9 0.4 1 2 3 A 5 4 B 3 C 2 1 0 3.8 0 MAX1191 toc35 4.2 fIN = 2.
PAGE 14
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Pin Description (continued) PIN NAME 23 PD0 FUNCTION 24 REFIN 25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 26 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. 27 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33µF capacitor. — EP Power-Down Digital Input 0. See Table 3. Reference Input.
PAGE 15
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC MAX1191 INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b COM INTERNAL BIAS HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 MAX1191 OUT INBS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM Figure 3. Internal T/H Circuits Input Track-and-Hold (T/H) Circuits Figure 3 displays a simplified functional diagram of the input T/H circuits.
PAGE 16
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Table 1. Reference Modes VREFIN REFERENCE MODE >0.8 x VDD Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. <0.
PAGE 17
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC MAX1191 5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB) CHA CHB tCLK tCL tCH CLK tDOB A/B tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB D0B D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B tDA/B D0–D7 Figure 5. System Timing Diagram provide lowest possible jitter.
PAGE 18
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Table 2. Output Codes vs.
PAGE 19
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC R5 600Ω MAX1191 RISO 22Ω R1 600Ω VCOM = 0.5V TO 1.5V VSIG = ±85mVP-P R2 300Ω R3 600Ω MAX1191 R4 600Ω INACIN 5pF R6 600Ω R7 600Ω COM AV = 6V/V VCOM = VDD/2 R8 600Ω R9 600Ω RISO 22Ω CIN 5pF R10 600Ω OPERATIONAL AMPLIFIERS CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/ DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A 0.
PAGE 20
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC REFP 25Ω INA+ 22pF 1kΩ VIN 0.1µF 1 VIN T1 RISO 50Ω 6 INA+ MAX4108 2 5 3 4 N.C. 0.1µF 100Ω 1kΩ COM 2.2µF CIN 22pF 0.1µF COM REFN MINICIRCUITS TT1-6-KK81 0.1µF RISO 50Ω 25Ω INA- INA- 100Ω CIN 22pF 22pF MAX1191 REFP 25Ω MAX1191 INB+ 22pF VIN 0.1µF 1 VIN N.C. T1 0.1µF RISO 50Ω 6 INB+ MAX4108 2 5 3 4 100Ω 2.2µF 1kΩ CIN 22pF 0.1µF REFN MINICIRCUITS TT1-6-KK81 0.1µF RISO 50Ω 25Ω INB22pF Figure 8.
PAGE 21
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC MAX1191 3V 24 0.1µF 1.248V VDD REFIN 0.1µF 1 2 27 MAX6061 3 10Hz LOWPASS FILTER REFP N=1 0.33µF 1% 20kΩ MAX1191 26 REFN 0.33µF 1µF 1% 90.9kΩ 25 3V 5 3 NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES ±15mA OF OUTPUT DRIVE AND SUPPORTS OVER 1000 MAX1191s. MAX4250 4 COM GND 0.33µF 0.1µF 1 15Ω 2 1.023V 24 VDD REFIN 0.1µF 2.2µF 0.1µF 27 REFP N = 1000 0.33µF MAX1191 26 REFN 0.33µF 25 COM 0.33µF GND Figure 10.
PAGE 22
MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC 3V 2.500V 1 0.1µF 2 27 MAX6066 1% 30.1kΩ 3 3 10µF 6V 0.1µF 12 1MΩ 13 14 MAX4254 1.47kΩ 10µF 6V 24 COM GND 0.1µF 27 330µF 6V 1.47kΩ VDD REFP N = 160 0.33µF 47Ω 8 MAX4254 10µF 6V 2.2µF 1.47kΩ 1.248V 1/4 11 25 0.33µF 330µF 6V 10 9 REFIN 47Ω 7 1% 10.0kΩ 4 1/4 330µF 6V MAX4254 3V UNCOMMITTED MAX1191 1.498V 1/4 1MΩ REFN 0.33µF 1% 10.
PAGE 23
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC INA+ INA0° 90° MAX1191 DSP POSTPROCESSING INB+ INBDOWNCONVERTER ÷8 Figure 12. Typical QAM Receiver Application Typical QAM Demodulation Application Quadrature amplitude modulation (QAM) is frequently used in digital communications. Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase.
PAGE 24
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC MAX1191 Dynamic Parameter Definitions Aperture Jitter CLK Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. ANALOG INPUT Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13). tAD tAJ SAMPLED DATA (T/H) T/H Signal-to-Noise Ratio (SNR) TRACK HOLD TRACK Figure 13.
PAGE 25
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Third-Order Intermodulation (IM3) IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 ±f2), (2 x f2 ±f1). The individual input tone levels are at -7dB FS.
PAGE 26
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) D2 0.15 C A D b CL 0.10 M C A B D2/2 D/2 PIN # 1 I.D. QFN THIN.EPS MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC k 0.15 C B PIN # 1 I.D. 0.35x45 E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e CL CL L L e e 0.10 C A C 0.
PAGE 27
Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC COMMON DIMENSIONS EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.